专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US09337093B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09337093B2
公开(公告)日：2016-05-10
申请号：US13182944
申请日：2011-07-14
申请人： Daisuke Oshida , Ippei Kume , Makoto Ueki , Manabu Iguchi , Naoya Inoue , Takuya Maruyama , Toshiji Taiji , Hirokazu Katsuyama
发明人： Daisuke Oshida , Ippei Kume , Makoto Ueki , Manabu Iguchi , Naoya Inoue , Takuya Maruyama , Toshiji Taiji , Hirokazu Katsuyama
IPC分类号： H01L21/283 , H01L21/768 , H01L21/3105 , H01L23/532 , H01L21/02
CPC分类号： H01L21/76883 , H01L21/02126 , H01L21/02216 , H01L21/3105 , H01L21/76805 , H01L21/76807 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L21/76843 , H01L21/76865 , H01L21/76873 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device includes an insulating film that is formed using a cyclic siloxane having a six-membered ring structure as a raw material; a trench that is formed in the insulating film; and a interconnect that is configured by a metal film embedded in the trench. In the semiconductor device, a modified layer is formed on a bottom surface of the trench, in which the number of carbon atoms and/or the number of nitrogen atoms per unit volume is larger than that inside the insulating film.
摘要翻译：半导体器件包括使用具有六元环结构的环状硅氧烷作为原料形成的绝缘膜; 在绝缘膜中形成的沟槽; 以及由嵌入在沟槽中的金属膜构成的互连。在半导体装置中，在沟槽的底面上形成改性层，其中每单位体积的碳原子数和/或氮原子数大于绝缘膜内部。

52. 发明授权

US09305840B2 Cluster system for eliminating barrier overhang 有权
标题翻译：用于消除障碍突出的簇系统
公开(公告)号：US09305840B2
公开(公告)日：2016-04-05
申请号：US14138038
申请日：2013-12-21
申请人： Macronix International Co., Ltd.
发明人： Hsu-Sheng Yu , Hong-Ji Lee , N. T. Lian , T. H. Yang
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/67
CPC分类号： H01L21/76879 , H01L21/67207 , H01L21/76843 , H01L21/76865 , H01L21/76877 , H01L23/5226 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： A cluster tool is disclosed that can increase throughput of a wafer fabrication process by facilitating removal of barrier overhang in contact holes of contact film stacks. Individual chambers of the cluster tool provide for deposition of barrier material onto a semiconductor structure, depositing over with an amorphous carbon film (ACF), etching back the ACF, and etching a corner region of the contact hole. Removal of the barrier overhang improves the quality of metal fill-in of the contact hole. An expectedly ensuing feature entails a technique in which filling-in of the contact hole with a metal such as tungsten can be achieved with attenuated or eliminated adverse consequence.
摘要翻译：公开了一种集群工具，其可以通过有助于去除接触膜堆叠的接触孔中的阻挡突出部来增加晶片制造工艺的生产量。集群工具的单个室提供阻挡材料沉积到半导体结构上，用无定形碳膜（ACF）沉积，对ACF进行蚀刻，并蚀刻接触孔的拐角区域。阻挡突出部的移除提高了接触孔的金属填充质量。预期的随后特征需要一种技术，其中可以通过减弱或消除不利后果来实现用诸如钨的金属填充接触孔。

53. 发明申请

US20160013100A1 VIA STRUCTURE AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：通过其结构和形成方法
公开(公告)号：US20160013100A1
公开(公告)日：2016-01-14
申请号：US14461433
申请日：2014-08-17
申请人： UNITED MICROELECTRONICS CORP.
发明人： Kun-Ju Li , Po-Cheng Huang , Chih-Chien Liu , Yu-Ting Li , Jen-Chieh Lin , Chang-Hung Kung , Wen-Chin Lin , Chih-Hsun Lin , Kuo-Chin Hung
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76843 , H01L21/32136 , H01L21/3215 , H01L21/76859 , H01L21/76865 , H01L21/76874 , H01L21/76879 , H01L29/41791 , H01L29/66545 , H01L29/6656 , H01L29/66795
摘要： A via structure and a method of forming the same are provided. In the forming method of the present invention, a via is formed in a dielectric layer. Next, a U-shaped seed layer is formed in the via. After that, a conductive material is selectively formed in the via to form a conductive bulk layer in the via. Through the present invention, the purposes of effectively removing the overhang adjacent to the opening of the via and protecting the U-shaped seed layer in the via can be achieved.
摘要翻译：提供通孔结构及其形成方法。在本发明的形成方法中，在电介质层中形成通孔。接下来，在通孔中形成U形种子层。之后，在通路中选择性地形成导电材料，以在通孔中形成导电体层。通过本发明，可以实现有效地去除邻近通孔开口的突出端并保护通孔中的U形种子层的目的。

54. 发明申请

US20150349083A1 METHODS OF FORMING MIS CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES AND THE RESULTING DEVICES 有权
标题翻译：形成半导体器件和结果器件的接触结构的方法
公开(公告)号：US20150349083A1
公开(公告)日：2015-12-03
申请号：US14289737
申请日：2014-05-29
申请人： GLOBALFOUNDRIES Inc. , International Business Machines Corporation
发明人： Ruilong Xie , Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz
IPC分类号： H01L29/51 , H01L29/66 , H01L21/3213 , H01L49/02 , H01L21/02 , H01L29/78 , H01L29/49
CPC分类号： H01L23/535 , H01L21/0214 , H01L21/0217 , H01L21/285 , H01L21/32133 , H01L21/32139 , H01L21/76805 , H01L21/76816 , H01L21/76831 , H01L21/76838 , H01L21/7684 , H01L21/76843 , H01L21/76865 , H01L21/76877 , H01L21/76895 , H01L23/485 , H01L23/5283 , H01L23/53266 , H01L29/6659 , H01L29/66643 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： One method disclosed includes, among other things, conformably depositing a layer of contact insulating material and a conductive material layer in a contact opening, forming a reduced-thickness sacrificial material layer in the contact opening so as to expose a portion, but not all, of the conductive material layer, removing portions of the conductive material layer and the layer of contact insulating material positioned above the upper surface of the reduced-thickness sacrificial material layer, removing the reduced-thickness sacrificial material layer, and forming a conductive contact in the contact opening that contacts the recessed portions of the conductive material layer and the layer of contact insulating material.
摘要翻译：所公开的一种方法包括在接触开口中顺应地沉积接触绝缘材料层和导电材料层，在接触开口中形成减小厚度的牺牲材料层，以暴露部分，但不是全部，的导电材料层的去除部分，去除部分导电材料层和接触绝缘材料层位于减薄厚度的牺牲材料层的上表面之上，去除减薄的牺牲材料层，并在其中形成导电接触接触开口，其接触导电材料层的凹部和接触绝缘材料层。

55. 发明申请

US20150318205A1 METHOD FOR FORMING INTERCONNECTION STRUCTURES 有权
标题翻译：形成互连结构的方法
公开(公告)号：US20150318205A1
公开(公告)日：2015-11-05
申请号：US14647706
申请日：2012-11-27
申请人： ACM RESEARCH (SHANGHAI) INC.
发明人： Jian Wang , Zhaowei Jia , Hui Wang
IPC分类号： H01L21/768
CPC分类号： H01L21/76843 , H01L21/32115 , H01L21/76802 , H01L21/7684 , H01L21/76865 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for forming interconnection structures, including the following steps: providing a semiconductor wafer with a dielectric layer; forming a first recessed area for forming the interconnection structures and a non-recessed area on the dielectric layer; forming a second recessed area for forming dummy structures on the dielectric layer; depositing a barrier layer to cover the first and second recessed areas and the non-recessed area; depositing a metal layer to fill the first and second recessed areas and cover the non-recessed area; removing the metal layer on the non-recessed area to expose the barrier layer; and removing the barrier layer on the non-recessed area to expose the dielectric layer.
摘要翻译：本发明提供一种用于形成互连结构的方法，包括以下步骤：向半导体晶片提供介电层; 形成用于形成所述互连结构的第一凹陷区域和所述电介质层上的非凹陷区域; 形成用于在所述电介质层上形成虚设结构的第二凹陷区域; 沉积阻挡层以覆盖第一和第二凹陷区域和非凹陷区域; 沉积金属层以填充第一和第二凹陷区域并覆盖非凹陷区域; 去除非凹陷区域上的金属层以暴露阻挡层; 以及去除所述非凹陷区域上的所述阻挡层以暴露所述介电层。

56. 发明申请

US20150315419A1 POLISHING SLURRY FOR CMP AND POLISHING METHOD 审中-公开
标题翻译：抛光浆料用于CMP和抛光方法
公开(公告)号：US20150315419A1
公开(公告)日：2015-11-05
申请号：US14799971
申请日：2015-07-15
申请人： HITACHI CHEMICAL COMPANY, LTD.
发明人： Takashi Shinoda , Shigeru Nobe , Takafumi Sakurada , Yoshikazu Oomori , Tadahiro Kimura
IPC分类号： C09G1/02 , H01L21/768 , H01L21/3105 , H01L21/321
CPC分类号： C09G1/02 , C23F3/04 , H01L21/30625 , H01L21/31055 , H01L21/3212 , H01L21/32125 , H01L21/7684 , H01L21/76865
摘要： The invention provides polishing slurry for CMP for suppressing corrosion of wiring lines of a conductive substance, or for suppressing bimetallic corrosion of a barrier conductor and conductive substance, by suppressing electrons from being transferred at near the boundaries between a barrier conductor and a conductive substance such as copper. The invention provides polishing slurry for CMP for polishing at least a conductor layer and a conductive substance layer in contact with the conductor layer, wherein the absolute value of the potential difference between the conductive substance and the conductor at 50±5° C. is 0.25 V or less in the polishing slurry when a positive electrode and a negative electrode of a potentiometer are connected to the conductive substance and the conductor, respectively. The polishing slurry for CMP preferably comprises at least one compound selected from heterocyclic compounds containing any one of hydroxyl group, carbonyl group, carboxyl group, amino group, amide group and sulfinyl group, and containing at least one of nitrogen and sulfur atoms.
摘要翻译：本发明提供了通过抑制电子在阻挡导体和导电物质之间的边界附近转移而抑制导电物质的布线的腐蚀或抑制阻挡导体和导电物质的双金属腐蚀的CMP抛光浆料，例如作为铜。本发明提供了用于CMP的抛光浆料，用于至少对与导体层接触的导体层和导电物质层进行抛光，其中在50±5℃下导电物质与导体之间的电位差的绝对值为0.25 当电位计的正电极和负电极分别连接到导电物质和导体时，抛光浆料中的V或更小。用于CMP的抛光浆料优选包含至少一种选自含有羟基，羰基，羧基，氨基，酰胺基和亚磺酰基中的任何一种的杂环化合物并且含有氮和硫原子中的至少一个的化合物。

57. 发明授权

US09175404B2 Etching agent for copper or copper alloy 有权
标题翻译：铜或铜合金蚀刻剂
公开(公告)号：US09175404B2
公开(公告)日：2015-11-03
申请号：US14348115
申请日：2012-09-28
申请人： ADVANCED TECHNOLOGY MATERIALS, INC.
发明人： Tsutomu Kojima , Yukichi Koji
IPC分类号： C23F3/00 , C23F1/18 , H01L21/3213 , C23F1/34 , C23F1/44 , H01L23/00 , H01L21/768 , H01L23/48
CPC分类号： C23F1/18 , C23F1/34 , C23F1/44 , H01L21/32134 , H01L21/76865 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/03614 , H01L2224/03826 , H01L2224/03912 , H01L2224/0401 , H01L2224/05027 , H01L2224/05166 , H01L2224/05572 , H01L2224/05647 , H01L2224/1146 , H01L2224/1147 , H01L2224/13009 , H01L2224/13083 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2924/00014 , H01L2924/12044 , H01L2924/1461 , H01L2924/01079 , H01L2924/00 , H01L2224/05552
摘要： Object is to provide an etching solution which generates less foam and can etch copper or copper alloy at high selectivity when used in a step of etching copper or copper alloy in an electronic substrate having both of copper or copper alloy and nickel.The etching solution to be used in a step of selectively etching copper or copper alloy in an electronic substrate having both of copper or copper alloy and nickel has, as essential components thereof, (A) a linear alkanolamine, (B) a chelating agent having an acid group in the molecule thereof, and (C) hydrogen peroxide.
摘要翻译：目的在于提供一种在具有铜或铜合金和镍两者的电子基板中蚀刻铜或铜合金的步骤中，以高选择性产生较少泡沫并可以蚀刻铜或铜合金的蚀刻溶液。在具有铜或铜合金和镍的电子基板中选择性蚀刻铜或铜合金的步骤中使用的蚀刻溶液作为其主要组分，（A）直链烷醇胺，（B）螯合剂，其具有分子中的酸基，和（C）过氧化氢。

58. 发明申请

US20150311117A1 Method Of Forming Chip With Through Silicon Via Electrode 有权
标题翻译：通过电极形成芯片的方法
公开(公告)号：US20150311117A1
公开(公告)日：2015-10-29
申请号：US14791265
申请日：2015-07-03
申请人： UNITED MICROELECTRONICS CORP.
发明人： Ming-Tse Lin , Chu-Fu Lin , Chien-Li Kuo , Yung-Chang Lin
IPC分类号： H01L21/768 , H01L23/00 , H01L21/302 , H01L21/283
CPC分类号： H01L21/76898 , H01L21/283 , H01L21/302 , H01L21/7685 , H01L21/76865 , H01L21/76871 , H01L21/76883 , H01L23/481 , H01L23/49827 , H01L23/5226 , H01L24/03 , H01L24/16 , H01L28/60 , H01L2224/02317 , H01L2224/0401 , H01L2224/4824 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening.
摘要翻译：本发明提供一种用TSV电极形成芯片的方法。提供具有第一表面和第二表面的基底。从第二表面的一侧进行变薄处理，使得第二表面变成第三表面。接下来，在衬底中形成穿过第一表面和第三表面的穿透。图案化材料层形成在衬底上，其中图案化材料层具有开口以暴露穿透通孔。导电层形成在第三表面上，从而同时在穿透孔中形成TSV电极和开口中的表面导电层。

59. 发明申请

US20150279856A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150279856A1
公开(公告)日：2015-10-01
申请号：US14453403
申请日：2014-08-06
申请人： SK hynix Inc.
发明人： Chan Sun HYUN , Myung Kyu AHN , Woo June KWON
IPC分类号： H01L27/115 , H01L23/532 , H01L21/768 , H01L23/528
CPC分类号： H01L27/11582 , G11C2213/71 , H01L21/76838 , H01L21/76841 , H01L21/76843 , H01L21/76865 , H01L21/76871 , H01L21/76876 , H01L21/76877 , H01L21/76879 , H01L21/76895 , H01L21/8221 , H01L23/528 , H01L23/53257 , H01L23/53266 , H01L27/0688 , H01L27/11524 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/1157 , H01L27/11575 , H01L27/2481 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.
摘要翻译：半导体器件包括彼此层叠并间隔开的层间电介质，穿过层间电介质的沟道层，各自围绕要设置在层间电介质之间的沟道层的侧壁的线图案区域，沿着线路图案区域和沟道层的侧壁中的每一个，沿着每个线图案区域的第一区域的表面形成在阻挡图案上的反应防止图案，第一区域与沟道层相邻，保护填充在反应防止图案的第一区域中的图案，以及填充在每个线图案区域的第二区域中的第一金属层。

60. 发明申请

US20150255330A1 BARRIER-SEED TOOL FOR FINE-PITCHED METAL INTERCONNECTS 有权
标题翻译：用于精细金属互连的BARRIER-SEED工具
公开(公告)号：US20150255330A1
公开(公告)日：2015-09-10
申请号：US14196268
申请日：2014-03-04
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Ya-Lien Lee
IPC分类号： H01L21/768
CPC分类号： H01L21/76862 , H01J37/32422 , H01J37/32706 , H01L21/02063 , H01L21/02068 , H01L21/32136 , H01L21/76802 , H01L21/7681 , H01L21/76814 , H01L21/76816 , H01L21/7684 , H01L21/76843 , H01L21/76865 , H01L21/76871 , H01L21/76873 , H01L21/76879 , H01L23/5226 , H01L23/528 , H01L23/53238
摘要： A barrier seed tool is configured to clean trenches in a first chamber, line the trenches with a diffusion barrier layer, and form a copper seed layer over the diffusion barrier layer in a second chamber. The clean chamber is configured to reduce overhangs in the copper seed layer by producing a plasma comprising positively and negatively charged ions including halogen ions, filtering the plasma to selectively exclude positively charged ions, and bombarding with the filtered plasma. The tool and related method can be used to reduce overhangs and improve subsequent gap fill while avoiding excessive damage to the dielectric matrix.
摘要翻译：阻挡种子工具被配置为清洁第一室中的沟槽，将沟槽与扩散阻挡层对准，并在第二室中在扩散阻挡层上形成铜籽晶层。清洁室被配置为通过产生包括正离子和带负电荷的离子包括卤素离子，过滤等离子体以选择性地排除带正电荷的离子和用过滤的等离子体轰击来减少铜籽晶层中的悬垂。该工具和相关方法可用于减少悬垂并改善随后的间隙填充，同时避免对电介质基体的过度损坏。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式