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51. 发明申请

US20170098575A1 METHODS FOR DEPOSITING DIELECTRIC BARRIER LAYERS AND ALUMINUM CONTAINING ETCH STOP LAYERS 审中-公开
公开(公告)号：US20170098575A1
公开(公告)日：2017-04-06
申请号：US15285011
申请日：2016-10-04
申请人： APPLIED MATERIALS, INC.
发明人： Sree Rangasai V. KESAPRAGADA , Kevin MORAES , Srinivas GUGGILLA , He REN , Mehul NAIK , David THOMPSON , Weifeng YE , Yana CHENG , Yong CAO , Xianmin TANG , Paul F. MA , Deenesh PADHI
IPC分类号： H01L21/768 , H01L21/02
CPC分类号： H01L21/76832 , H01L21/02126 , H01L21/02167 , H01L21/02178 , H01L21/02211 , H01L21/02219 , H01L21/02266 , H01L21/02274 , H01L21/0228 , H01L21/3105 , H01L21/32 , H01L21/76826 , H01L21/76829 , H01L21/76834
摘要： In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

52. 发明申请

US20170084542A1 METHOD OF PROCESSING TARGET OBJECT 有权
公开(公告)号：US20170084542A1
公开(公告)日：2017-03-23
申请号：US15264737
申请日：2016-09-14
申请人： Tokyo Electron Limited
发明人： Kazuya Kato , Toshihiko Shindo , Ryuichi Asako , Hiroshi Nagahata
IPC分类号： H01L23/532 , H01L21/768 , H01L21/02 , H01L21/311
CPC分类号： H01L23/53238 , H01L21/02063 , H01L21/02115 , H01L21/02118 , H01L21/0212 , H01L21/02274 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76811 , H01L21/76813 , H01L21/76814 , H01L21/76826 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2221/1063
摘要： A plasma processing method can suppress both surface roughness of a wiring and surface roughness of a metal mask. The method includes generating plasma of a first processing gas containing a fluorocarbon gas and/or a hydrofluorocarbon gas to etch a diffusion barrier film until a copper wiring is exposed and generating plasma of a second processing gas containing a carbon-containing gas to form an organic film on a surface of a target object in which the diffusion barrier film is etched.

53. 发明申请

US20170069536A1 PLASMA TREATMENT METHOD AND METHOD OF MANUFACTURING ELECTRONIC COMPONENT 有权
标题翻译：等离子体处理方法及制造电子元件的方法
公开(公告)号：US20170069536A1
公开(公告)日：2017-03-09
申请号：US15245139
申请日：2016-08-23
申请人： Panasonic Intellectual Property Management Co., Ltd.
发明人： ATSUSHI HARIKAI , NORIYUKI MATSUBARA , HIDEO KANOU , MITSURU HIROSHIMA , SYOUZOU WATANABE , TOSHIHIRO WADA
IPC分类号： H01L21/78 , H01L21/308 , H01L21/3065
CPC分类号： H01L21/76826 , H01L21/78
摘要： Provided is a plasma treatment method including: placing a substrate carrier holding a substrate on a stage; adjusting a distance between a cover and the stage to a first distance in which the cover covers a frame without coming into contact with the substrate carrier; performing a plasma treatment on the substrate placed on the stage after the adjusting of the distance; carrying the substrate together with the substrate carrier out from a reaction chamber after the performing of the plasma treatment; and removing an adhered substance adhered to the cover by generating plasma in the inside of the reaction chamber after the carrying of the substrate, in which the distance between the cover and the stage in the removing of the adhered substance is a second distance greater than the first distance.
摘要翻译：提供了一种等离子体处理方法，包括：将保持衬底的衬底载体放置在平台上; 将盖和台架之间的距离调整到第一距离，其中盖子覆盖框架而不与基板载体接触; 在调整距离后，在放置在舞台上的基板上进行等离子体处理; 在执行等离子体处理之后将基板与基板载体一起从反应室中输出; 以及在承载基板之后，通过在反应室内部产生等离子体，除去附着在盖子上的附着物质，其中盖子和移除粘合物质的台阶之间的距离比第二距离大第一距离

54. 发明授权

US09580801B2 Enhancing electrical property and UV compatibility of ultrathin blok barrier film 有权
标题翻译：提高超薄屏障膜的电性能和紫外线相容性
公开(公告)号：US09580801B2
公开(公告)日：2017-02-28
申请号：US14535803
申请日：2014-11-07
申请人： Applied Materials, Inc.
发明人： Xiaolan Ba , Weifeng Ye , Mei-yee Shek , Yu Jin , Li-Qun Xia , Deenesh Padhi , Alexandros T. Demos
IPC分类号： H01L21/31 , C23C16/44 , C23C16/36 , C23C16/455 , C23C16/50 , C23C16/56 , H01L21/768 , H01L21/02
CPC分类号： C23C16/4408 , C23C16/36 , C23C16/45523 , C23C16/50 , C23C16/56 , H01L21/02167 , H01L21/76826 , H01L21/76832 , H01L21/76834
摘要： Embodiments described herein generally relate to the formation of a UV compatible barrier stack. Methods described herein can include delivering a process gas to a substrate positioned in a process chamber. The process gas can be activated to form an activated process gas, the activated process gas forming a barrier layer on a surface of the substrate, the barrier layer comprising silicon, carbon and nitrogen. The activated process gas can then be purged from the process chamber. An activated nitrogen-containing gas can be delivered to the barrier layer, the activated nitrogen-containing gas having a N2:NH3 ratio of greater than about 1:1. The activated nitrogen-containing gas can then be purged from the process chamber. The above elements can be performed one or more times to deposit the barrier stack.
摘要翻译：本文描述的实施方案通常涉及形成与UV相容的阻挡层叠体。本文所述的方法可以包括将处理气体输送到位于处理室中的基板。工艺气体可以被活化以形成活化的工艺气体，活化的工艺气体在衬底的表面上形成阻挡层，阻挡层包括硅，碳和氮。然后可以从处理室清除活化的工艺气体。可以将活化的含氮气体输送到阻挡层，活性含氮气体的N 2 :NH 3比率大于约1:1。然后可以将活化的含氮气体从处理室清除。上述元件可以执行一次或多次以沉积势垒堆叠。

55. 发明申请

US20170004976A1 Manufacturing Method of Semiconductor Device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：US20170004976A1
公开(公告)日：2017-01-05
申请号：US15267993
申请日：2016-09-16
申请人： Renesas Electronics Corporation
发明人： Kotaro HORIKOSHI , Toshikazu HANAWA , Masatoshi AKAISHI , Yuji KIKUCHI
IPC分类号： H01L21/311 , H01L21/768
CPC分类号： H01L21/31116 , H01L21/76802 , H01L21/76825 , H01L21/76826 , H01L21/76829
摘要： In order to provide a semiconductor device with high reliability while manufacturing cost is being suppressed, dry etching for an insulating film is performed by using mixed gas containing at least CF4 gas and C3H2F4 gas as its components.
摘要翻译：为了在抑制制造成本的同时提供高可靠性的半导体器件，通过使用至少包含CF 4气体和C 3 H 2 F 4气体的混合气体作为其组分，进行绝缘膜的干式蚀刻。

56. 发明申请

US20160379819A1 INTERCONNECT INTEGRATION FOR SIDEWALL PORE SEAL AND VIA CLEANLINESS 有权
标题翻译：侧壁密封和通过清洁度的互连整合
公开(公告)号：US20160379819A1
公开(公告)日：2016-12-29
申请号：US14750778
申请日：2015-06-25
申请人： Applied Materials, Inc.
发明人： He REN , Mehul B. NAIK , Deenesh PADHI , Priyanka DASH , Bhaskar KUMAR , Alexandros T. DEMOS
IPC分类号： H01L21/02
CPC分类号： H01L21/02126 , C23C16/045 , C23C16/36 , C23C16/482 , C23C16/56 , H01L21/02337 , H01L21/0234 , H01L21/02348 , H01L21/02359 , H01L21/3105 , H01L21/31058 , H01L21/76814 , H01L21/76825 , H01L21/76826 , H01L21/76831
摘要： A method for sealing porous low-k dielectric films is provided. The method comprises exposing a substrate to UV radiation and a first reactive gas, wherein the substrate has an open feature defined therein, the open feature defined by a porous low-k dielectric layer and a conductive material, wherein the porous low-k dielectric layer is a silicon and carbon containing material and selectively forming a pore sealing layer in the open feature on exposed surfaces of the porous low-k dielectric layer using UV assisted photochemical vapor deposition.
摘要翻译：提供了一种用于密封多孔低k电介质膜的方法。该方法包括将衬底暴露于UV辐射和第一反应气体，其中衬底具有限定在其中的开放特征，由多孔低k电介质层和导电材料限定的开放特征，其中多孔低k电介质层是含硅和碳的材料，并使用UV辅助光化学气相沉积在多孔低k电介质层的暴露表面上的开放特征中选择性地形成孔密封层。

57. 发明申请

US20160351441A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20160351441A1
公开(公告)日：2016-12-01
申请号：US15054855
申请日：2016-02-26
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Satoshi TSUKIYAMA , Motoshi SETO
IPC分类号： H01L21/768 , H01L23/528 , H01L23/522
CPC分类号： H01L21/76826 , H01L21/76814 , H01L21/76831 , H01L21/76898 , H01L23/481 , H01L23/53238 , H01L2224/11
摘要： According to an embodiment, a method of manufacturing a semiconductor device includes forming a first opening that extends from a second surface of a semiconductor substrate opposite to a first surface toward the first surface and extending to a first insulating layer in the semiconductor substrate, performing a first annealing process in a first gas atmosphere that contains hydrogen after formation of the first opening, forming a second insulating layer on a side wall of the semiconductor substrate in the first opening, performing a second annealing process after formation of the second insulating layer, forming a second opening that extends to the conductive layer in the first insulating layer through the first opening, and forming a via that is connected to the conductive layer in the first and second openings.
摘要翻译：根据实施例，制造半导体器件的方法包括形成从半导体衬底的与第一表面相对的第二表面朝向第一表面延伸并延伸到半导体衬底中的第一绝缘层的第一开口，执行在形成第一开口后在含有氢的第一气体气氛中进行第一退火处理，在第一开口中在半导体基板的侧壁上形成第二绝缘层，在形成第二绝缘层之后进行第二退火处理，形成第二开口，其通过第一开口延伸到第一绝缘层中的导电层，并形成连接到第一和第二开口中的导电层的通孔。

58. 发明授权

US09508549B2 Methods of forming electronic devices including filling porous features with a polymer 有权
标题翻译：形成电子器件的方法，包括用聚合物填充多孔特征
公开(公告)号：US09508549B2
公开(公告)日：2016-11-29
申请号：US14972522
申请日：2015-12-17
申请人： Rohm and Haas Electronic Materials LLC , Dow Global Technologies LLC
发明人： Jong Keun Park , Phillip D. Hustad , Emad Aqad , Mingqi Li , Cheng-Bai Xu , Peter Trefonas, III , James W. Thackeray
IPC分类号： H01L21/02
CPC分类号： H01L21/02359 , H01L21/02118 , H01L21/0212 , H01L21/02203 , H01L21/02343 , H01L21/3105 , H01L21/76826
摘要： Methods of forming an electronic device comprise: (a) providing a semiconductor substrate comprising a porous feature on a surface thereof; (b) applying a composition over the porous feature, wherein the composition comprises a polymer and a solvent, wherein the polymer comprises a repeat unit of the following general formula (I): wherein: Ar1, Ar2, Ar3 and Ar4 independently represent an optionally substituted divalent aromatic group; X1 and X2 independently represent a single bond, —O—, —C(O)—, —C(O)O—, —OC(O)—, —C(O)NR1—, —NR2C(O)—, —S—, —S(O)—, —SO2— or an optionally substituted C1-20 divalent hydrocarbon group, wherein R1 and R2 independently represent H or a C1-20 hydrocarbyl group; m is 0 or 1; n is 0 or 1; and o is 0 or 1; and (c) heating the composition; wherein the polymer is disposed in pores of the porous feature. The methods find particular applicability in the manufacture of semiconductor devices for forming low-k and ultra-low-k dielectric materials.

59. 发明申请

US20160343729A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20160343729A1
公开(公告)日：2016-11-24
申请号：US15142365
申请日：2016-04-29
申请人： Hyun-Jin SHIN , Hong-Suk KIM , Jung-Hwan KIM , Sang-Hoon LEE , Hun-Hyeong LIM , Yong-Seok CHO , Young-Dae KIM , Han-Vit YANG
发明人： Hyun-Jin SHIN , Hong-Suk KIM , Jung-Hwan KIM , Sang-Hoon LEE , Hun-Hyeong LIM , Yong-Seok CHO , Young-Dae KIM , Han-Vit YANG
IPC分类号： H01L27/115 , H01L21/768 , H01L21/02 , H01L21/28 , H01L21/3105 , H01L21/311
CPC分类号： H01L27/11582 , H01L21/0206 , H01L21/28273 , H01L21/28282 , H01L21/3105 , H01L21/31111 , H01L21/76826 , H01L21/76831 , H01L27/11521 , H01L27/11568
摘要： A method of manufacturing a semiconductor device, the method including forming a structure on a substrate, the structure including a metal pattern, at least a portion of the metal pattern being exposed; forming a preliminary buffer oxide layer to cover the structure, a metal oxide layer being formed at the exposed portion of the metal pattern; and deoxidizing the metal oxide layer so that the preliminary buffer oxide layer is transformed into a buffer oxide layer.
摘要翻译：一种制造半导体器件的方法，所述方法包括在衬底上形成结构，所述结构包括金属图案，所述金属图案的至少一部分被暴露; 形成预备的缓冲氧化物层以覆盖该结构，金属氧化物层形成在金属图案的暴露部分; 并且使金属氧化物层脱氧，使得预备缓冲氧化物层转变成缓冲氧化物层。

60. 发明申请

US20160343606A1 AIR GAP FORMING TECHNIQUES BASED ON ANODIC ALUMINA FOR INTERCONNECT STRUCTURES 有权
公开(公告)号：US20160343606A1
公开(公告)日：2016-11-24
申请号：US15224728
申请日：2016-08-01
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chia-Tien Wu , Tien-Lu Lin
IPC分类号： H01L21/768 , H01L23/532 , H01L23/528 , H01L21/02
CPC分类号： H01L21/7682 , H01L21/02178 , H01L21/02258 , H01L21/76807 , H01L21/76822 , H01L21/76826 , H01L21/76829 , H01L21/76843 , H01L21/76849 , H01L21/76877 , H01L23/5222 , H01L23/528 , H01L23/53228 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： An aluminum (Al) layer is formed over a semiconductor substrate. A selective portion of the Al layer is removed to form openings. The Al layer is anodized to obtain an alumina dielectric layer with a plurality of pores. The openings are filled with a conductive interconnect material. The pores are widened to form air gaps and a top etch stop layer is formed over the alumina dielectric layer.

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