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51. 发明申请

US20150206902A1 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体器件及其形成方法
公开(公告)号：US20150206902A1
公开(公告)日：2015-07-23
申请号：US14158430
申请日：2014-01-17
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Kuo-Yu CHENG , Keng-Yu CHEN , Wei-Kung TSAI , Kuan-Chi TSAI , Tsung-Yu YANG , Chung-LONG CHANG , Chun-Hung CHEN , Chih-Ping CHAO
IPC分类号： H01L27/12 , H01L21/306 , H01L21/02 , H01L21/28 , H01L23/66 , H01L21/762 , H01L27/06 , H01L21/311
CPC分类号： H01L27/1203 , H01L21/02532 , H01L21/02595 , H01L21/0262 , H01L21/28194 , H01L21/30604 , H01L21/31111 , H01L21/7624 , H01L21/76264 , H01L21/763 , H01L21/84 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L23/66 , H01L27/0629 , H01L28/20 , H01L2223/6672 , H01L2924/0002 , H01L2924/00
摘要： Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a buried oxide layer formed over the substrate. An interface layer is formed between the substrate and the buried oxide layer. The semiconductor device structure also includes a silicon layer formed over the buried oxide layer; and a polysilicon layer formed over the substrate and in a deep trench. The polysilicon layer extends through the silicon layer, the buried oxide layer and the interface layer.
摘要翻译：提供了用于形成半导体器件结构的实施例。半导体器件结构包括在衬底上形成的衬底和掩埋氧化物层。在衬底和掩埋氧化物层之间形成界面层。半导体器件结构还包括形成在掩埋氧化物层上的硅层; 以及形成在衬底上和深沟槽中的多晶硅层。多晶硅层延伸穿过硅层，掩埋氧化物层和界面层。

52. 发明申请

US20150194527A1 SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF EVALUATING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及其制造方法以及评估半导体器件的方法
公开(公告)号：US20150194527A1
公开(公告)日：2015-07-09
申请号：US14665969
申请日：2015-03-23
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Hidenobu Fukutome , Tomohiro Kubo
IPC分类号： H01L29/78 , H01L29/417 , H01L29/165 , H01L29/04 , H01L29/161
CPC分类号： H01L29/7848 , H01L21/26513 , H01L21/2658 , H01L21/28518 , H01L21/30608 , H01L21/76264 , H01L22/14 , H01L29/045 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/41758 , H01L29/45 , H01L29/66636
摘要： A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this order; and source/drain material layers formed in recesses (holes) in the silicon substrate, the recesses being located beside the gate electrode. Here, each of side surfaces of the recesses, which are closer to the gate electrode, is constituted of at least one crystal plane of the silicon substrate.
摘要翻译：半导体器件具有：硅（半导体）衬底; 栅极绝缘膜和栅电极，其依次形成在硅衬底上; 以及形成在硅衬底中的凹槽（空穴）中的源极/漏极材料层，凹部位于栅电极旁边。这里，凹部的靠近栅电极的侧表面由硅基板的至少一个晶面构成。

53. 发明授权

US09059183B2 Structure of very high insertion loss of the substrate noise decoupling 有权
标题翻译：非常高的衬底噪声去耦插入损耗的结构
公开(公告)号：US09059183B2
公开(公告)日：2015-06-16
申请号：US13748662
申请日：2013-01-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01L23/552 , H01L21/76 , H01L21/762 , H01L23/58
CPC分类号： H01L23/552 , H01L21/76 , H01L21/76264 , H01L23/585 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A structure includes a substrate comprising a region having a circuit or device which is sensitive to electrical noise. Additionally, the structure includes a first isolation structure extending through an entire thickness of the substrate and surrounding the region and a second isolation structure extending through the entire thickness of the substrate and surrounding the region.
摘要翻译：一种结构包括具有对电噪声敏感的电路或器件的区域的衬底。此外，该结构包括延伸穿过衬底的整个厚度并围绕该区域的第一隔离结构，以及延伸穿过衬底的整个厚度并围绕该区域的第二隔离结构。

54. 发明申请

US20150132918A1 Integrated Circuit Using Deep Trench Through Silicon (DTS) 审中-公开
标题翻译：使用深沟槽硅集成电路（DTS）
公开(公告)号：US20150132918A1
公开(公告)日：2015-05-14
申请号：US14604471
申请日：2015-01-23
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Kuo-Yu Cheng , Wei-Kung Tsai , Kuan-Chi Tsai , Tsung-Yu Yang , Chung-Long Chang , Chun-Hong Chen , Chih-Ping Chao , Chen-Yao Tang , Yu Hung Chen
IPC分类号： H01L21/762
CPC分类号： H01L21/76283 , H01L21/76237 , H01L21/76264 , H01L21/76267 , H01L21/764 , H01L29/0649
摘要： An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer.
摘要翻译：公开了集成电路的实施例射频区域。射频区域包括具有植入区域的衬底。衬底具有第一电阻。掩埋氧化物层设置在衬底上，并且界面层设置在衬底和掩埋氧化物层之间。界面层具有比第一电阻低的第二电阻。硅层设置在掩埋氧化物层上方，并且层间电介质设置在深沟槽中。深沟槽延伸穿过硅层，掩埋氧化物层和植入区域上的界面层。深沟槽还可以延伸穿过设置在硅层上的多晶硅层。

55. 发明授权

US09029949B2 Semiconductor-on-insulator (SOI) structures with local heat dissipater(s) and methods 有权
标题翻译：具有局部散热器和方法的绝缘体上半导体（SOI）结构
公开(公告)号：US09029949B2
公开(公告)日：2015-05-12
申请号：US14036158
申请日：2013-09-25
申请人： International Business Machines Corporation
发明人： Jeffrey P. Gambino , Qizhi Liu , Zhenzhen Ye , Yan Zhang
IPC分类号： H01L27/12 , H01L21/00 , H01L23/34 , H01L21/283
CPC分类号： H01L23/34 , H01L21/283 , H01L21/76264 , H01L21/84 , H01L23/367 , H01L27/1203 , H01L29/66772 , H01L29/78603 , H01L29/78606 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are semiconductor-on-insulator (SOI) structures comprising an SOI device (e.g., an SOI metal oxide semiconductor field effect transistor (MOSFET)) with local heat dissipater(s). Each heat dissipater comprises an opening, which is adjacent an active region of the SOI device, which extends through the insulator layer on which the SOI device sits to the semiconductor substrate below, and which is at least partially filled with a fill material. This fill material is a thermal conductor so as to dissipate heat generated by the SOI device and is also an electrical isolator so as to minimize current leakage. In the case of MOSFET, the local heat dissipater(s) can be aligned below the source/drain extension(s) or the source/drain(s). Alternatively, the local heat dissipater(s) can be aligned below the channel or parallel and adjacent to opposing sides of the channel. Also disclosed herein are methods of forming these SOI structures.
摘要翻译：公开了包括具有局部散热器的SOI器件（例如，SOI金属氧化物半导体场效应晶体管（MOSFET））的绝缘体上半导体（SOI）结构。每个散热器包括与SOI器件的有源区相邻的开口，该开口延伸穿过SOI器件位于半导体衬底下面的绝缘体层，并且至少部分地填充有填充材料。该填充材料是导热体，以散发由SOI器件产生的热量，并且也是电隔离器，以便最小化电流泄漏。在MOSFET的情况下，局部散热器可以在源极/漏极延伸部分或源极/漏极之下对准。或者，局部散热器可以在通道下方对准或平行并邻近通道的相对侧。本文还公开了形成这些SOI结构的方法。

56. 发明申请

US20150084130A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体结构及其制造方法
公开(公告)号：US20150084130A1
公开(公告)日：2015-03-26
申请号：US14397558
申请日：2012-05-16
申请人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
发明人： Haizhou Yin , Huilong Zhu , Zhijiong Luo
IPC分类号： H01L29/78 , H01L21/02 , H01L21/762 , H01L27/12 , H01L29/66
CPC分类号： H01L29/7841 , H01L21/02532 , H01L21/76264 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/6656 , H01L29/66772 , H01L29/78612 , H01L29/78648
摘要： The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing an SOI substrate, onto which a heavily doped buried layer and a surface active layer are formed; forming a gate stack and sidewall spacers on the substrate; forming an opening at one side of the gate stack, wherein the opening penetrates through the surface active layer, the heavily doped buried layer and reaches into a silicon film located on an insulating buried layer of the SOI substrate; filling the opening to form a plug; forming source/drain regions, wherein the source region overlaps with the heavily doped buried layer, and a part of the drain region is located in the plug. Accordingly, the present invention further provides a semiconductor structure. In the present invention, the heavily doped buried layer is favorable for reducing width of depletion layers at source/drain regions and suppressing short-channel effects. The heavily doped buried layer overlaps with the source region, which thence forms a heavily doped pn junction favorable for suppressing floating body effects of SOI MOS devices, thereby improving performance of semiconductor devices. Besides, no body contact is needed in the present invention, thus device area and manufacturing cost are saved.
摘要翻译：本发明提供一种制造半导体结构的方法，其包括以下步骤：提供SOI衬底，在其上形成重掺杂掩埋层和表面活性层; 在衬底上形成栅极叠层和侧壁间隔物; 在所述栅极叠层的一侧形成开口，其中所述开口穿过所述表面有源层，所述重掺杂掩埋层并进入位于所述SOI衬底的绝缘掩埋层上的硅膜; 填充开口形成插头; 形成源极/漏极区域，其中源极区域与重掺杂的掩埋层重叠，并且漏极区域的一部分位于插塞中。因此，本发明还提供一种半导体结构。在本发明中，重掺杂掩埋层有利于减小源极/漏极区的耗尽层的宽度并抑制短沟道效应。重掺杂掩埋层与源区重叠，从而形成重掺杂pn结，有利于抑制SOI MOS器件的浮体效应，从而提高半导体器件的性能。此外，在本发明中不需要接触体，从而节省了设备面积和制造成本。

57. 发明授权

US08981480B2 Semiconductor device having low resistivity region under isolation layer 有权
标题翻译：在隔离层下具有低电阻率区域的半导体器件
公开(公告)号：US08981480B2
公开(公告)日：2015-03-17
申请号：US13180822
申请日：2011-07-12
申请人： Jun-Hee Lim , Satoru Yamada , Sung-Duk Hong
发明人： Jun-Hee Lim , Satoru Yamada , Sung-Duk Hong
IPC分类号： H01L29/786 , H01L27/108 , H01L21/762 , H01L21/8234
CPC分类号： H01L27/10894 , H01L21/76264 , H01L21/823481
摘要： A semiconductor device includes a buried well, first and second active regions, an isolation layer, and a low resistance region. The buried well is disposed on a substrate and has impurity ions of a first conductivity type. The first and second active regions are disposed on the buried well and each have impurity ions of a second conductivity type, which is different from the first conductivity type. The isolation layer is disposed between the first and second active regions. The low resistance region is disposed between the isolation layer and the substrate and has impurity ions of the second conductivity type. The concentration of impurity ions in the low resistance region is greater than the concentration of the impurity ions in each of the first and second active regions.
摘要翻译：半导体器件包括掩埋阱，第一和第二有源区，隔离层和低电阻区域。掩埋阱设置在基板上并具有第一导电类型的杂质离子。第一和第二有源区域设置在掩埋阱上，并且每个具有与第一导电类型不同的第二导电类型的杂质离子。隔离层设置在第一和第二有源区之间。低电阻区域设置在隔离层和衬底之间，并且具有第二导电类型的杂质离子。低电阻区域中的杂质离子的浓度大于第一和第二活性区域中的每一个中的杂质离子的浓度。

58. 发明授权

US08963280B1 Semiconductor devices and methods of manufacture 有权
标题翻译：半导体器件及制造方法
公开(公告)号：US08963280B1
公开(公告)日：2015-02-24
申请号：US14024102
申请日：2013-09-11
申请人： International Business Machines Corporation
发明人： Effendi Leobandung
IPC分类号： H01L21/70 , H01L29/06
CPC分类号： H01L29/06 , H01L21/02002 , H01L21/02647 , H01L21/76224 , H01L21/76264
摘要： Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming a dielectric material on a substrate. The method further includes forming a shallow trench structure and deep trench structure within the dielectric material. The method further includes forming a material within the shallow trench structure and deep trench structure. The method further includes forming active areas of the material separated by shallow trench isolation structures. The shallow trench isolation structures are formed by: removing the material from within the deep trench structure and portions of the shallow trench structure to form trenches; and depositing an insulator material within the trenches.
摘要翻译：公开了具有减少的衬底缺陷的半导体器件和制造方法。该方法包括在基板上形成电介质材料。该方法还包括在电介质材料内形成浅沟槽结构和深沟槽结构。该方法还包括在浅沟槽结构和深沟槽结构内形成材料。该方法还包括形成由浅沟槽隔离结构隔开的材料的有源区域。浅沟槽隔离结构通过以下方式形成：从深沟槽结构内的材料和浅沟槽结构的部分去除材料以形成沟槽; 以及在所述沟槽内沉积绝缘体材料。

59. 发明申请

US20150041900A1 TRANSISTORS WITH VARIOUS LEVELS OF THRESHOLD VOLTAGES AND ABSENCE OF DISTORTIONS BETWEEN NMOS AND PMOS 有权
标题翻译：具有各种阈值电压的晶体管和NMOS和PMOS之间的失真
公开(公告)号：US20150041900A1
公开(公告)日：2015-02-12
申请号：US14309385
申请日：2014-06-19
申请人： Commissariat a l'energie atomique et aux energies alternatives , STMicroelectronics (Crolles 2) SAS
发明人： Olivier Weber , Nicolas Planes , Rossella Ranica
IPC分类号： H01L27/12 , H01L27/092
CPC分类号： H01L27/1203 , H01L21/7624 , H01L21/76264 , H01L21/84 , H01L27/092 , H01L27/0922 , H01L27/0928 , H01L29/78648
摘要： The invention relates to an integrated circuit comprising a semi-conducting substrate and first and second cells. Each cell comprises first and second transistors of nMOS and pMOS type including first and second gate stacks including a gate metal. There are first and second ground planes under the first and second transistors and an oxide layer extending between the transistors and the ground planes. The gate metals of the nMOS and of a pMOS exhibit a first work function and the gate metal of the other pMOS exhibiting a second work function greater than the first work function. The difference between the work functions is between 55 and 85 meV and the first work function Wf1 satisfies the relation Wfmg−0.04−0.005*Xge
摘要翻译：本发明涉及包括半导体衬底和第一和第二单元的集成电路。每个单元包括nMOS和pMOS型的第一和第二晶体管，包括包括栅极金属的第一和第二栅极堆叠。在第一和第二晶体管之下有第一和第二接地层，以及在晶体管和接地层之间延伸的氧化物层。 nMOS和pMOS的栅极金属表现出第一功函数，另一个pMOS的栅极金属表现出大于第一功函数的第二功函数。工作函数之间的差异在55和85meV之间，第一功函数Wf1满足关系Wfmg-0.04-0.005 * Xge

60. 发明授权

US08802520B2 Method of forming a field effect transistor having source/drain material over insulative material 有权
标题翻译：在绝缘材料上形成具有源极/漏极材料的场效应晶体管的方法
公开(公告)号：US08802520B2
公开(公告)日：2014-08-12
申请号：US13861082
申请日：2013-04-11
申请人： Micron Technology, Inc.
发明人： Sanh D. Tang , Michael P. Violette , Robert Burke
IPC分类号： H01L21/00
CPC分类号： H01L29/7833 , G06K19/0723 , G06K19/0726 , G06K19/07771 , H01L21/76229 , H01L21/76232 , H01L21/76264 , H01L21/823418 , H01L21/823437 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L29/1083 , H01L29/41783 , H01L29/66545 , H01L29/66583 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.
摘要翻译：在一个实施方案中，形成场效应晶体管的方法包括蚀刻半导体衬底的源/漏区的开口。开口具有包括半导体材料的基底。在蚀刻之后，在半导体材料基体的开口内形成绝缘材料。绝缘材料小于完全填充开口并且在开口上具有基本均匀的厚度。在开口内的绝缘材料的开口内形成半导电源极/漏极材料。半导体源极/漏极材料可操作地提供晶体管栅极。考虑了其他方面和实现。

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