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51. 发明申请

US20150228745A1 SELF-ALIGNED LINER FORMED ON METAL SEMICONDUCTOR ALLOY CONTACTS 有权
标题翻译：金属半导体合金接头上形成的自对准衬垫
公开(公告)号：US20150228745A1
公开(公告)日：2015-08-13
申请号：US14177481
申请日：2014-02-11
申请人： International Business Machines Corporation
发明人： Nicolas Breil , Christian Lavoie , Ahmet S. Ozcan , Kathryn T. Schonenberg , Jian Yu
IPC分类号： H01L29/45 , H01L21/285 , H01L29/66 , H01L29/20 , H01L29/78 , H01L29/16
CPC分类号： H01L29/456 , H01L21/28052 , H01L21/28518 , H01L21/2855 , H01L21/28568 , H01L21/28575 , H01L21/76843 , H01L21/76855 , H01L29/665 , H01L29/66545 , H01L29/78
摘要： Metal semiconductor alloy contacts are provided on each of a source region and a drain region which are present in a semiconductor substrate. A transition metal is then deposited on each of the metal semiconductor alloy contacts, and during the deposition of the transition metal, the deposited transition metal reacts preferably, but not necessarily always, in-situ with a portion of each the metal semiconductor alloy contacts forming a transition metal-metal semiconductor alloy liner atop each metal semiconductor alloy contact. Each transition metal-metal semiconductor alloy liner that is provided has outer edges that are vertically coincident with outer edges of each metal semiconductor alloy contact. The transition metal-metal semiconductor alloy liner is more etch resistant as compared to the underlying metal semiconductor alloy. As such, the transition metal-metal semiconductor alloy liner can serve as an effective etch stop layer during any subsequently performed etch process.
摘要翻译：金属半导体合金触点设置在存在于半导体基板中的源极区域和漏极区域中的每一个上。然后在每个金属半导体合金触点上沉积过渡金属，并且在沉积过渡金属期间，沉积的过渡金属优选地但不一定总是与形成的每个金属半导体合金触点的一部分原位反应在每个金属半导体合金接触顶上的过渡金属 - 金属半导体合金衬里。设置有过渡金属 - 金属半导体合金衬垫的每个金属半导体合金衬垫的外边缘与每个金属半导体合金触点的外边缘垂直重合。与下面的金属半导体合金相比，过渡金属 - 金属半导体合金衬里更耐腐蚀。因此，过渡金属 - 金属半导体合金衬里可以在任何随后执行的蚀刻工艺期间用作有效的蚀刻停止层。

52. 发明申请

US20150221649A1 Complementary Field Effect Transistors Using Gallium Polar and Nitrogen Polar III-Nitride Material 有权
标题翻译：互补场效应晶体管使用镓极极和氮极三氮化物材料
公开(公告)号：US20150221649A1
公开(公告)日：2015-08-06
申请号：US14666494
申请日：2015-03-24
申请人： Francis J. Kub , Travis J. Anderson , Michael A. Mastro , Charles R. Eddy, JR. , Jennifer K. Hite
发明人： Francis J. Kub , Travis J. Anderson , Michael A. Mastro , Charles R. Eddy, JR. , Jennifer K. Hite
IPC分类号： H01L27/092 , H01L29/778 , H01L21/8252
CPC分类号： H01L27/095 , H01L21/02458 , H01L21/0254 , H01L21/02609 , H01L21/0262 , H01L21/02631 , H01L21/26546 , H01L21/28575 , H01L21/28587 , H01L21/30612 , H01L21/3065 , H01L21/762 , H01L21/8228 , H01L21/8238 , H01L21/8252 , H01L27/092 , H01L27/0921 , H01L27/0922 , H01L29/045 , H01L29/1075 , H01L29/1608 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/207 , H01L29/365 , H01L29/407 , H01L29/41725 , H01L29/41766 , H01L29/42364 , H01L29/452 , H01L29/51 , H01L29/66431 , H01L29/66439 , H01L29/66462 , H01L29/66477 , H01L29/778 , H01L29/7781 , H01L29/7782 , H01L29/7783 , H01L29/7784 , H01L29/7786 , H01L29/7787 , H01L29/78 , H01L29/7831
摘要： A device with complementary non-inverted N-channel and inverted P-channel field effect transistors comprising a layer grown epitaxially on a substrate, a barrier layer, a two-dimensional electron gas in the first III-Nitride epitaxial layer, a second III-Nitride material layer, and a two-dimensional hole gas in the second III-Nitride epitaxial layer. A device with complementary inverted N-channel and non-inverted P-channel field effect transistors comprising a nitrogen-polar III-Nitride layer grown epitaxially, a barrier material layer, a two-dimensional hole gas, and a two-dimensional electron gas in the second III-Nitride epitaxial layer. A method of making complementary inverted P-channel and non-inverted N-channel III-Nitride field effect transistors. A method of making a complementary non-inverted P-channel field effect transistor and inverted N-channel III-Nitride field effect transistor on a substrate.
摘要翻译：具有互补非反相N沟道和反相P沟道场效应晶体管的器件，其包括在衬底上外延生长的层，第一III-氮化物外延层中的势垒层，二维电子气，第二III- 氮化物材料层和第二III-氮化物外延层中的二维空穴气体。具有互补反向N沟道和非反相P沟道场效应晶体管的器件，其包括外延生长的氮极III-氮化物层，阻挡材料层，二维空穴气体和二维电子气第二个III-氮化物外延层。制造互补的反相P沟道和非反相N沟道III氮化物场效应晶体管的方法。在衬底上制作互补的非反相P沟道场效应晶体管和反相N沟道III氮化物场效应晶体管的方法。

53. 发明授权

US09087775B2 Planar semiconductor growth on III-V material 有权
标题翻译： III-V材料的平面半导体生长
公开(公告)号：US09087775B2
公开(公告)日：2015-07-21
申请号：US13760277
申请日：2013-02-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Cheng-Wei Cheng , Jack O. Chu , Devendra K. Sadana , Kuen-Ting Shiu , Yanning Sun
IPC分类号： H01L29/66 , H01L29/267 , H01L29/772 , H01L21/02 , H01L29/78
CPC分类号： H01L29/267 , H01L21/02387 , H01L21/02439 , H01L21/02532 , H01L21/02538 , H01L21/0262 , H01L21/02661 , H01L21/02664 , H01L21/28575 , H01L21/3228 , H01L29/452 , H01L29/66522 , H01L29/772 , H01L29/78
摘要： A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.
摘要翻译：半导体结构包括III-V单晶层和锗表面层。从III-V单晶层和锗表面层之间直接形成中间层，所述材料被选择为在中间层和锗表面层之间提供更强的成核结合，而不是直接在III-V单晶层和锗表面层，使得提供连续的，相对缺陷的锗表面层。

54. 发明申请

US20150179823A1 ELECTRODE STRUCTURE FOR NITRIDE SEMICONDUCTOR DEVICE, PRODUCTION METHOD THEREFOR, AND NITRIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR 审中-公开
标题翻译：用于氮化物半导体器件的电极结构，其制造方法和氮化物半导体场效应晶体管
公开(公告)号：US20150179823A1
公开(公告)日：2015-06-25
申请号：US14406553
申请日：2013-06-26
申请人： SHARP KABUSHIKI KAISHA
发明人： Daisuke Kurita
IPC分类号： H01L29/808 , H01L29/201 , H01L29/40 , H01L21/324 , H01L21/311 , H01L21/3205 , H01L21/3213 , H01L29/20 , H01L29/417
CPC分类号： H01L29/808 , H01L21/28575 , H01L21/3081 , H01L21/3105 , H01L21/311 , H01L21/32051 , H01L21/32133 , H01L21/324 , H01L21/3245 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/401 , H01L29/41725 , H01L29/41766 , H01L29/66462 , H01L29/7786
摘要： According to an electrode structure of an embodiment of the invention, an ohmic electrode is provided from recess to a surface of an insulating film without being in contact with the surface of the nitride semiconductor multilayer body, so that the insulating film covers the surface of the AlGaN barrier layer. Accordingly, during the formation process of the ohmic electrode by dry etching, the surface of the nitride semiconductor multilayer body can be protected by the insulating film.
摘要翻译：根据本发明的实施例的电极结构，欧姆电极从凹部到绝缘膜的表面设置，而不与氮化物半导体多层体的表面接触，使得绝缘膜覆盖 AlGaN势垒层。因此，在通过干蚀刻形成欧姆电极的过程中，可以通过绝缘膜来保护氮化物半导体多层体的表面。

55. 发明申请

US20150179751A1 Ohmic Contact to Semiconductor Layer 有权
标题翻译：欧姆接触半导体层
公开(公告)号：US20150179751A1
公开(公告)日：2015-06-25
申请号：US14636546
申请日：2015-03-03
申请人： Sensor Electronic Technology, Inc.
发明人： Mikhail Gaevski , Grigory Simin , Maxim S. Shatalov , Alexander Dobrinsky , Michael Shur , Remigijus Gaska
IPC分类号： H01L29/45 , H01L33/36 , H01L33/32 , H01L29/20 , H01L21/283 , H01L21/324 , H01L29/40 , H01L33/00 , H01L29/778
CPC分类号： H01L29/452 , H01L21/28575 , H01L21/28587 , H01L21/28593 , H01L29/2003 , H01L29/4175 , H01L29/41766 , H01L29/7787 , H01L33/382 , H01L2933/0016
摘要： A perforating ohmic contact to a semiconductor layer in a semiconductor structure is provided. The perforating ohmic contact can include a set of perforating elements, which can include a set of metal protrusions laterally penetrating the semiconductor layer(s). The perforating elements can be separated from one another by a characteristic length scale selected based on a sheet resistance of the semiconductor layer and a contact resistance per unit length of a metal of the perforating ohmic contact contacting the semiconductor layer. The structure can be annealed using a set of conditions configured to ensure formation of the set of metal protrusions.
摘要翻译：提供了与半导体结构中的半导体层的穿孔欧姆接触。穿孔欧姆接触可以包括一组穿孔元件，其可以包括横向渗透半导体层的一组金属突起。穿孔元件可以通过基于半导体层的薄层电阻选择的特征长度刻度和接触半导体层的穿孔欧姆接触金属的每单位长度的接触电阻彼此分离。该结构可以使用一组条件进行退火，所述条件被配置成确保形成该组金属突起。

56. 发明申请

US20150170921A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20150170921A1
公开(公告)日：2015-06-18
申请号：US14464786
申请日：2014-08-21
申请人： Mitsubishi Electric Corporation
发明人： Yoshihiko Hanamaki
IPC分类号： H01L21/285 , H01L21/324
CPC分类号： H01L21/28575 , H01L21/28512 , H01L29/2003 , H01L29/452
摘要： A method of making an ohmic contact from a multi-metal-layer includes increasing a temperature in an annealing furnace containing the multi-metal-layer to a temperature within a first temperature range, from a temperature lower by 100° C. than a minimum melting point, which is the lowest melting point among melting points of the respective layers of the multi-metal-layer, to the minimum melting point, maintaining the temperature within the first temperature range, increasing the temperature in the furnace to a temperature to within a second temperature range, lower than a maximum melting point, which is the highest melting point of the respective layers of the multi-metal-layer, to higher than the minimum melting point among melting points of the respective layers of the multi-metal-layer, at a temperature increasing speed of 5° C./sec to 20° C./sec, and maintaining the temperature within the second temperature range.
摘要翻译：从多金属层制造欧姆接触的方法包括将包含多金属层的退火炉中的温度从低于100℃的温度升高到第一温度范围内的温度，而不是最小值熔点，其是多金属层的各层的熔点中的最低熔点至最低熔点，将温度保持在第一温度范围内，将炉中的温度升高至内部温度低于多金属层各层的最高熔点的第二温度范围，高于多金属层各层的熔点之间的最小熔点，层，以5℃/秒至20℃/秒的升温速度，并将温度保持在第二温度范围内。

57. 发明授权

US09018056B2 Complementary field effect transistors using gallium polar and nitrogen polar III-nitride material 有权
公开(公告)号：US09018056B2
公开(公告)日：2015-04-28
申请号：US14170161
申请日：2014-01-31
申请人： Francis J. Kub , Travis J. Anderson , Michael A. Mastro , Charles R. Eddy, Jr. , Jennifer K. Hite
发明人： Francis J. Kub , Travis J. Anderson , Michael A. Mastro , Charles R. Eddy, Jr. , Jennifer K. Hite
IPC分类号： H01L21/335 , H01L29/778 , H01L29/66 , H01L29/78 , H01L29/20 , H01L29/417 , H01L29/10 , H01L29/16 , H01L29/423
CPC分类号： H01L27/095 , H01L21/02458 , H01L21/0254 , H01L21/02609 , H01L21/0262 , H01L21/02631 , H01L21/26546 , H01L21/28575 , H01L21/28587 , H01L21/30612 , H01L21/3065 , H01L21/762 , H01L21/8228 , H01L21/8238 , H01L21/8252 , H01L27/092 , H01L27/0921 , H01L27/0922 , H01L29/045 , H01L29/1075 , H01L29/1608 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/207 , H01L29/365 , H01L29/407 , H01L29/41725 , H01L29/41766 , H01L29/42364 , H01L29/452 , H01L29/51 , H01L29/66431 , H01L29/66439 , H01L29/66462 , H01L29/66477 , H01L29/778 , H01L29/7781 , H01L29/7782 , H01L29/7783 , H01L29/7784 , H01L29/7786 , H01L29/7787 , H01L29/78 , H01L29/7831
摘要： A device with N-Channel and P-Channel III-Nitride field effect transistors comprising a non-inverted P-channel III-Nitride field effect transistor on a first nitrogen-polar nitrogen face III-Nitride material, a non-inverted N-channel III-Nitride field effect transistor, epitaxially grown, a first III-Nitride barrier layer, two-dimensional hole gas, second III-Nitride barrier layer, and a two-dimensional hole gas. A method of making complementary non-inverted P-channel and non-inverted N-channel III-Nitride FET comprising growing epitaxial layers, depositing oxide, defining opening, growing epitaxially a first nitrogen-polar III-Nitride material, buffer, back barrier, channel, spacer, barrier, and cap layer, and carrier enhancement layer, depositing oxide, growing AlN nucleation layer/polarity inversion layer, growing gallium-polar III-Nitride, including epitaxial layers, depositing dielectric, fabricating P-channel III-Nitride FET, and fabricating N-channel III-Nitride FET.

58. 发明申请

US20150108496A1 GROUP III-N TRANSISTOR ON NANOSCALE TEMPLATE STRUCTURES 有权
标题翻译：纳米晶体结构的III-N族晶体管
公开(公告)号：US20150108496A1
公开(公告)日：2015-04-23
申请号：US14581722
申请日：2014-12-23
申请人： Intel Corporation
发明人： Han Wui THEN , Sansaptak DASGUPTA , Marko RADOSAVLJEVIC , Benjamin CHU-KUNG , Sanaz GARDNER , Seung Hoon SUNG , Robert S. Chau
IPC分类号： H01L27/12 , H01L29/201 , H01L29/06 , H01L21/285 , H01L29/66 , H01L21/84 , H01L21/02 , H01L29/20 , H01L29/778
CPC分类号： H01L29/2003 , H01L21/02164 , H01L21/02238 , H01L21/02255 , H01L21/0228 , H01L21/0254 , H01L21/283 , H01L21/28575 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/201 , H01L29/42356 , H01L29/66462 , H01L29/66795 , H01L29/7787 , H01L29/78 , H01L29/785 , H01L29/7851 , H01L29/802
摘要： A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.
摘要翻译： III-N半导体沟道形成在形成于诸如翅片侧壁的硅模板结构的（111）或（110）表面上的III-N过渡层上。在实施例中，硅鳍具有与更适应的种子层的III-N外延膜厚度相当的宽度，允许更低的缺陷密度和/或降低的外延膜厚度。在实施例中，过渡层是GaN，并且半导体沟道包括铟（In）以增加从硅片的导带偏移。在其它实施例中，鳍是牺牲性的，并且在晶体管制造期间被去除或氧化，或以其它方式转换为电介质结构。在采用牺牲散热片的某些实施例中，III-N过渡层和半导体通道是基本上纯的GaN，允许击穿电压高于在硅片存在时可持续的击穿电压。

59. 发明授权

US08987143B2 Hydrogen plasma cleaning of germanium oxide surfaces 有权
标题翻译：氧化锗表面的氢等离子体清洗
公开(公告)号：US08987143B2
公开(公告)日：2015-03-24
申请号：US14031975
申请日：2013-09-19
申请人： Intermolecular, Inc.
发明人： Ratsamee Limdulpaiboon , Chi-I Lang , Sandip Niyogi , J. Watanabe
IPC分类号： H01L21/302 , H01L21/02 , H01L29/66 , H01L27/146 , H01L21/283 , H01L29/41 , H01L21/3065 , H01L29/778 , H01L29/16
CPC分类号： H01L21/76864 , H01L21/02005 , H01L21/02104 , H01L21/02172 , H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02205 , H01L21/0228 , H01L21/283 , H01L21/28575 , H01L21/3065 , H01L22/12 , H01L22/14 , H01L27/1462 , H01L27/14643 , H01L27/14698 , H01L29/1606 , H01L29/41 , H01L29/66477 , H01L29/66742 , H01L29/778 , H01L29/786
摘要： Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The plasma system may be used to generate activated hydrogen species. The activated hydrogen species can be used to etch/clean semiconductor oxide surfaces such as silicon oxide or germanium oxide.
摘要翻译：公开了使用远程等离子体源的处理方法和装置。该装置包括封闭衬底支撑件，远程等离子体源和喷头的外室。基板加热器可以安装在基板支撑件中。运输系统移动基板支撑件并且能够定位基板。等离子体系统可用于产生活性氢物质。活化的氢物质可用于蚀刻/清洁半导体氧化物表面，例如氧化硅或氧化锗。

60. 发明申请

US20150014792A1 III-V COMPOUND SEMICONDUCTOR DEVICE HAVING METAL CONTACTS AND METHOD OF MAKING THE SAME 审中-公开
公开(公告)号：US20150014792A1
公开(公告)日：2015-01-15
申请号：US14499308
申请日：2014-09-29
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Richard Kenneth OXLAND
IPC分类号： H01L29/78 , H01L29/49 , H01L29/45
CPC分类号： H01L29/452 , H01L21/28575 , H01L23/485 , H01L23/53266 , H01L27/0605 , H01L29/20 , H01L29/205 , H01L29/45 , H01L29/4933 , H01L29/78 , H01L29/7833 , H01L29/7839 , H01L29/78681 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises a semiconductor substrate; a channel layer of at least a first III-V semiconductor compound above the semiconductor substrate; a gate stack structure above a first portion of the channel layer; a source region and a drain region comprising at least a second III-V semiconductor compound above a second portion of the channel layer; and a first metal contact structure above the S/D regions comprising a first metallic contact layer contacting the S/D regions. The first metallic contact layer comprises at least one metal-III-V semiconductor compound.

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