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51. 发明申请

US20150071000A1 SEMICONDUCTOR MEMORY DEVICE AND DEFECTIVE JUDGING METHOD THEREOF 有权
标题翻译：半导体存储器件及其有缺陷的判断方法
公开(公告)号：US20150071000A1
公开(公告)日：2015-03-12
申请号：US14204165
申请日：2014-03-11
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yuzuru NAMAI , Manabu SATO
IPC分类号： G11C29/12
CPC分类号： G11C29/12005 , G11C7/04 , G11C29/025 , G11C29/028 , G11C2029/1202
摘要： A semiconductor memory device is provided with a plurality of memory cells connected to a plurality of word lines, a word-line leakage detector configured to detect a leakage current generated on at least one of the plurality of word lines, and a controller configured, when a leakage current is detected by the word-line leakage detector, to determine that a block including a memory cell connected to a word line through which the leakage current is flowing is defective. The word-line leakage detector has a detection voltage generator configured to generate a detection voltage in accordance with the leakage current, a comparator configured to generate a flag signal having output logic that is inverted depending on whether the detection voltage exceeds a predetermined threshold voltage, and an adjuster configured to adjust a current amount by diverting part of the leakage current in accordance with an ambient temperature.
摘要翻译：半导体存储器件具有连接到多个字线的多个存储器单元，字线泄漏检测器，被配置为检测在所述多个字线中的至少一个字线上产生的漏电流;以及控制器，由字线泄漏检测器检测泄漏电流，以确定包括连接到泄漏电流流过的字线的存储单元的块有缺陷。字线泄漏检测器具有检测电压发生器，被配置为根据泄漏电流产生检测电压，比较器被配置为产生具有根据检测电压是否超过预定阈值电压而反转的输出逻辑的标志信号，以及调整器，被配置为通过根据环境温度转移部分泄漏电流来调节电流量。

52. 发明申请

US20150043292A1 MEMORY, MEMORY SYSTEM INCLUDING THE SAME AND METHOD FOR OPERATING MEMORY 有权
标题翻译：存储器，包括其的存储器系统和操作存储器的方法
公开(公告)号：US20150043292A1
公开(公告)日：2015-02-12
申请号：US14109582
申请日：2013-12-17
申请人： SK hynix Inc.
发明人： Yo-Sep LEE , Choung-Ki SONG
IPC分类号： G11C29/08
CPC分类号： G11C29/50012 , G11C29/025 , G11C29/08 , G11C2029/1202 , G11C2029/5002
摘要： A memory may include a plurality of word lines to which one or more memory cells are connected, and a control unit suitable for activating and precharging a first word line that is selected based on an address of a high-activated word line during a target refresh operation while sequentially activating and precharging the plurality of word lines in a refresh operation, wherein the control unit is suitable for writing a test data to one or more first memory cells connected to the first word line during the target refresh operation in a test mode, wherein the high-activated word line is a word line activated over a reference number or a reference frequency, among the plurality of word lines.
摘要翻译：存储器可以包括连接一个或多个存储器单元的多个字线，以及适于在目标刷新期间基于高激活字线的地址来选择的第一字线的激活和预充电的控制单元在刷新操作中顺序地激活和预充电多个字线的操作，其中所述控制单元适合于在测试模式期间的目标刷新操作期间将测试数据写入连接到第一字线的一个或多个第一存储器单元，其中所述高激活字线是在所述多个字线中的参考数字或参考频率上激活的字线。

53. 发明申请

US20140375348A1 SHORT-CHECKING METHODS 有权
标题翻译：短期检查方法
公开(公告)号：US20140375348A1
公开(公告)日：2014-12-25
申请号：US13922378
申请日：2013-06-20
申请人： Micron Technology, Inc.
发明人： Toru Tanzawa
IPC分类号： G01R31/26
CPC分类号： G11C29/50 , G01R31/025 , G11C16/0483 , G11C16/14 , G11C16/26 , G11C29/025 , G11C29/08 , G11C2029/1202 , G11C2029/1204 , G11C2029/5004
摘要： In an embodiment, a short-checking method includes charging a data line to an initial voltage while activating a memory cell coupled to the data line, allowing the data line to float while continuing to activate the memory cell, sensing a resulting voltage on the data line after a certain time, and determining whether a short exists in response to a level of the resulting voltage.
摘要翻译：在一个实施例中，短检查方法包括在激活耦合到数据线的存储器单元的同时将数据线充电到初始电压，从而允许数据线在继续激活存储器单元的同时浮动，感测数据上产生的电压在一定时间之后，确定是否存在响应于所得电压的电平的短路。

54. 发明申请

US20140325297A1 CODE COVERAGE CIRCUITRY 有权
标题翻译：代码覆盖电路
公开(公告)号：US20140325297A1
公开(公告)日：2014-10-30
申请号：US14326622
申请日：2014-07-09
申请人： Freescale Semiconductor, Inc.
发明人： Rafael M. VILELA , Walter Luis TERCARIOL , Fernando Zampronho NETO , Sandro A. P. HADDAD
IPC分类号： G11C29/12 , G11C7/16
CPC分类号： G11C29/12015 , G06F11/3676 , G11C7/16 , G11C8/08 , G11C2029/1202
摘要： A method with a circuit that includes a memory (130) coupled to an analog line coverage circuit (104). The analog line coverage circuit includes a plurality of buffers (151-154) in which each buffer is coupled to one memory location of the memory, a plurality of bin cells (161-164) in which each bin cell is coupled to a buffer, a multiplexer (170), each input terminal of which is coupled to a bin cell, and an analog-to-digital converter (180) coupled to the multiplexer and to an output terminal of the analog line coverage circuit. The analog line coverage circuit stores an analog voltage that is representative of a number of occasions that a memory location is accessed, and outputs a signal indicative thereof. A processor (102), coupled to the memory and to the analog line coverage circuit, enables the analog line coverage circuit when the processor is in a debug mode.
摘要翻译：一种具有电路的方法，包括耦合到模拟线路覆盖电路（104）的存储器（130）。模拟线路覆盖电路包括多个缓冲器（151-154），其中每个缓冲器耦合到存储器的一个存储器位置，其中每个存储单元耦合到缓冲器的多个存储单元（161-164）多路复用器（170），其每个输入端耦合到一个二进制信元单元，以及耦合到多路复用器和模拟线路覆盖电路的输出端的模拟 - 数字转换器（180）。模拟线路覆盖电路存储表示访问存储器位置的次数的模拟电压，并输出表示其的信号。当处理器处于调试模式时，耦合到存储器和模拟线路覆盖电路的处理器（102）使能模拟线路覆盖电路。

55. 发明授权

US08824238B2 Memory device with bi-directional tracking of timing constraints 有权
标题翻译：具有双向跟踪时序约束的存储器件
公开(公告)号：US08824238B2
公开(公告)日：2014-09-02
申请号：US13849557
申请日：2013-03-25
申请人： Etron Technology, Inc.
发明人： Ho-Yin Chen , Hung-Jen Chang , Chun Shiah
IPC分类号： G11C7/22 , G11C8/08 , G11C29/50 , G11C29/02 , G11C29/12
CPC分类号： G11C29/023 , G11C7/227 , G11C8/08 , G11C11/4076 , G11C29/50012 , G11C2029/1202
摘要： A memory device includes a DRAM, a first bi-directional tracking circuit and a second bi-directional tracking circuit. The DRAM includes a cell, a word line and a bit line. The first bi-directional tracking circuit is configured to track a first timing constraint associated with turning on or turning off the word line. The second bi-directional tracking circuit is configured to track a second timing constraint associated with turning on the bit line, turning off the bit line, or accessing the cell via the bit line.
摘要翻译：存储器件包括DRAM，第一双向跟踪电路和第二双向跟踪电路。 DRAM包括单元，字线和位线。第一双向跟踪电路被配置为跟踪与打开或关闭字线相关联的第一定时约束。第二双向跟踪电路被配置为跟踪与打开位线相关联的第二定时约束，关闭位线或经由位线访问单元。

56. 发明授权

US08811086B2 Flash memory device and programming method thereof 有权
标题翻译：闪存设备及其编程方法
公开(公告)号：US08811086B2
公开(公告)日：2014-08-19
申请号：US12458089
申请日：2009-06-30
申请人： Moo-Sung Kim
发明人： Moo-Sung Kim
IPC分类号： G11C16/04 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/12
CPC分类号： G11C16/30 , G11C8/08 , G11C16/04 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/1202
摘要： A flash memory device including a controller to determine higher, M, and lower, N, word-line address bits based on an input word-line address, to determine a selected area of a memory array based on the higher and lower word-line address bits, and an unselected area of the memory array based on the selected area; and a high voltage generator to provide a first pass voltage to a word line of the selected area, and to provide a second pass voltage to a word line of the unselected area. The pass voltages are discriminately applied to the programmed and non-programmed memory cells, enlarging the pass voltage window. The memory array is divided into pluralities of zones to which local voltages are each applied in different levels.
摘要翻译：一种闪速存储装置，包括：控制器，用于基于输入字线地址确定较高的M，和N个字线地址位，以基于较高和较低字线确定存储器阵列的选定区域地址位和基于所选区域的存储器阵列的未选择区域; 以及高电压发生器，用于向选定区域的字线提供第一通过电压，并向未选择区域的字线提供第二通过电压。通过电压被区分地施加到已编程和非编程的存储器单元，扩大通过电压窗口。存储器阵列被分成多个区域，每个区域各自以不同的级别施加局部电压。

57. 发明授权

US08804430B2 Selected word line dependent select gate diffusion region voltage during programming 有权
标题翻译：选择字线依赖选择栅扩散区电压编程
公开(公告)号：US08804430B2
公开(公告)日：2014-08-12
申请号：US13430494
申请日：2012-03-26
申请人： Chun-Hung Lai , Shinji Sato , Shih-Chung Lee , Gerrit Jan Hemink
发明人： Chun-Hung Lai , Shinji Sato , Shih-Chung Lee , Gerrit Jan Hemink
IPC分类号： G11C11/34 , G11C16/04 , G11C16/10 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/04 , G11C16/06 , G11C16/10 , G11C29/021 , G11C29/028 , G11C2029/1202
摘要： Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The voltage applied to a common source line may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction, which may prevent or reduce program disturb. The voltage applied to bit lines of unselected NAND strings may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction.
摘要翻译：公开了用于操作非易失性存储器的方法和装置。一个或多个编程条件取决于为编程选择的字线的位置。应用所选字线相关程序条件可能会减少或消除程序干扰。施加到公共源极线的电压可以取决于被选择用于编程的字线的位置。这可以防止或减少穿通传导，这可以防止或减少程序干扰。施加到未选择NAND串的位线的电压可能取决于选择用于编程的字线的位置。这可以防止或减少穿透传导。

58. 发明申请

US20140119101A1 WORDLINE TRACKING FOR BOOSTED-WORDLINE TIMING SCHEME 有权
标题翻译： WORDLINE跟踪增强型WORDLINE时序方案
公开(公告)号：US20140119101A1
公开(公告)日：2014-05-01
申请号：US13665031
申请日：2012-10-31
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
发明人： Li-Wen Wang , Chih-Yu Lin , Yen-Huei Chen , Hung-Jen Liao
IPC分类号： G11C8/08
CPC分类号： G11C8/08 , G11C7/00 , G11C8/00 , G11C11/4063 , G11C16/04 , G11C29/021 , G11C29/025 , G11C29/028 , G11C2029/1202
摘要： Some aspects of the present disclosure a method. In this method, a wordline voltage is provided to a wordline, which is coupled to a plurality of memory cells. A boost enable signal is provided. The state of the boost enable signal is indicative of whether the wordline voltage at a predetermined position on the wordline has reached a non-zero, predetermined wordline voltage. The wordline voltage is selectively boosted to a boosted wordline voltage level based on the boost enable signal.
摘要翻译：本公开的一些方面是一种方法。在该方法中，字线电压被提供给字线，该字线耦合到多个存储器单元。提供升压使能信号。升压使能信号的状态表示字线上的预定位置的字线电压是否达到非零预定字线电压。基于升压使能信号，字线电压被选择性地升压到升压的字线电压电平。

59. 发明授权

US08630118B2 Defective word line detection 有权
标题翻译：字线检测不良
公开(公告)号：US08630118B2
公开(公告)日：2014-01-14
申请号：US13292556
申请日：2011-11-09
申请人： Manabu Sakai , Toru Miwa
发明人： Manabu Sakai , Toru Miwa
IPC分类号： G11C16/04
CPC分类号： G11C29/025 , G11C11/5628 , G11C16/0483 , G11C2029/1202 , G11C2211/5621
摘要： Methods and non-volatile storage systems are provided for detecting defects in word lines. A “broken” word line defect may be detected. Information may be maintained as to which storage elements were intended to be programmed to a tracked state. Then, after programming is complete, the storage elements are read to determine which storage elements have a threshold voltage below a reference voltage level associated with the tracked state. By tracking which storage elements are in the tracked state, elements associated with other states may be filtered out such that an accurate assessment may be made as to which storage elements were under-programmed. From this information, a determination may be made whether the word line is defective. For example, if too many storage elements are under-programmed, this may indicate a broken word line.
摘要翻译：提供了用于检测字线中的缺陷的方法和非易失性存储系统。可能检测到“破碎”的字线缺陷。可以保持关于哪些存储元件被编程为跟踪状态的信息。然后，在完成编程之后，读取存储元件以确定哪些存储元件具有低于与跟踪状态相关联的参考电压电平的阈值电压。通过跟踪哪些存储元件处于跟踪状态，可以滤除与其他状态相关联的元件，使得可以对哪些存储元件被编程不正确进行准确的评估。根据该信息，可以确定字线是否有缺陷。例如，如果存储元素太多被编程不当，则这可能表示一个破损的字线。

60. 发明授权

US08611164B2 Device and method for detecting resistive defect 有权
标题翻译：用于检测电阻缺陷的装置和方法
公开(公告)号：US08611164B2
公开(公告)日：2013-12-17
申请号：US13195114
申请日：2011-08-01
申请人： George Maria Braceras , Harold Pilo , George E. Rudgers
发明人： George Maria Braceras , Harold Pilo , George E. Rudgers
IPC分类号： G11C29/00 , G11C7/12
CPC分类号： G11C29/025 , G11C11/41 , G11C29/50008 , G11C2029/1202 , G11C2029/1204
摘要： The invention provides a device and method for detecting a resistive defect in a static random access memory (SRAM) device. A first aspect of the invention provides a static random access memory (SRAM) device comprising: a bitline; a wordline; a bitline precharge circuit electrically connected to the bitline and adapted to provide to the bitline a first precharge voltage for precharging the bitline during normal operation of the SRAM device and a second precharge voltage less than the first precharge voltage for testing the SRAM device for a resistive defect between the bitline and the wordline.
摘要翻译：本发明提供一种用于检测静态随机存取存储器（SRAM）装置中的电阻性缺陷的装置和方法。本发明的第一方面提供了一种静态随机存取存储器（SRAM）装置，包括：位线; 一字电位连接到所述位线的位线预充电电路，并且适于向所述位线提供用于在所述SRAM器件的正常操作期间对所述位线进行预充电的第一预充电电压以及小于所述第一预充电电压的第二预充电电压，以用于测试所述SRAM器件的电阻位线和字线之间的缺陷。

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