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51. 发明授权

US09472758B2 High endurance non-volatile storage 有权
标题翻译：高耐久性非易失性存储
公开(公告)号：US09472758B2
公开(公告)日：2016-10-18
申请号：US14538763
申请日：2014-11-11
申请人： SANDISK 3D LLC
发明人： Zhida Lan , Abhijit Bandyopadhyay , Christopher Petti , Li Xiao , Girish Nagavarapu
IPC分类号： G11C5/02 , H01L45/00 , G11C13/00 , H01L27/24
CPC分类号： H01L45/16 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0069 , G11C2013/0083 , G11C2013/0092 , G11C2213/71 , G11C2213/77 , G11C2213/78 , G11C2213/79 , H01L27/2481 , H01L27/249 , H01L45/04 , H01L45/146 , H01L45/1683
摘要： The manufacturing of the non-volatile storage system includes depositing one or more layers of reversible resistance-switching material for a non-volatile storage element. Prior to operation, either during manufacturing or afterwards, a forming operation is performed. In one embodiment, the forming operation includes applying a forming voltage to the one or more layers of reversible resistance-switching material to form a first region that includes a resistor and a second region that can reversibly change resistance at a low current, the resistor is formed in response to the forming condition and is not deposited on the device. In some embodiments, programming the non-volatile storage element includes applying a programming voltage that increases in voltage over time at low current but does not exceed the final forming voltage.
摘要翻译：非易失性存储系统的制造包括为非易失性存储元件沉积一层或多层可逆电阻切换材料。在操作之前，在制造期间或之后，进行成形操作。在一个实施例中，形成操作包括向一个或多个可逆电阻切换材料层施加成形电压以形成包括电阻器的第一区域和可在低电流下可逆地改变电阻的第二区域，电阻器响应于成形条件而形成，并且不会沉积在该装置上。在一些实施例中，对非易失性存储元件的编程包括施加在低电流下随时间增加的电压但不超过最终形成电压的编程电压。

52. 发明申请

US20160276021A1 APPARATUSES AND METHODS FOR BI-DIRECTIONAL ACCESS OF CROSS-POINT ARRAYS 有权
公开(公告)号：US20160276021A1
公开(公告)日：2016-09-22
申请号：US15076185
申请日：2016-03-21
申请人： Micron Technology, Inc.
发明人： Hernan A. Castro
IPC分类号： G11C13/00
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0004 , G11C13/0069 , G11C2013/0073 , G11C2013/0092 , G11C2213/76
摘要： The disclosed technology generally relates to apparatuses and methods of operating the same, and more particularly to cross point memory arrays and methods of accessing memory cells in a cross point memory array. In one aspect, an apparatus comprises a memory array. The apparatus further comprises a memory controller configured to cause an access operation, where the access operation includes application of a first bias across a memory cell of the memory array for a selection phase of the access operation and application of a second bias, lower in magnitude than the first bias, across the memory cell for an access phase of the access operation. The memory controller is further configured to cause a direction of current flowing through the memory cell to be reversed between the selection phase and the access phase.

53. 发明授权

US09443587B1 Resistive memory apparatus and writing method thereof 有权
标题翻译：电阻式存储装置及其写入方法
公开(公告)号：US09443587B1
公开(公告)日：2016-09-13
申请号：US14804354
申请日：2015-07-21
申请人： Winbond Electronics Corp.
发明人： Frederick Chen , Meng-Hung Lin , Ping-Kun Wang , Shao-Ching Liao , Chuan-Sheng Chou
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0064 , G11C2013/0066 , G11C2013/0073 , G11C2013/0076 , G11C2013/0078 , G11C2013/0092
摘要： A resistive memory apparatus and a writing method thereof are provided. In the method, logic data is received, and a corresponding resistive memory cell is selected. A logic level of the logic data is determined. When the logic data is in a first logic level, where a first reading current of the corresponding resistive memory cell is greater than a first reference current, a set pulse and a reset pulse are provided to the resistive memory cell during a writing period. When the logic data is in a second logic level, where a second reading current of the resistive memory cell is smaller than a second reference current, the reset pulse is provided to the resistive memory cell during the writing period. Polarities of the reset pulse and the set pulse are opposite.
摘要翻译：提供了一种电阻式存储装置及其写入方法。在该方法中，接收逻辑数据，并且选择相应的电阻性存储单元。确定逻辑数据的逻辑电平。当逻辑数据处于第一逻辑电平（其中对应的电阻性存储单元的第一读取电流大于第一参考电流）时，在写入周期期间将设置脉冲和复位脉冲提供给电阻存储器单元。当逻辑数据处于第二逻辑电平时，其中电阻存储单元的第二读取电流小于第二参考电流，在写入周期期间将复位脉冲提供给电阻存储单元。复位脉冲和设定脉冲的极性相反。

54. 发明申请

US20160254051A1 Memory Systems and Memory Programming Methods 有权
公开(公告)号：US20160254051A1
公开(公告)日：2016-09-01
申请号：US15150168
申请日：2016-05-09
申请人： Micron Technology, Inc.
发明人： Richard E. Fackenthal , Simone Lombardo
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0011 , G11C13/003 , G11C13/0061 , G11C2013/0078 , G11C2013/0092
摘要： Memory systems and memory programming methods are described. In one arrangement, a memory system includes a memory cell configured to have a plurality of different memory states, an access circuit coupled with the memory cell and configured to provide a first signal to a memory element of the memory cell to program the memory cell from a first memory state to a second memory state, and a current source coupled with the memory cell and configured to generate a second signal which is provided to the memory element of the memory cell after the first signal to complete programming of the memory cell from the first memory state to the second memory state.

55. 发明申请

US20160196876A1 RESISTIVE MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：电阻记忆体装置及其操作方法
公开(公告)号：US20160196876A1
公开(公告)日：2016-07-07
申请号：US14979947
申请日：2015-12-28
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： YONG-KYU LEE , YEONG-TAEK LEE , DAE-SEOK BYEON , CHI-WEON YOON
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C5/063 , G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/0064 , G11C2013/0078 , G11C2013/0092 , G11C2213/72
摘要： A resistive memory device includes a memory cell array that has a plurality of resistive memory cells that are arranged respectively on regions where a plurality of first signal lines and a plurality of second signal lines cross each other. A write circuit is connected to a selected first signal line that is connected to a selected memory cell from among the plurality of memory cells, and provides pulses to the selected memory cell. A voltage detector detects a node voltage at a connection node between the selected first signal line and the write circuit. A voltage generation circuit generates a first inhibit voltage and a second inhibit voltage that are applied respectively to unselected first and second signal lines connected to unselected memory cells from among the plurality of memory cells, and changes a voltage level of the second inhibit voltage based on the node voltage that is detected.
摘要翻译：电阻式存储器件包括存储单元阵列，该存储单元阵列具有分别布置在多个第一信号线和多个第二信号线彼此交叉的区域上的多个电阻存储单元。写入电路连接到从多个存储器单元中连接到所选择的存储器单元的所选择的第一信号线，并向所选存储单元提供脉冲。电压检测器检测所选择的第一信号线和写入电路之间的连接节点处的节点电压。电压产生电路产生分别施加到从多个存储单元中连接到未选择的存储单元的未选择的第一和第二信号线的第一禁止电压和第二禁止电压，并且基于检测到的节点电压。

56. 发明授权

US09378817B2 Variable resistance nonvolatile memory element writing method and variable resistance nonvolatile memory device 有权
标题翻译：可变电阻非易失性存储元件写入方法和可变电阻非易失性存储器件
公开(公告)号：US09378817B2
公开(公告)日：2016-06-28
申请号：US13581925
申请日：2012-03-22
申请人： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh
发明人： Ken Kawai , Kazuhiko Shimakawa , Yoshikazu Katoh
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/0064 , G11C2013/0073 , G11C2013/0083 , G11C2013/0092
摘要： A variable resistance nonvolatile memory element writing method of, by applying a voltage pulse to a memory cell including a variable resistance element, reversibly changing the variable resistance element between a first resistance state and a second resistance state according to a polarity of the applied voltage pulse is provided. The variable resistance nonvolatile memory element writing method includes applying a first preliminary voltage pulse and subsequently applying the first voltage pulse to the variable resistance element to change the variable resistance element from the second resistance state to the first resistance state, the first preliminary voltage pulse being smaller in voltage absolute value than the second threshold voltage and different in polarity from the first voltage pulse.
摘要翻译：一种可变电阻非易失性存储元件写入方法，通过向包括可变电阻元件的存储单元施加电压脉冲，根据所施加的电压脉冲的极性可逆地改变第一电阻状态和第二电阻状态之间的可变电阻元件被提供。可变电阻非易失性存储元件写入方法包括施加第一初步电压脉冲，并随后将第一电压脉冲施加到可变电阻元件，以将可变电阻元件从第二电阻状态改变到第一电阻状态，第一初步电压脉冲为电压绝对值比第二阈值电压小，并且极性与第一电压脉冲不同。

57. 发明授权

US09355722B2 Method of writing data of a nonvolatile semiconductor memory device including setting and removing operations 有权
标题翻译：写入包括设置和移除操作的非易失性半导体存储器件的数据的方法
公开(公告)号：US09355722B2
公开(公告)日：2016-05-31
申请号：US14806380
申请日：2015-07-22
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Junya Matsunami
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0097 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0064 , G11C13/0069 , G11C2013/0092 , G11C2213/71 , G11C2213/73
摘要： A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory cells provided one at each of intersections of a plurality of first lines and a plurality of second lines and each storing data by a data storing state of a filament; and a control circuit configured to execute a write sequence that writes data to the memory cell, the write sequence including: a setting operation that applies a setting pulse having a first polarity to the memory cell; and a removing operation that applies a removing pulse having a second polarity opposite to the first polarity to the memory cell; and the control circuit, during execution of the write sequence, is configured to repeatedly execute the setting operation until the memory cell attains a desired data storing state, and then to execute the removing operation.
摘要翻译：根据实施例的非易失性半导体存储器件包括：存储单元阵列，包括在多个第一线和多条第二线的每个交点处设置的多个存储单元，并且每个存储单元通过数据存储状态存储数据灯丝; 以及控制电路，被配置为执行向存储单元写入数据的写入序列，所述写入序列包括：将具有第一极性的设置脉冲施加到所述存储器单元的设置操作; 以及将具有与第一极性相反的第二极性的去除脉冲施加到存储单元的去除操作; 并且控制电路在执行写入顺序期间被配置为重复执行设置操作，直到存储器单元达到期望的数据存储状态，然后执行去除操作。

58. 发明授权

US09355721B2 Resistive memory device and operating method 有权
标题翻译：电阻式存储器件及操作方法
公开(公告)号：US09355721B2
公开(公告)日：2016-05-31
申请号：US14800727
申请日：2015-07-16
申请人： Chi-Weon Yoon , Hyun-Kook Park , Dae-Seok Byeon
发明人： Chi-Weon Yoon , Hyun-Kook Park , Dae-Seok Byeon
IPC分类号： G11C11/34 , G11C16/04 , G11C13/00
CPC分类号： G11C13/0069 , G11C7/04 , G11C11/1675 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0061 , G11C2013/0071 , G11C2013/0083 , G11C2013/0092
摘要： A method of operating a memory device includes; applying a pre-write voltage to a selected memory cell by applying a first voltage to a first signal line connected to the selected memory cell and a second voltage to a second signal line connected to the selected memory cell during a first set writing interval, wherein a level of the first voltage is higher than a level of the second voltage, and thereafter, applying a write voltage to the selected memory cell by applying a third voltage having a level lower than the level of the first voltage and higher than the level of the second voltage to the first signal line during a second set writing interval.
摘要翻译：操作存储器件的方法包括：通过在连接到所选存储单元的第一信号线上施加第一电压并将第二电压施加到在第一设定写入间隔期间连接到所选存储单元的第二信号线，将预写电压施加到所选择的存储单元，其中所述第一电压的电平高于所述第二电压的电平，然后通过施加具有低于所述第一电压的电平的电平的第三电压并高于所述第一电压的电平而对所选择的存储单元施加写入电压在第二设定写入间隔期间到第一信号线的第二电压。

59. 发明授权

US09343149B2 Enhancing nucleation in phase-change memory cells 有权
标题翻译：在相变记忆细胞中增强成核
公开(公告)号：US09343149B2
公开(公告)日：2016-05-17
申请号：US14328536
申请日：2014-07-10
申请人： Micron Technology, Inc.
发明人： Agostino Pirovano , Fabio Pellizzer , Anna Maria Conti , Davide Fugazza , Johannes A. Kalb
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0069 , G11C2013/0083 , G11C2013/0092
摘要： Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described.
摘要翻译：本文公开的各种实施例包括用于将存储器阵列的相变存储器（PCM）单元放置在其中在应用随后的SET编程信号之前增强PCM单元的成核概率的温度状态的方法和装置。在一个实施例中，该方法包括将成核信号施加到PCM单元以在存储器阵列内形成成核位置，其中成核信号具有非零上升沿。随后施加编程信号以在所述多个PCM单元的选定的单元内实现期望的结晶度。还描述了附加的方法和装置。

60. 发明申请

US20160125938A1 PHASE CHANGE MEMORY WITH METASTABLE SET AND RESET STATES 审中-公开
标题翻译：相变更改存储器与可复制的设置和复位状态
公开(公告)号：US20160125938A1
公开(公告)日：2016-05-05
申请号：US14749161
申请日：2015-06-24
申请人： International Business Machines Corporation
发明人： Matthew J. BrightSky , SangBum Kim , Wanki Kim , Chung H. Lam
IPC分类号： G11C13/00 , H01L45/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C13/0097 , G11C2013/0078 , G11C2013/0083 , G11C2013/0092 , H01L45/06 , H01L45/144
摘要： A memory device that includes a phase change material. The phase change material is programmable to a metastable set state and metastable reset state. Furthermore, the phase change material includes an initial state with an initial electrical resistance between the set electrical resistance and the reset electrical resistance. The initial state is at a lower potential energy than the set state and the reset state. Thus, the electrical resistance of the phase change material programmed to the set state or the reset state drifts toward the initial electrical resistance over time. The memory device also includes a first electrode electrically coupled to a first area of the phase change material, and a second electrode electrically coupled to a second area of the phase change material.
摘要翻译：一种包括相变材料的存储器件。相变材料可编程为亚稳态和亚稳态复位状态。此外，相变材料包括在设定的电阻和复位电阻之间具有初始电阻的初始状态。初始状态处于比设定状态和复位状态低的势能。因此，被编程到设定状态或复位状态的相变材料的电阻随时间漂移到初始电阻。存储器件还包括电耦合到相变材料的第一区域的第一电极和电耦合到相变材料的第二区域的第二电极。

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