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51. 发明申请

US20140153312A1 MEMORY CELLS HAVING FERROELECTRIC MATERIALS 有权
标题翻译：具有电磁材料的记忆体
公开(公告)号：US20140153312A1
公开(公告)日：2014-06-05
申请号：US13690957
申请日：2012-11-30
申请人： MICRON TECHNOLOGY, INC.
发明人： Gurtej S. Sandhu , D.V. Nirmal Ramaswamy
IPC分类号： H01L29/82 , G11C11/22
CPC分类号： G11C11/22 , G11C13/0007 , G11C13/0069 , G11C2213/54 , G11C2213/55 , H01L21/28291 , H01L27/2463 , H01L28/55 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1616
摘要： Memory cells having ferroelectric materials and methods of operating and forming the same are described herein. As an example, a memory cell can include a first electrode and a second electrode, and an ion source and a ferroelectric material formed between the first electrode and the second electrode, where the ferroelectric material serves to stabilize storage of ions transitioned from the ion source.
摘要翻译：具有铁电材料的存储单元以及操作和形成铁电材料的方法在此描述。作为示例，存储单元可以包括第一电极和第二电极，以及形成在第一电极和第二电极之间的离子源和铁电材料，其中铁电体材料用于稳定从离子源转移的离子的存储。

52. 发明授权

US08686774B2 Control circuit and data hold device using the control circuit 有权
标题翻译：控制电路和数据保持装置使用控制电路
公开(公告)号：US08686774B2
公开(公告)日：2014-04-01
申请号：US13332558
申请日：2011-12-21
申请人： Hiromitsu Kimura , Yoshinobu Ichida
发明人： Hiromitsu Kimura , Yoshinobu Ichida
IPC分类号： H03K3/00
CPC分类号： H03K3/45 , G06F1/3237 , G11C11/22 , G11C11/2275 , G11C29/022 , G11C29/32 , G11C2029/5002 , H03K3/356008 , Y02D10/128
摘要： A control circuit 10 includes an internal clock generating portion (12), which starts generating an internal clock signal (LCLK) required by a control portion (11) to perform action when a specific signal pattern appears in a trigger signal, continually generates the internal clock signal (LCLK) at least before the control portion (11) completes predetermined processing, and then stops generating the internal clock signal (LCLK); and the control portion (11), which uses the internal clock signal (LCLK) to perform the predetermined processing.
摘要翻译：控制电路10包括内部时钟产生部分（12），当特定信号模式出现在触发信号中时，开始产生控制部分（11）所需的内部时钟信号（LCLK）以执行动作，连续地产生内部至少在控制部分（11）完成预定处理之前，然后停止产生内部时钟信号（LCLK）; 以及使用内部时钟信号（LCLK）执行预定处理的控制部分（11）。

53. 发明申请

US20140063905A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF MEASURING WRITE CURRENT AND METHOD FOR MEASURING WRITE CURRENT 有权
标题翻译：可测量写入电流的半导体存储器件和用于测量写入电流的方法
公开(公告)号：US20140063905A1
公开(公告)日：2014-03-06
申请号：US13720974
申请日：2012-12-19
申请人： SK HYNIX INC.
发明人： Chang Yong AHN , Ho Seok EM
IPC分类号： G11C29/50 , G11C11/21
CPC分类号： G11C29/50 , G11C11/21 , G11C11/22 , G11C13/00 , G11C16/00 , G11C29/50008 , G11C2029/5006
摘要： A method for measuring a write current of a semiconductor memory device includes the steps of: programming initial data into memory cells which are to be programmed substantially at the same time; determining whether the memory cells are programmed into the same state or not; inputting test data when the memory cells are programmed into the same state; setting write current paths of the memory cells by comparing the initial data and the test data; and measuring a write current consumed when the test data are programmed into the memory cells.
摘要翻译：一种用于测量半导体存储器件的写入电流的方法包括以下步骤：将初始数据编程到基本上同时被编程的存储器单元中; 确定存储器单元是否被编程为相同的状态; 当存储器单元被编程到相同的状态时输入测试数据; 通过比较初始数据和测试数据来设置存储器单元的写入电流路径; 并测量当测试数据被编程到存储器单元中时所消耗的写入电流。

54. 发明申请

US20140050008A1 Electronic Device and Method for FRAM Power Supply Management 有权
标题翻译： FRAM电源管理电子设备及方法
公开(公告)号：US20140050008A1
公开(公告)日：2014-02-20
申请号：US13050529
申请日：2011-03-17
申请人： Ruediger Kuhn , Adi Baumann , Ronald Nerlich , Matthias Arnold , Christian Sichert , Ralph Ledwa
发明人： Ruediger Kuhn , Adi Baumann , Ronald Nerlich , Matthias Arnold , Christian Sichert , Ralph Ledwa
IPC分类号： G11C11/22
CPC分类号： G11C11/2297 , G11C11/22
摘要： The invention is an electronic device including a ferroelectric random access memory (FRAM), a first supply voltage domain, a second supply voltage domain and a low drop output voltage regulator (LDO) receive a first supply voltage of the first supply voltage domain and providing a second supply voltage of the second supply voltage domain. The second supply voltage domain supplies the FRAM. The LDO switches between a first state providing and maintaining the second supply voltage of the second supply voltage domain and a second state providing a high impedance output to the second supply voltage domain. The electronic device switches the LDO from the first state to the second state in response to a failure of the first supply voltage domain.
摘要翻译：本发明是一种包括铁电随机存取存储器（FRAM），第一电源电压域，第二电源电压域和低压降输出稳压器（LDO）的电子设备，其接收第一电源电压域的第一电源电压并提供第二电源电压域的第二电源电压。第二个电源电压域供应FRAM。 LDO在提供和维持第二电源电压域的第二电源电压的第一状态和向第二电源电压域提供高阻抗输出的第二状态之间切换。电子设备响应于第一电源电压域的故障将LDO从第一状态切换到第二状态。

55. 发明申请

US20140010031A1 METHOD FOR ESTIMATING CHANNEL CHARACTERISTICS OF NONVOLATILE MEMORY DEVICE 有权
标题翻译：估计非易失性存储器件的通道特性的方法
公开(公告)号：US20140010031A1
公开(公告)日：2014-01-09
申请号：US13767598
申请日：2013-02-14
申请人： KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY , SK HYNIX INC.
发明人： Seok Hwan CHOI , Joong Seob YANG , Seung Ho CHANG , Sang Sik KIM , Sang Chul LEE , Ho Yeon LEE , Jaekyun MOON , Jaehyeong NO
IPC分类号： G11C29/04
CPC分类号： G11C29/04 , G11C11/16 , G11C11/22 , G11C13/00 , G11C16/00 , G11C29/50004 , G11C2029/5002
摘要： A method for estimating channel characteristics of a nonvolatile memory device including a plurality of memory cells includes the steps of: calculating first threshold voltage distributions of the memory cells programmed according to input data, based on the input data and a physical structure of the memory cells; calculating second threshold voltage distributions of the memory cells, based on output data and the physical structure of the memory cells; and analyzing the relation between the first and second threshold voltage distributions, using a mask.
摘要翻译：一种用于估计包括多个存储单元的非易失性存储器件的通道特性的方法，包括以下步骤：基于输入数据和存储单元的物理结构，计算根据输入数据编程的存储器单元的第一阈值电压分布 ; 基于输出数据和存储器单元的物理结构计算存储器单元的第二阈值电压分布; 以及使用掩模分析第一和第二阈值电压分布之间的关系。

56. 发明授权

US08611142B2 Magnetic recording device and magnetic recording apparatus 失效
标题翻译：磁记录装置和磁记录装置
公开(公告)号：US08611142B2
公开(公告)日：2013-12-17
申请号：US13299130
申请日：2011-11-17
申请人： Shiho Nakamura , Hirofumi Morise , Satoshi Yanagi , Daisuke Saida , Akira Kikitsu
发明人： Shiho Nakamura , Hirofumi Morise , Satoshi Yanagi , Daisuke Saida , Akira Kikitsu
IPC分类号： G11C11/15 , G11C11/16 , G11C11/14 , G11C11/02
CPC分类号： G11C11/22 , G11B5/66 , G11C11/16 , G11C11/161 , G11C11/1675
摘要： An example magnetic recording device includes a laminated body. The laminated body includes a first ferromagnetic layer with a magnetization substantially fixed in a first direction; a second ferromagnetic layer with a variable magnetization direction; a first nonmagnetic layer disposed between the first ferromagnetic layer and the second ferromagnetic layer; a third ferromagnetic layer with a variable magnetization direction; and a fourth ferromagnetic layer with a magnetization substantially fixed in a second direction, wherein at least one of the first and second direction is generally perpendicular to the film plane. The magnetization direction of the second ferromagnetic layer is determinable in response to the orientation of a current, by passing the current in a direction generally perpendicular to the film plane of the layers of the laminated body and the magnetization of the third ferromagnetic layer is able to undergo precession by passing the current.
摘要翻译：示例性磁记录装置包括层压体。层叠体包括具有在第一方向上基本固定的磁化的第一铁磁层; 具有可变磁化方向的第二铁磁层; 设置在所述第一铁磁层和所述第二铁磁层之间的第一非磁性层; 具有可变磁化方向的第三铁磁层; 以及具有在第二方向上基本固定的磁化的第四铁磁层，其中所述第一和第二方向中的至少一个大致垂直于所述膜平面。第二铁磁层的磁化方向可以通过使电流沿大致垂直于层叠体的层的膜平面的方向流过电流的方向来确定，并且第三铁磁层的磁化能够通过传递目前进行进攻。

57. 发明授权

US08558295B2 Nonvolatile memory cell and method of manufacturing the same 有权
标题翻译：非易失性存储单元及其制造方法
公开(公告)号：US08558295B2
公开(公告)日：2013-10-15
申请号：US12838878
申请日：2010-07-19
申请人： Sung Min Yoon , Chun Won Byun , Shin Hyuk Yang , Sang Hee Park , Soon Won Jung , Seung Youl Kang , Chi Sun Hwang , Byoung Gon Yu
发明人： Sung Min Yoon , Chun Won Byun , Shin Hyuk Yang , Sang Hee Park , Soon Won Jung , Seung Youl Kang , Chi Sun Hwang , Byoung Gon Yu
IPC分类号： H01G7/06
CPC分类号： H01L29/6684 , B82Y10/00 , G11C11/22 , H01L21/28291 , H01L27/1159 , H01L29/78391
摘要： Provided are a nonvolatile memory cell and a method of manufacturing the same. The nonvolatile memory cell includes a memory transistor and a driver transistor. The memory transistor includes a semiconductor layer, a buffer layer, an organic ferroelectric layer, and a gate electrode, which are disposed on a substrate. The driver transistor includes the semiconductor layer, the buffer layer, a gate insulating layer, and the gate electrode, which are disposed on the substrate. The memory transistor and the driver transistor are disposed on the same substrate. The nonvolatile memory cell is transparent in a visible light region.
摘要翻译：提供一种非易失性存储单元及其制造方法。非易失性存储单元包括存储晶体管和驱动晶体管。存储晶体管包括设置在基板上的半导体层，缓冲层，有机铁电层和栅极电极。驱动晶体管包括设置在基板上的半导体层，缓冲层，栅极绝缘层和栅极电极。存储晶体管和驱动晶体管设置在同一衬底上。非易失性存储单元在可见光区域是透明的。

58. 发明授权

US08531896B2 Semiconductor system, semiconductor memory apparatus, and method for input/output of data using the same 有权
标题翻译：半导体系统，半导体存储装置以及使用其的数据的输入/输出方法
公开(公告)号：US08531896B2
公开(公告)日：2013-09-10
申请号：US13219656
申请日：2011-08-27
申请人： Yong Kee Kwon , Hyung Dong Lee , Young Suk Moon , Hyung Gyun Yang , Sung Wook Kim
发明人： Yong Kee Kwon , Hyung Dong Lee , Young Suk Moon , Hyung Gyun Yang , Sung Wook Kim
IPC分类号： G11C7/00 , G11C7/22 , G11C11/22
CPC分类号： G11C7/22 , G06F2213/0038 , G11C7/1063 , G11C7/1066 , G11C7/222 , G11C11/22
摘要： A semiconductor system, a semiconductor memory apparatus, and a method for input/output of data using the same are disclosed. The semiconductor system includes a controller and a memory apparatus where the controller is configured to transmit a clock signal, a data output command, an address signal, and a second strobe signal to a memory apparatus. The memory apparatus is configured to provide data to the controller in synchronization with the second strobe signal, and in response to the clock signal, the data output command, the address signal, and the second strobe signal received from the controller.
摘要翻译：公开了一种半导体系统，半导体存储装置和使用其的数据的输入/输出方法。半导体系统包括控制器和存储装置，其中控制器被配置为向存储装置发送时钟信号，数据输出命令，地址信号和第二选通信号。存储装置被配置为与第二选通信号同步地向控制器提供数据，并且响应于从控制器接收到的时钟信号，数据输出命令，地址信号和第二选通信号。

59. 发明授权

US08482954B2 Semiconductor memory and method for operating the semiconductor memory 有权
标题翻译：用于操作半导体存储器的半导体存储器和方法
公开(公告)号：US08482954B2
公开(公告)日：2013-07-09
申请号：US13224158
申请日：2011-09-01
申请人： Mitsuharu Nakazawa
发明人： Mitsuharu Nakazawa
IPC分类号： G11C11/22 , G11C8/00
CPC分类号： G11C8/08 , G11C8/10 , G11C11/22
摘要： A semiconductor memory includes memory cells; word lines coupled to the memory cells; plate lines coupled to the memory cells; a selector that selects a first address signal in a first period and select a second address signal in a second period; a decode circuit that sequentially decodes the first and the second address signals selected by the selector, sequentially generates decode address signals based on the decoded first and second address signals, and sequentially activates the generated decode address signals; and a driver circuit that drives the word lines in accordance with the decode address signals activated based on the first address signal and drives the plate lines in accordance with the decode address signals activated based on the second address signal.
摘要翻译：半导体存储器包括存储单元; 耦合到存储器单元的字线; 耦合到存储器单元的板线; 选择器，其在第一周期中选择第一地址信号，并在第二周期中选择第二地址信号; 依次对由选择器选择的第一和第二地址信号进行解码的解码电路依次解码的第一和第二地址信号产生解码地址信号，并且顺序地激活所生成的解码地址信号; 以及驱动电路，其根据基于第一地址信号激活的解码地址信号来驱动字线，并根据基于第二地址信号激活的解码地址信号驱动板线。

60. 发明授权

US08472236B2 Differential plate line screen test for ferroelectric latch circuits 有权
公开(公告)号：US08472236B2
公开(公告)日：2013-06-25
申请号：US13626531
申请日：2012-09-25
申请人： Texas Instruments Incorporated
发明人： Scott R. Summerfelt , John Anthony Rodriguez , Hugh P. McAdams , Steven Craig Bartling
IPC分类号： G11C11/22
CPC分类号： G11C29/50 , G11C11/22
摘要： Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability.

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