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51. 发明申请

US20050262465A1 Handling of unused coreware with embedded boundary scan chains to avoid the need of a boundary scan synthesis tool during custom instance creation 有权
标题翻译：使用嵌入式边界扫描链处理未使用的核心软件，以避免在自定义实例创建期间需要边界扫描综合工具
公开(公告)号：US20050262465A1
公开(公告)日：2005-11-24
申请号：US10847692
申请日：2004-05-18
申请人： Saket Goyal
发明人： Saket Goyal
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5068 , G06F2217/64
摘要： A method and system is provided for handling unused structures in a slice during custom instance creation to avoid the need of a boundary scan synthesis tool, wherein the slice includes an embedded boundary scan chain having a particular length and order. Aspects of the present invention include using a software tool during slice creation to create at least one slice connectivity file. During instance creation, a customer designs a custom chip using the software tool by selecting which structures are to be use on the slice. The slice connectivity file is then reused for the instance by reading the connectivity file to determine which structures in the file are used and not used based on the customer's selections. Thereafter, the slice is reconfigured to include dummy logic in unused structures, such that the boundary scan chain retains the same length and order.
摘要翻译：提供了一种方法和系统，用于在自定义实例创建期间处理切片中的未使用的结构，以避免边界扫描合成工具的需要，其中切片包括具有特定长度和顺序的嵌入式边界扫描链。本发明的方面包括在切片创建期间使用软件工具来创建至少一个切片连接文件。在创建实例期间，客户通过选择要在片上使用哪些结构，使用软件工具设计定制芯片。然后，切片连接文件通过读取连接文件重新用于实例，以根据客户的选择确定文件中的哪些结构被使用和不被使用。此后，重新配置切片以在未使用的结构中包括虚拟逻辑，使得边界扫描链保持相同的长度和顺序。

52. 发明申请

US20040128626A1 Placement of configurable input/output buffer structures during design of integrated circuits 失效
公开(公告)号：US20040128626A1
公开(公告)日：2004-07-01
申请号：US10334568
申请日：2002-12-31
申请人： LSI Logic Corporation
发明人： Matthew Scott Wingren , George Wayne Nation , Gary Scott Delp , Jonathan William Byrn
IPC分类号： G06F017/50
CPC分类号： G06F17/5045 , G06F2217/64
摘要： A tool for designing an integrated circuit and semiconductor product that generates correct RTL for I/O buffer structures in consideration of the requirements of diffused configurable I/O blocks and/or I/O hardmacs of the product. Given either a slice description of a partially manufactured semiconductor product, a designer can generate the I/O resources of an application set. Then given an application set having a transistor fabric, and the diffused configurable I/O blocks and/or the I/O hardmacs, and a plurality of accompanying shells, the I/O generation tool herein automatically reads a database having the slice description and generates the I/O buffer structures from the transistor fabric. The I/O generation tool further conditions and integrates input from either or both customer having her/his own logic and requesting a specific semiconductor product or from IP cores with their preestablished logic. The I/O generation tool creates correct RTL from the transistor fabric for correct placement, timing, testing, and function of I/O buffer amplifiers for the semiconductor product, either incrementally or globally. Once I/O buffer structures are created, they are qualified by a plurality of shells including a verification shell, a static timing analysis shell, a manufacturing test shell, and a RTL analysis shell.

53. 发明申请

US20180366367A1 EFFECTIVE SUBSTITUTION OF GLOBAL DISTRIBUTED HEAD SWITCH CELLS WITH CLUSTER HEAD SWITCH CELLS 审中-公开
公开(公告)号：US20180366367A1
公开(公告)日：2018-12-20
申请号：US15625754
申请日：2017-06-16
申请人： QUALCOMM Incorporated
发明人： Rajesh ARIMILLI , Sabyasachi SARKAR , Gaurav ARYA
IPC分类号： H01L21/762 , H01L27/118 , G06F17/50 , H01L21/768 , H01L23/48 , H05K1/02
CPC分类号： G06F17/5072 , G06F17/5068 , G06F2217/64 , G06F2217/66 , H01L21/768 , H01L27/0207 , H01L27/11807 , H01L2027/11881
摘要： An IC includes a first IC portion and a second IC portion. The IC includes a first set of standard cells in the first IC portion. The IC includes a plurality of memory cells and a second set of standard cells in the second IC portion. The second set of standard cells is located in channels between the memory cells. The IC further includes a plurality of GDHS cells in the first IC portion. The GDHS cells are configured to switch power on and to switch power off to the first set of standard cells. The IC further includes a plurality of CHS cells in the first IC portion. The CHS cells are configured to switch power on and to switch power off to the second set of standard cells in the second IC portion.

54. 发明申请

US20180034412A1 TAPPED INDUCTOR VOLTAGE CONTROLLED OSCILLATOR 审中-公开
公开(公告)号：US20180034412A1
公开(公告)日：2018-02-01
申请号：US15725964
申请日：2017-10-05
申请人： Futurewei Technologies, Inc.
发明人： Michael L. Bushman , Charles J. Duey , James W. Caldwell
IPC分类号： H03B5/12 , G06F17/50
CPC分类号： H03B5/1228 , G06F17/5063 , G06F17/5068 , G06F2217/64 , H03B5/1206 , H03B5/1212 , H03B5/1243 , H03B5/1259 , H03B5/1296 , H03B2200/0012 , H03B2200/004
摘要： A voltage controlled oscillator includes a resonator and an amplifier. The resonator includes a capacitive element and an inductive element. The inductive element has a plurality of conductive segments forming a physical loop. The inductive element has electrical connections on the physical loop to the plurality of conductive segments forming at least one electrical loop disposed within an interior space formed by the physical loop. The amplifier has an input and an output, the input coupled to a first conductive segment forming a first impedance and the output coupled to a second conductive segment forming a second impedance.

55. 发明申请

US20170220727A1 Application specific integrated circuit (ASIC) test screens and selection of such screens 有权
公开(公告)号：US20170220727A1
公开(公告)日：2017-08-03
申请号：US15012331
申请日：2016-02-01
申请人： GLOBALFOUNDRIES INC.
发明人： Eric D. Hunt-Schroeder , John R. Goss , Igor Arsovski , Paul J. Grzymkowski
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/64
摘要： Various embodiments include approaches for analyzing a customer design for an application specific integrated circuit (ASIC). In some cases, an approach includes: determining performance requirements of the customer design; querying a test screen database for the performance requirements of the customer design, the test screen database having failure thresholds and associated test screens for detecting the failure thresholds for a set of ASIC devices; generating a filter database including select failure thresholds and associated test screens for the performance requirements of the customer design; and selecting a set of test screens from the filter database based upon a yield cost criteria in forming the ASIC.

56. 发明授权

US09251305B1 Method and apparatus for analyzing structured cell candidates for structured application specific integrated circuits 有权
标题翻译：用于分析结构化专用集成电路的结构化单元候选的方法和装置
公开(公告)号：US09251305B1
公开(公告)日：2016-02-02
申请号：US12287993
申请日：2008-10-14
申请人： Gregg William Baeckler
发明人： Gregg William Baeckler
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/64
摘要： A method for evaluating structured cells is disclosed. Functions that may be implemented by a candidate structured cell are identified. A cell library having a subset of functions that may be implemented by the structured cell is generated. A system is implemented on a target device using the functions in the cell library. The system on the target device is evaluated.
摘要翻译：公开了一种用于评估结构化单元的方法。识别可由候选结构化单元实现的功能。生成具有可由结构化单元实现的功能子集的单元库。使用单元库中的功能在目标设备上实现系统。评估目标设备上的系统。

57. 发明申请

US20150205902A1 Communicating Configuration Information Across A Programmable Analog Tile to Another Tile 有权
标题翻译：将可编程模拟平铺中的配置信息通信到另一个平铺
公开(公告)号：US20150205902A1
公开(公告)日：2015-07-23
申请号：US14672083
申请日：2015-03-27
申请人： Active-Semi, Inc.
发明人： Steven Huynh , Matthew A. Grant , Gary M. Hurtz , David J. Kunst , Trey A. Roessig
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F1/26 , G06F1/3203 , G06F12/1408 , G06F17/5063 , G06F2217/64 , G06F2217/78
摘要： A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.
摘要翻译：通过将第一集成电路瓦片中的瓦片配置信息通过第二集成电路瓦片传送到第三集成电路瓦片，在标准化总线上配置可编程模拟瓦片集成电路。三个集成电路瓦片中的每一个是集成电路的一部分。当瓦片彼此相邻放置时，形成标准化总线。相邻瓦片的数据总线和控制信号导体排列并互连，使得每个信号导体电连接到每个瓦片。可以使用数据总线和控制线将瓦片配置信息写入由任何所选择的瓦片中的地址识别的所选择的寄存器，而不管瓦片发送和瓦片接收信息的相对物理位置。因此，瓦片配置信息可以通过任何数量的中间瓦片从一个瓦片传递到另一个瓦片。

58. 发明申请

US20150113495A1 DESIGN STRUCTURE FOR LOGIC CIRCUIT AND SERIALIZER-DESERIALIZER STACK 有权
标题翻译：逻辑电路设计结构和串级设备堆栈
公开(公告)号：US20150113495A1
公开(公告)日：2015-04-23
申请号：US14151331
申请日：2014-01-09
申请人： International Business Machines Corporation
发明人： Michael J. Shapiro , William F. Van Duyne
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/02 , G06F2217/06 , G06F2217/08 , G06F2217/38 , G06F2217/40 , G06F2217/64 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/13025 , H01L2224/131 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2924/14 , H01L2924/1421 , H01L2924/1431 , H01L2924/1433 , H01L2924/15311 , H01L2924/157 , H01L2924/16251 , H01L2924/163 , H01L2924/014 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Serializer-deserializer (SERDES) and integrated circuit package including a package substrate, first and second SERDES dies having a SERDES circuit, and a logic die having a logic circuit. The SERDES circuit communicatively connected to the package substrate. The first and second SERDES dies positioned adjacent, in a plane, and disposed on the package substrate. The logic circuit communicatively connected to the SERDES circuit and to the package substrate. The logic die stacked vertically and disposed on the first and second SERDES dies. A method of assembling a SERDES and integrated circuit package including providing a SERDES structure selected from a menu of SERDES die and SERDES circuit combinations. A design structure of a SERDES and integrated circuit package including a package substrate, first and second SERDES dies having a SERDES circuit, and a logic die having a logic circuit. The SERDES circuit communicatively connected to the package substrate.
摘要翻译：串行器解串器（SERDES）和集成电路封装，包括封装衬底，具有SERDES电路的第一和第二SERDES管芯和具有逻辑电路的逻辑管芯。 SERDES电路通信连接到封装衬底。第一和第二SERDES模具定位成相邻于平面并且设置在封装衬底上。逻辑电路通信连接到SERDES电路和封装衬底。垂直堆叠的逻辑管芯设置在第一和第二SERDES管芯上。一种组装SERDES和集成电路封装的方法，包括提供从SERDES管芯和SERDES电路组合的菜单中选择的SERDES结构。 SERDES和集成电路封装的设计结构，包括封装衬底，具有SERDES电路的第一和第二SERDES管芯以及具有逻辑电路的逻辑管芯。 SERDES电路通信连接到封装衬底。

59. 发明授权

US09003340B2 Communicating configuration information across a programmable analog tile to another tile 有权
标题翻译：将可编程模拟图块中的配置信息传递到另一个图块
公开(公告)号：US09003340B2
公开(公告)日：2015-04-07
申请号：US12322375
申请日：2009-01-30
申请人： Steven Huynh , Matthew A. Grant , Gary M. Hurtz , David J. Kunst , Trey A. Roessig
发明人： Steven Huynh , Matthew A. Grant , Gary M. Hurtz , David J. Kunst , Trey A. Roessig
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F1/26 , G06F1/3203 , G06F12/1408 , G06F17/5063 , G06F2217/64 , G06F2217/78
摘要： A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.
摘要翻译：通过将第一集成电路瓦片中的瓦片配置信息通过第二集成电路瓦片传送到第三集成电路瓦片，在标准化总线上配置可编程模拟瓦片集成电路。三个集成电路瓦片中的每一个是集成电路的一部分。当瓦片彼此相邻放置时，形成标准化总线。相邻瓦片的数据总线和控制信号导体排列并互连，使得每个信号导体电连接到每个瓦片。可以使用数据总线和控制线将瓦片配置信息写入由任何所选择的瓦片中的地址识别的所选择的寄存器，而不管瓦片发送和瓦片接收信息的相对物理位置。因此，瓦片配置信息可以通过任何数量的中间瓦片从一个瓦片传递到另一个瓦片。

60. 发明授权

US08884314B1 Circuitry configurable based on device orientation 有权
标题翻译：基于设备方向的电路配置
公开(公告)号：US08884314B1
公开(公告)日：2014-11-11
申请号：US13891874
申请日：2013-05-10
申请人： Jeffery J. Serre
发明人： Jeffery J. Serre
IPC分类号： H01L29/18 , H01L33/62 , H01L27/15
CPC分类号： H01L33/62 , G06F17/5045 , G06F17/5068 , G06F2217/64 , H01L21/485 , H01L23/5382 , H01L24/95 , H01L25/0753 , H01L25/50 , H01L2224/16225 , H01L2224/95085 , H01L2224/95101 , H01L2224/95146 , H01L2924/12041 , H01L2924/12042 , H01L2924/00
摘要： The present disclosure is directed to circuitry configurable based on device orientation. Example circuitry may comprise at least one device location and configurable conductors. The at least one device location may include at least two conductive pads onto which a device may be populated by a manufacturing process. The configurable conductors may be coupled to each of the at least two conductive pads. The configurable conductors may be configured by adding conductive material to at least one configurable conductor or subtracting at least part of at least one configurable conductor. For example, conductive material may be added to close a space between two segments of a configurable conductor to form a conduction path. Alternatively, at least part of at least one of a plurality of configurable conductors coupled to a conductive pad may be subtracted (e.g., cut) to stop conduction in the at least one configurable conductor.
摘要翻译：本公开涉及基于设备取向配置的电路。示例电路可以包括至少一个设备位置和可配置导体。至少一个设备位置可以包括至少两个导电焊盘，其上可以通过制造工艺填充设备。可配置导体可以耦合到至少两个导电焊盘中的每一个。可配置导体可以通过将导电材料添加到至少一个可配置导体或减去至少一个可配置导体的至少一部分来配置。例如，可以添加导电材料以封闭可配置导体的两个部分之间的空间以形成传导路径。或者，可以减去耦合到导电焊盘的多个可配置导体中的至少一个的至少一个，以便减少（例如，切割）以停止在至少一个可配置导体中的导通。

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