专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

US20160188752A1 DEFINING REUSABLE METRICS FOR ARCHITECTURAL OPTIMIZATION 审中-公开
标题翻译：定义用于建筑优化的可重用度量
公开(公告)号：US20160188752A1
公开(公告)日：2016-06-30
申请号：US14582217
申请日：2014-12-24
申请人： International Business Machines Corporation
发明人： Henry Broodney , Lior Limonad , Nir Mashkif , Michael Masin , Aviad Sela
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F2217/02
摘要： Methods, computing systems and computer program products implement embodiments of the present invention that include receiving, by a computer executing a system modeling application, a first input including multiple attributes and a second input including multiple components. The attribute set is associated with a plurality of the components in the system model, and based on a third input received that includes calculation parameters, one or more calculations are defined that include one or more of the attributes over the plurality of the components, thereby defining a metric for the system model.
摘要翻译：方法，计算系统和计算机程序产品实现本发明的实施例，其包括由执行系统建模应用的计算机接收包括多个属性的第一输入和包括多个组件的第二输入。属性集合与系统模型中的多个组件相关联，并且基于接收的包括计算参数的第三输入，定义包括多个组件中的一个或多个属性的一个或多个计算，从而定义系统模型的度量。

52. 发明授权

US09355205B2 Method and apparatus of a three dimensional integrated circuit 有权
标题翻译：三维集成电路的方法和装置
公开(公告)号：US09355205B2
公开(公告)日：2016-05-31
申请号：US14137679
申请日：2013-12-20
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chi-Wen Chang , Hui Yu Lee , Ya Yun Liu , Jui-Feng Kuan , Yi-Kan Cheng
IPC分类号： G06F17/50 , H01L23/48 , H01L25/065
CPC分类号： G06F17/5077 , G06F17/5072 , G06F2217/02 , G06F2217/66 , H01L21/76898 , H01L23/481 , H01L23/528 , H01L25/0657 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： An apparatus includes a first tier and a second tier. The second tier is above the first tier. The first tier includes a first cell. The second tier includes a second cell and a third cell. The third cell includes a first ILV to couple the first cell in the first tier to the second cell in the second tier. The third cell further includes a second ILV, the first ILV and the second ILV are extended along a first direction. The first tier further includes a fourth cell. The second tier further includes a fifth cell. The second ILV of the third cell is arranged to connect the fourth cell of the first tier with the fifth cell of the second tier. In some embodiments, the second tier further includes a spare cell including a spare ILV for ECO purpose.
摘要翻译：一种装置包括第一层和第二层。第二层高于第一层。第一层包括第一个单元格。第二层包括第二单元和第三单元。第三小区包括将第一层中的第一小区耦合到第二层中的第二小区的第一ILV。第三单元还包括第二ILV，第一ILV和第二ILV沿第一方向延伸。第一层还包括第四个单元格。第二层还包括第五个单元格。第三单元的第二ILV被布置成将第一层的第四单元与第二层的第五单元连接。在一些实施例中，第二层还包括备用单元，其包括用于ECO目的的备用ILV。

53. 发明授权

US09336339B2 Computer aided design method and system for modular layouts 有权
公开(公告)号：US09336339B2
公开(公告)日：2016-05-10
申请号：US14027963
申请日：2013-09-16
申请人： Squareclock
发明人： Eric Sellem
IPC分类号： G06T17/00 , G06F17/50 , G06Q30/06
CPC分类号： G06T17/00 , G06F17/5004 , G06F2217/02 , G06Q30/0601
摘要： The invention relates to the design of layouts for a room in which a user wishes to position elements figuring in a collection of catalogs. Prior art systems only allow incremental construction by making direct selections from one or more catalogs. The inventive system and procedure allow rapid, overall construction of several solutions satisfying a certain number of constraints determined by the room, the user or the distributor of the equipment to be positioned, as well as rules derived from experience in the field of the equipment concerned. The method is subdivided into the steps of spatial analysis, definition of layout templates, selection of candidates from the collection of catalogs and optimization of the positioning. The system permits simultaneous visualization in three dimensions of optimum solutions and the printing of two-dimensional assembly drawings. The procedure and the system are preferably applicable to kitchen layouts.

54. 发明授权

US09311438B1 Signal delay flip-flop cell for fixing hold time violation 有权
标题翻译：用于固定保持时间违规的信号延迟触发器单元
公开(公告)号：US09311438B1
公开(公告)日：2016-04-12
申请号：US14509037
申请日：2014-10-07
申请人： Amol Agarwal , Gaurav Goyal , Abhishek Mahajan , Sidhartha Taneja
发明人： Amol Agarwal , Gaurav Goyal , Abhishek Mahajan , Sidhartha Taneja
IPC分类号： G06F17/50 , H03K3/037 , H03K3/012
CPC分类号： G06F17/5031 , G06F2217/02 , G06F2217/84 , H03K3/012 , H03K3/0372 , H03K3/0375
摘要： A signal delay cell for use in resolving hold time violations in an IC has a first multiplexer having a first functional data input node and a scan data input node TI and a second multiplexer having a second functional data input node, a second input node connected to the output of the first multiplexer and a flip-flop module. The propagation of a data input signal applied to the first multiplexer is delayed, and the hold margin of the flip-flop module is increased by transit through the first multiplexer. The signal delay cell is available to replace a flip-flop having a scan data hold problem, and also for use in solving a functional data violation in the same or another cell.
摘要翻译：用于解决IC中的保持时间冲突的信号延迟单元具有第一多路复用器，其具有第一功能数据输入节点和扫描数据输入节点TI，第二多路复用器具有第二功能数据输入节点，第二输入节点连接到第一多路复用器和触发器模块的输出。施加到第一多路复用器的数据输入信号的传播被延迟，并且通过第一多路复用器的传输来增加触发器模块的保持余量。信号延迟单元可用于替换具有扫描数据保持问题的触发器，并且还用于解决相同或另一个单元中的功能数据违例。

55. 发明申请

US20160098506A1 SIGNAL DELAY FLIP-FLOP CELL FOR FIXING HOLD TIME VIOLATION 有权
标题翻译：信号延迟翻转细胞固定持续时间
公开(公告)号：US20160098506A1
公开(公告)日：2016-04-07
申请号：US14509037
申请日：2014-10-07
申请人： Amol Agarwal , Gaurav Goyal , Abhishek Mahajan , Sidharrtha Taneja
发明人： Amol Agarwal , Gaurav Goyal , Abhishek Mahajan , Sidharrtha Taneja
IPC分类号： G06F17/50 , H03K3/012 , H03K3/037
CPC分类号： G06F17/5031 , G06F2217/02 , G06F2217/84 , H03K3/012 , H03K3/0372 , H03K3/0375
摘要： A signal delay cell for use in resolving hold time violations in an IC has a first multiplexer having a first functional data input node and a scan data input node TI and a second multiplexer having a second functional data input node, a second input node connected to the output of the first multiplexer and a flip-flop module. The propagation of a data input signal applied to the first multiplexer is delayed, and the hold margin of the flip-flop module is increased by transit through the first multiplexer. The signal delay cell is available to replace a flip-flop having a scan data hold problem, and also for use in solving a functional data violation in the same or another cell.
摘要翻译：用于解决IC中的保持时间冲突的信号延迟单元具有第一多路复用器，其具有第一功能数据输入节点和扫描数据输入节点TI，第二多路复用器具有第二功能数据输入节点，第二输入节点连接到第一多路复用器和触发器模块的输出。施加到第一多路复用器的数据输入信号的传播被延迟，并且通过第一多路复用器的传输来增加触发器模块的保持余量。信号延迟单元可用于替换具有扫描数据保持问题的触发器，并且还用于解决相同或另一个单元中的功能数据违例。

56. 发明授权

US09306036B2 Nitride spacer for protecting a fin-shaped field effect transistor (finFET) device 有权
标题翻译：用于保护鳍状场效应晶体管（finFET）器件的氮化物间隔物
公开(公告)号：US09306036B2
公开(公告)日：2016-04-05
申请号：US13953833
申请日：2013-07-30
申请人： GLOBALFOUNDRIES Inc.
发明人： Michael Ganz
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L21/02362 , G06F17/505 , G06F2217/02 , H01L21/0217 , H01L27/0207 , H01L29/66636 , H01L29/66795 , H01L29/785
摘要： Approaches for protecting a semiconductor device (e.g., a fin field effect transistor device (FinFET)) using a nitride spacer are provided. Specifically, a nitride spacer is formed over an oxide and a set of fins of the FinFET device to mitigate damage during subsequent processing. The nitride spacer is deposited before the block layers to protect the oxide on top of a set of gates in an open area of the FinFET device uncovered by a photoresist. The oxide on top of each gate will be preserved throughout all of the block layers to provide hardmask protection during subsequent source/drain epitaxial layering. Furthermore, the fins that are open and uncovered by the photoresist or the set of gates remain protected by the nitride spacer. Accordingly, fin erosion caused by amorphization of the fins exposed to resist strip processes is prevented, resulting in improved device yield.
摘要翻译：提供了使用氮化物间隔物来保护半导体器件（例如，鳍式场效应晶体管器件（FinFET））的方法。具体地说，在FinFET器件的一个氧化物和一组鳍片之上形成一个氮化物间隔物，以减轻随后的处理过程中的损坏。在阻挡层之前沉积氮化物间隔物，以在未被光致抗蚀剂覆盖的FinFET器件的开放区域中的一组栅极的顶部上保护氧化物。每个栅极顶部的氧化物将保留在所有块层中，以在随后的源/漏外延层分层期间提供硬掩模保护。此外，由光致抗蚀剂或该组栅极打开和未覆盖的翅片仍然被氮化物间隔物保护。因此，防止由于暴露于抗蚀剂剥离处理的翅片的非晶化而引起的翅片侵蚀，从而提高了器件的产率。

57. 发明申请

US20160070825A1 METHOD FOR AUTOMATICALLY PRESENTING PAVEMENT SCHEME OF DECORATION PILES OR MARBLES 审中-公开
标题翻译：用于自动展示装饰柱或大小的摊铺方案的方法
公开(公告)号：US20160070825A1
公开(公告)日：2016-03-10
申请号：US14662205
申请日：2015-03-18
申请人： Jin YAO , Rujia LIU , Decai HE , Kun BAI , Hao LI , Bo WANG , Xingnan ZHANG , Xin FANG
发明人： Jin YAO , Rujia LIU , Decai HE , Kun BAI , Hao LI , Bo WANG , Xingnan ZHANG , Xin FANG
IPC分类号： G06F17/50
CPC分类号： G06F17/5004 , G06F2217/02 , G06F2217/04 , G06T19/20 , G06T2210/04 , G06T2219/2021 , G06T2219/2024
摘要： The present invention discloses a method for automatically presenting a pavement scheme of decoration piles or marbles, including: step 1), recording tiles, pictures of marbles, mosaic modelings, patterns of cross banding line frames, patterns of modeling tiles of each brand into a database of the brand in a QEYJ software according to a QEYJ rule; step 2), transforming all kinds of designs of tiles or marbles and pavement manners into computer description language and formulas of functions; step 3), in a 3D stereo scene, by calling the computer description language and formulas of functions, re-transforming various tiles, pictures of marbles, mosaic modelings, patterns of cross banding line frames, patterns of modeling tiles by calculation, to present them in the 3D scene of a region to be paved; and step 4), by recording and transmitting, the pavement pattern produced in the 3D stereo scene may be calculated, transformed, and re-presented in other scenes. The present invention is particularly suitable for quickly presenting paving effects to consumers and owners in sales industry for tiles, marbles and the like, and has a significant promotion value.
摘要翻译：本发明公开了一种自动呈现装饰桩或弹珠路面方案的方法，包括：步骤1）记录瓷砖，大理石图案，马赛克模拟，交叉条线框架图案，各品牌建模瓦片图案为根据QEYJ规则，QEYJ软件中的品牌数据库; 步骤2），将各种瓷砖或大理石和路面设计的设计转化为计算机描述语言和功能公式; 步骤3），在3D立体场景中，通过调用计算机描述语言和功能公式，重新变换各种瓦片，大理石的图片，马赛克模拟，交叉条带线框架的图案，通过计算建模瓦片的图案，以呈现他们在一个要铺成的地区的3D场景中; 和步骤4），通过记录和发送，可以在其他场景中计算，变换和重新呈现3D立体场景中产生的路面图案。本发明特别适用于向瓷砖，大理石等销售行业的消费者和业主快速呈现铺路效果，并具有显着的促进价值。

58. 发明申请

US20160070824A1 METHOD FOR GENERATING DESIGN SCHEME OF KITCHEN 审中-公开
标题翻译：生产厨房设计方案的方法
公开(公告)号：US20160070824A1
公开(公告)日：2016-03-10
申请号：US14662178
申请日：2015-03-18
申请人： Jin YAO , Rujia LIU , Decai HE , Kun BAI , Hao LI , Bo WANG , Xingnan ZHANG , Xin FANG
发明人： Jin YAO , Rujia LIU , Decai HE , Kun BAI , Hao LI , Bo WANG , Xingnan ZHANG , Xin FANG
IPC分类号： G06F17/50 , G06T17/00
CPC分类号： G06F17/5004 , G06F2217/02 , G06F2217/04 , G06T17/00
摘要： The present invention discloses a method for generating a design scheme of a kitchen, characterized in that, the method includes: step 1) inputting combination data, 3D model data and the like of each series, type, size, material, modeling door and accessories and various cabinet body of each brand into a database of the brand in QEYJ software according to a QEYJ rule; step 2) transforming all kinds of cabinet designs and usage requirements of placement into computer description language and formulas of functions; step 3) determining s region to place cabinets, after a starting point, turning points, a finishing point and positions of a range hood and a sink are determined in a kitchen of a customer; for an island table and a bar table, determining a position by determining a starting point and a finishing point of placement; then, through the present invention, immediately calculating optimal design of placement for each series in a QEYJ system, and presenting it in a 2D interface. Since a data amount to be stored is relatively small in this method, the data may be easily transmitted to every computer mounted with QEYJ cabinet software over the world. Every upgraded cabinet series and every upgraded design fashion may be easily transmitted over the world.
摘要翻译：本发明公开了一种生成厨房设计方案的方法，其特征在于，该方法包括：步骤1）输入每个系列的组合数据，3D模型数据等，类型，尺寸，材料，建模门和配件各品牌的柜体根据QEYJ规则成为QEYJ软件中的品牌数据库; 步骤2）将各种柜体设计和使用要求转化为计算机描述语言和功能公式; 步骤3）在客户的厨房中确定起始点，转折点，终点和抽油烟机和水槽的位置之后确定区域放置橱柜; 通过确定放置的起点和终点来确定位置; 然后，通过本发明，立即计算QEYJ系统中每个系列的最佳布局设计，并将其呈现在2D界面中。由于在该方法中要存储的数据量相对较小，因此数据可以容易地传输到世界上安装有QEYJ机柜软件的每台计算机。每个升级柜系列和每一个升级的设计风格可能很容易传播到世界各地。

59. 发明申请

US20160048611A1 System, Method, Apparatus, and Computer Program Product for Generation of an Elevation Plan for a Computing System 审中-公开
标题翻译：用于生成计算系统高程计划的系统，方法，设备和计算机程序产品
公开(公告)号：US20160048611A1
公开(公告)日：2016-02-18
申请号：US14460677
申请日：2014-08-15
申请人： VCE Company, LLC
发明人： Timothy Allen Cox , Jeffery Jon Hayward , Brian Keefe
IPC分类号： G06F17/50
CPC分类号： G06F17/5004 , G06F17/50 , G06F17/5086 , G06F2217/02 , G06F2217/06
摘要： A system, method, apparatus, and computer program product for generating an elevation plan for a computing system are disclosed. A method may include accessing a build specification identifying components to be included in the computing system. The method may also include accessing a set of component placement rules defining rules for placing components within a rack. The method may further include generating an elevation plan defining a respective mount position for each of a subset of the components within one or more racks based on the set of component placement rules.
摘要翻译：公开了一种用于生成计算系统的升降计划的系统，方法，装置和计算机程序产品。方法可以包括访问构建规范，以识别要包括在计算系统中的组件。该方法还可以包括访问定义用于将组件放置在机架内的规则的组件放置规则集合。该方法可以进一步包括基于组件放置规则的集合来生成为一个或多个机架中的部件的子集中的每一个定义相应安装位置的升高平面。

60. 发明授权

US09250649B2 Displaying recommended placement of information handling systems based on impedance ranking 有权
标题翻译：显示基于阻抗排名的信息处理系统的推荐布局
公开(公告)号：US09250649B2
公开(公告)日：2016-02-02
申请号：US14041152
申请日：2013-09-30
申请人： Dell Products L.P.
发明人： Hasnain Shabbir , Ramsundar Govindarajan , Dinesh Kunnathur Ragupathi
IPC分类号： G06F17/00 , G06F1/16 , G06Q10/00 , G06F17/50
CPC分类号： G06F1/16 , G06F1/206 , G06F17/5086 , G06F17/509 , G06F2217/02 , G06F2217/80 , G06Q10/00 , Y02D10/16
摘要： In accordance with embodiments of the present disclosure, a system may comprise a plurality of slots each configured to receive a modular information handling system, a plurality of air movers each configured to cool at least one modular information handling system disposed in at least one of the plurality slots, and a chassis management controller communicatively coupled to the plurality of slots and the plurality of air movers and configured to display a recommended placement of modular information handling systems in the plurality of slots based on at least one of: identities of slots populated with modular information handling systems, an airflow ranking of the plurality of slots, an impedance ranking of information handling systems disposed in the slots, and a workload of each of the information handling systems disposed in the slots.
摘要翻译：根据本公开的实施例，系统可以包括多个槽，每个槽被配置为接收模块化信息处理系统，多个空气移动器，每个空气移动器被配置为冷却至少一个模块化信息处理系统，该至少一个模块化信息处理系统设置在至少一个多个时隙，以及通信地耦合到所述多个时隙的所述机箱管理控制器，以及所述多个空气移动器，并且被配置为基于以下至少一个来显示所述多个时隙中的模块化信息处理系统的推荐布置：填充有模块化信息处理系统，多个时隙中的气流分级，设置在时隙中的信息处理系统的阻抗等级以及设置在时隙中的每个信息处理系统的工作负载。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式