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51. 发明申请

US20130168772A1 SEMICONDUCTOR DEVICE FOR ELECTROSTATIC DISCHARGE PROTECTING CIRCUIT 审中-公开
标题翻译：用于静电放电保护电路的半导体器件
公开(公告)号：US20130168772A1
公开(公告)日：2013-07-04
申请号：US13338324
申请日：2011-12-28
申请人： Yung-Ju WEN
发明人： Yung-Ju WEN
IPC分类号： H01L27/092
CPC分类号： H01L27/0277
摘要： A semiconductor device for an electrostatic discharge (ESD) protecting circuit connected to a pad is provided. The semiconductor device includes a semiconductor substrate of a first conductivity type; a plurality of metal oxide semiconductor transistors (MOSFETs) formed in the semiconductor substrate, and an isolation structure of a second conductivity type formed in the semiconductor substrate. The MOFETS are arranged in parallel. Drain electrodes of the MOSFETs are electrically connected to the pad, gate electrodes and source electrodes of the MOSFETs are connected to a constant voltage, and the gate electrodes extend in a first direction. The isolation structure includes a bottom and at least two side walls, wherein the bottom is located under the MOSFETs and the two side walls are located at two sides of the MOSFETs, and the side walls extend in the first direction.
摘要翻译：提供了一种用于连接到焊盘的静电放电（ESD）保护电路的半导体器件。半导体器件包括第一导电类型的半导体衬底; 形成在半导体衬底中的多个金属氧化物半导体晶体管（MOSFET）和形成在半导体衬底中的第二导电类型的隔离结构。 MOFETS并行布置。 MOSFET的漏极电连接到焊盘，MOSFET的栅电极和源电极连接到恒定电压，并且栅电极沿第一方向延伸。隔离结构包括底部和至少两个侧壁，其中底部位于MOSFET下方，并且两个侧壁位于MOSFET的两侧，并且侧壁沿第一方向延伸。

52. 发明申请

US20130149870A1 SUBSTRATE CARRIER AND APPLICATIONS THEREOF 失效
标题翻译：基板载体及其应用
公开(公告)号：US20130149870A1
公开(公告)日：2013-06-13
申请号：US13323941
申请日：2011-12-13
申请人： Chun-Hsing Tung , Fei-Tzu Lin
发明人： Chun-Hsing Tung , Fei-Tzu Lin
IPC分类号： H01L21/31 , C23C16/04 , C23C16/44 , B05C13/00
CPC分类号： H01L21/28506 , C23C14/3407 , C23C14/50 , C23C14/505 , C23C16/458 , C23C16/4584 , H01L21/68764 , H01L21/68771 , H01L21/68785
摘要： A substrate carrier for performing a deposition process comprises a supporting element and a cover element. The supporting element having a through hole is used to carry a substrate. The cover element is removably engaged with the supporting element, so as to secure the substrate therebetween and expose a deposition surface of the substrate from the through hole.
摘要翻译：用于执行沉积工艺的衬底载体包括支撑元件和覆盖元件。具有通孔的支撑元件用于承载基板。盖元件可移除地与支撑元件接合，以便将基板固定在其间，并使基板的沉积表面从通孔露出。

53. 发明申请

US20130130460A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130130460A1
公开(公告)日：2013-05-23
申请号：US13298395
申请日：2011-11-17
申请人： Duan-Quan LIAO , Shih-Chieh Hsu , Yi-Kun Chen , Ching-Hwa Tey
发明人： Duan-Quan LIAO , Shih-Chieh Hsu , Yi-Kun Chen , Ching-Hwa Tey
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L21/823842 , H01L29/66545
摘要： A method for fabricating a semiconductor device comprises steps as follows: A first dummy gate having a first high-k gate insulator layer, a first composite sacrificial layer, and a first dummy gate electrode sequentially stacked on a substrate is firstly provided. The first dummy gate electrode is subsequently removed to expose the first composite sacrificial layer. The first composite sacrificial layer is then removed. Thereafter, a first work function layer is formed on the first high-k gate insulator layer, and a first metal gate electrode is formed on the first work function layer.
摘要翻译：一种制造半导体器件的方法包括以下步骤：首先提供具有第一高k栅极绝缘体层，第一复合牺牲层和顺序堆叠在基板上的第一伪栅电极的第一伪栅极。随后去除第一伪栅电极以暴露第一复合牺牲层。然后去除第一复合牺牲层。此后，在第一高k栅极绝缘体层上形成第一功函数层，在第一功函数层上形成第一金属栅电极。

54. 发明授权

US08441134B2 Chip stacking structure 有权
标题翻译：芯片堆叠结构
公开(公告)号：US08441134B2
公开(公告)日：2013-05-14
申请号：US13228549
申请日：2011-09-09
申请人： Chien-Li Kuo , Yung-Chang Lin , Ming-Tse Lin
发明人： Chien-Li Kuo , Yung-Chang Lin , Ming-Tse Lin
IPC分类号： H01L23/52 , H01L23/48 , H01L27/146 , H01L27/148
CPC分类号： H01L23/12 , H01L21/563 , H01L25/0657 , H01L2225/06513 , H01L2225/06565 , H01L2924/0002 , H01L2924/00
摘要： A chip stacking structure includes a first chip and a second chip. The first chip includes a surface having a first group of pads formed thereon, and the second chip includes a surface having a second group of pads formed thereon. The second group of pads is bonded onto the first group of pads to define a plurality of capillary passages extending in a same direction. The chip stacking structure further includes an underfill filling up interspaces between the first chip and the second chip. The chip stacking structure is capable of avoiding chip deformation and cracking during a bonding process.
摘要翻译：芯片堆叠结构包括第一芯片和第二芯片。第一芯片包括具有形成在其上的第一组焊盘的表面，并且第二芯片包括具有形成在其上的第二组焊盘的表面。第二组垫被粘合到第一组垫上以限定沿相同方向延伸的多个毛细通道。芯片堆叠结构还包括在第一芯片和第二芯片之间的底部填充填充间隙。芯片堆叠结构能够在焊接过程中避免芯片变形和开裂。

55. 发明申请

US20130113075A1 METAL-INSULATOR-METAL CAPACITOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：金属绝缘体 - 金属电容器结构及其制造方法
公开(公告)号：US20130113075A1
公开(公告)日：2013-05-09
申请号：US13292156
申请日：2011-11-09
申请人： Ji FENG , Duan-Quan Liao , Hai-Long Gu , Ying-Tu Chen
发明人： Ji FENG , Duan-Quan Liao , Hai-Long Gu , Ying-Tu Chen
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L28/60 , H01L21/283 , H01L21/3213 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor structure includes a first dielectric layer, a first damascene electrode layer, an insulating barrier layer, a second dielectric layer and a second damascene electrode layer. The first damascene electrode layer is formed in the first dielectric layer. The insulating barrier layer covers the first dielectric layer and the first damascene electrode layer, and is a single layer structure. The second dielectric layer is formed on the insulating barrier layer. The second damascene electrode layer is formed in the second dielectric layer and is contacted with the insulating barrier layer. The MIM capacitor structure can includes a dual damascene structure formed in the second dielectric layer and the insulating barrier layer and electrically connected to the first damascene electrode layer. A method for manufacturing the MIM capacitor structure is also provided.
摘要翻译：金属绝缘体金属（MIM）电容器结构包括第一电介质层，第一镶嵌电极层，绝缘阻挡层，第二电介质层和第二镶嵌电极层。第一镶嵌电极层形成在第一介电层中。绝缘阻挡层覆盖第一电介质层和第一镶嵌电极层，并且是单层结构。第二电介质层形成在绝缘阻挡层上。第二镶嵌电极层形成在第二电介质层中并与绝缘阻挡层接触。 MIM电容器结构可以包括形成在第二电介质层和绝缘阻挡层中并电连接到第一镶嵌电极层的双镶嵌结构。还提供了一种用于制造MIM电容器结构的方法。

56. 发明申请

US20130109163A1 FABRICATING METHOD OF SEMICONDUCTOR ELEMENT 有权
标题翻译：半导体元件的制作方法
公开(公告)号：US20130109163A1
公开(公告)日：2013-05-02
申请号：US13283690
申请日：2011-10-28
申请人： Ming-Te WEI , Po-Chao Tsao , Ming-Tsung Chen
发明人： Ming-Te WEI , Po-Chao Tsao , Ming-Tsung Chen
IPC分类号： H01L21/28
CPC分类号： H01L21/28 , H01L21/823437 , H01L27/0207
摘要： The present invention relates to a fabricating method of a semiconductor element. First, a substrate is provided and a first layout structure having a first width is formed on the substrate. Then, an etching mask is formed to cover the first layout structure, and the etching mask exposes a portion of the first layout structure. After that, the first layout structure is etched with the etching mask to form a second layout structure having a second width. The second width is less than the first width. This fabricating method is capable of finishing the fabrication of gate structures in two different directions. Accordingly, the layout flexibility is improved.
摘要翻译：半导体元件的制造方法技术领域本发明涉及半导体元件的制造方法。首先，提供基板，并且在基板上形成具有第一宽度的第一布局结构。然后，形成蚀刻掩模以覆盖第一布局结构，并且蚀刻掩模暴露第一布局结构的一部分。之后，用蚀刻掩模蚀刻第一布局结构以形成具有第二宽度的第二布局结构。第二宽度小于第一宽度。该制造方法能够完成两个不同方向的栅极结构的制造。因此，布局灵活性得到改善。

57. 发明授权

US08434030B1 Integrated circuit design and fabrication method by way of detecting and scoring hotspots 有权
标题翻译：集成电路设计和制作方法，通过检测和评分热点
公开(公告)号：US08434030B1
公开(公告)日：2013-04-30
申请号：US13343774
申请日：2012-01-05
申请人： Hsin-Ming Hou , Ji-Fu Kung
发明人： Hsin-Ming Hou , Ji-Fu Kung
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： An integrated circuit design and fabrication method includes the following steps. Firstly, an integrated circuit design layout is provided. Then, a first hotspot group and a second hotpot group are searched from the integrated circuit design layout. Then, a hotspot score is acquired according to the first hotspot group, the second hotpot group and a product functionality. If the hotspot score is higher than a criterion, the integrated circuit design layout is corrected according to the first hotspot group and the second hotpot group.
摘要翻译：集成电路设计和制造方法包括以下步骤。首先，提供集成电路设计布局。然后，从集成电路设计布局搜索第一热点组和第二火锅组。然后，根据第一热点组，第二火锅组和产品功能获取热点分数。如果热点分数高于标准，则根据第一热点组和第二热点组来校正集成电路设计布局。

58. 发明申请

US20130089957A1 FIN FIELD-EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING PROCESS THEREOF 有权
标题翻译： FIN场效应晶体管结构及其制造工艺
公开(公告)号：US20130089957A1
公开(公告)日：2013-04-11
申请号：US13693009
申请日：2012-12-03
申请人： UNITED MICROELECTRONICS CORPORATION
发明人： Teng-Chun TSAI , Chun-Yuan WU , Chin-Fu LIN , Chih-Chien LIU , Chin-Cheng CHIEN
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L29/66545 , H01L29/66795 , H01L29/7833
摘要： A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced.
摘要翻译：鳍状场效应晶体管结构包括衬底，鳍状沟道和高k金属栅极。高k金属栅极形成在基板和鳍状通道上。制造鳍式场效应晶体管结构的工艺包括以下步骤。首先，在基板和散热片通道的表面上形成多晶硅伪栅极结构。通过使用多晶硅伪栅极结构作为掩模，在鳍式沟道中形成源/漏区。在去除多晶硅伪栅极结构之后，依次形成高k电介质层和金属栅极层。然后，在具有金属栅极层的基板上进行平坦化处理，直到第一介电层露出为止，从而产生高k金属栅极。

59. 发明申请

US20130062780A1 CHIP STACKING STRUCTURE 有权
标题翻译：芯片堆叠结构
公开(公告)号：US20130062780A1
公开(公告)日：2013-03-14
申请号：US13228549
申请日：2011-09-09
申请人： Chien-Li KUO , Yung-Chang Lin , Ming-Tse Lin
发明人： Chien-Li KUO , Yung-Chang Lin , Ming-Tse Lin
IPC分类号： H01L23/12
CPC分类号： H01L23/12 , H01L21/563 , H01L25/0657 , H01L2225/06513 , H01L2225/06565 , H01L2924/0002 , H01L2924/00
摘要： A chip stacking structure includes a first chip and a second chip. The first chip includes a surface having a first group of pads formed thereon, and the second chip includes a surface having a second group of pads formed thereon. The second group of pads is bonded onto the first group of pads to define a plurality of capillary passages extending in a same direction. The chip stacking structure further includes an underfill filling up interspaces between the first chip and the second chip. The chip stacking structure is capable of avoiding chip deformation and cracking during a bonding process.
摘要翻译：芯片堆叠结构包括第一芯片和第二芯片。第一芯片包括具有形成在其上的第一组焊盘的表面，并且第二芯片包括具有形成在其上的第二组焊盘的表面。第二组垫被粘合到第一组垫上以限定沿相同方向延伸的多个毛细通道。芯片堆叠结构还包括在第一芯片和第二芯片之间的底部填充填充间隙。芯片堆叠结构能够在焊接过程中避免芯片变形和开裂。

60. 发明申请

US20130038336A1 Probe Calibration Device and Calibration Method 审中-公开
标题翻译：探头校准装置和校准方法
公开(公告)号：US20130038336A1
公开(公告)日：2013-02-14
申请号：US13208440
申请日：2011-08-12
申请人： Jie-Wei SUN , Chao-Hsien Wu , Chia-Chun Sun , Yun-San Huang , Chien-Li Kuo
发明人： Jie-Wei SUN , Chao-Hsien Wu , Chia-Chun Sun , Yun-San Huang , Chien-Li Kuo
IPC分类号： G01R35/00
CPC分类号： G01R35/00 , G01R1/073 , G01R35/005
摘要： A calibration device applied for a test apparatus with at least a first probe and a second probe, the calibration device comprising: a first testing region and a second testing region, the first testing region and the second testing region divides into n×n sensing units respectively, the first testing region for generating n×n average electricity corresponding to a contact degree of the first probe contacted with the calibration device, and the second testing region for generating another n×n average electricity corresponding to a contact degree of the second probe contacted with the calibration device, and the pitch is the distance between the center of the first testing region to the center of the second testing region that is the same as that of the center of the first probe to the center of the second probe.
摘要翻译：一种用于具有至少第一探针和第二探针的测试装置的校准装置，所述校准装置包括：第一测试区域和第二测试区域，所述第一测试区域和所述第二测试区域分为n×n个感测单元分别产生与接收校准装置的第一探针的接触度相对应的n×n平均电力的第一测试区域和用于产生与第二探针的接触度相对应的另外n×n平均电流的第二测试区域与校准装置接触，间距是第一测试区域的中心与第二测试区域的中心之间的距离，其与第一探针的中心相对于第二探测器的中心的距离相同。

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