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51. 发明申请

US20110018565A1 DIELECTRIC BREAKDOWN LIFETIME ENHANCEMENT USING ALTERNATING CURRENT (AC) CAPACITANCE 有权
标题翻译：使用替代电流（AC）电容进行电介质断路寿命延长
公开(公告)号：US20110018565A1
公开(公告)日：2011-01-27
申请号：US12506837
申请日：2009-07-21
申请人： Kok Yong Yiang , Rick Francis , Amit P. Marathe , Van-Hung Pham
发明人： Kok Yong Yiang , Rick Francis , Amit P. Marathe , Van-Hung Pham
IPC分类号： G01R31/02 , G01R31/26 , G01R31/20
CPC分类号： G01R31/2623
摘要： A time-to-breakdown for a dielectric layer in a semiconductor device is determined based upon a sudden change in capacitance. An alternating voltage, greater in magnitude than an operating voltage of the device, is applied to the semiconductor device, capacitance is measured across the dielectric layer during the application of the voltage until a sudden change in capacitance occurs, thereby indicating a breakdown in the dielectric layer, and the breakdown time is scaled to the operating voltage.
摘要翻译：基于电容的突然变化来确定半导体器件中的电介质层的击穿时间。在半导体器件上施加大于该器件的工作电压的大小的交变电压，在施加电压期间在电介质层两端测量电容，直到发生电容的突然变化，从而表明电介质中的击穿层，并且击穿时间被缩放到工作电压。

52. 发明授权

US07871873B2 Method of forming fin structures using a sacrificial etch stop layer on bulk semiconductor material 有权
标题翻译：在体半导体材料上使用牺牲蚀刻停止层形成翅片结构的方法
公开(公告)号：US07871873B2
公开(公告)日：2011-01-18
申请号：US12413174
申请日：2009-03-27
申请人： Witold Maszara , Ming-Ren Lin , Jin Cho , Zoran Krivokapic
发明人： Witold Maszara , Ming-Ren Lin , Jin Cho , Zoran Krivokapic
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336
CPC分类号： H01L29/66795
摘要： A method of manufacturing semiconductor fins for a semiconductor device may begin by providing a bulk semiconductor substrate. The method continues by growing a layer of first epitaxial semiconductor material on the bulk semiconductor substrate, and by growing a layer of second epitaxial semiconductor material on the layer of first epitaxial semiconductor material. The method then creates a fin pattern mask on the layer of second epitaxial semiconductor material. The fin pattern mask has features corresponding to a plurality of fins. Next, the method anisotropically etches the layer of second epitaxial semiconductor material, using the fin pattern mask as an etch mask, and using the layer of first epitaxial semiconductor material as an etch stop layer. This etching step results in a plurality of fins formed from the layer of second epitaxial semiconductor material.
摘要翻译：制造用于半导体器件的半导体鳍片的方法可以通过提供体半导体衬底开始。该方法通过在体半导体衬底上生长第一外延半导体材料层并通过在第一外延半导体材料层上生长第二外延半导体材料层来继续。该方法然后在第二外延半导体材料层上产生鳍状图案掩模。翅片图形掩模具有对应于多个翅片的特征。接下来，使用鳍图案掩模作为蚀刻掩模，并且使用第一外延半导体材料层作为蚀刻停止层，该方法各向异性地蚀刻第二外延半导体材料的层。该蚀刻步骤导致由第二外延半导体材料层形成的多个鳍片。

53. 发明授权

US07601641B1 Two step optical planarizing layer etch 有权
标题翻译：两步光学平坦化层蚀刻
公开(公告)号：US07601641B1
公开(公告)日：2009-10-13
申请号：US12059888
申请日：2008-03-31
申请人： Erik Geiss , Christopher Prindle , Sven Beyer
发明人： Erik Geiss , Christopher Prindle , Sven Beyer
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/0271
摘要： Methods are provided for etching during fabrication of a semiconductor device. The method includes initially etching to partially remove a portion of one or more lithographic-aiding layers overlying an oxide layer while etching a first portion of the oxide layer in accordance with a mask formed by the one or more lithographic-aiding layers, and thereafter additionally etching to remove remaining portions of the one or more lithographic-aiding layers while etching a remaining portion of the oxide layer.
摘要翻译：在制造半导体器件期间提供蚀刻方法。该方法包括首先蚀刻以根据由一个或多个平版印刷助剂层形成的掩模蚀刻氧化物层的第一部分而部分地去除覆盖在氧化物层上的一个或多个平版印刷辅助层的一部分，此后另外蚀刻以除去一个或多个平版印刷辅助层的剩余部分，同时蚀刻氧化物层的剩余部分。

54. 发明申请

US20180331213A1 VERTICAL FET WITH SELF-ALIGNED SOURCE/DRAIN REGIONS AND GATE LENGTH BASED ON CHANNEL EPITAXIAL GROWTH PROCESS 审中-公开
公开(公告)号：US20180331213A1
公开(公告)日：2018-11-15
申请号：US15593651
申请日：2017-05-12
申请人： GLOBAL FOUNDRIES INC.
发明人： Steven Bentley , Puneet Harischandra Suvarna , Julien Frougier , Bartlomiej Jan Pawlak
IPC分类号： H01L29/78 , H01L29/66 , H01L29/10
CPC分类号： H01L29/7827 , H01L29/1033 , H01L29/66666 , H01L29/66795 , H01L29/785
摘要： A fin extends from, and is perpendicular to, a planar surface of a substrate. A self-aligned bottom source/drain conductor is on the substrate adjacent the fin, a bottom insulator spacer is on the bottom source/drain conductor adjacent the fin, and a gate insulator is on a channel portion of the fin. A gate conductor is on the gate insulator, a self-aligned top source/drain conductor contacts the channel portion of the fin distal to the bottom insulator spacer, a top gate length limit insulator is positioned where the channel portion meets the top source/drain conductor, and a bottom gate length limit insulator is positioned where the channel portion meets the bottom insulator spacer. The gate length of the gate conductor is defined by a distance between the gate length limit insulators.

55. 发明授权

US09704600B1 Method, apparatus, and system for global healing of write-limited die through bias temperature instability 有权
公开(公告)号：US09704600B1
公开(公告)日：2017-07-11
申请号：US15047271
申请日：2016-02-18
申请人： GLOBALFOUNDRIES INC.
发明人： Akhilesh Gautam , Randy W. Mann , William McMahon , Yoann Mamy Randriamihaja , Yuncheng Song
IPC分类号： G11C11/00 , G11C29/52 , G11C11/412 , G11C11/419
CPC分类号： G11C29/52 , G11C7/04 , G11C11/412 , G11C11/419
摘要： We disclose methods, apparatus, and systems for improving semiconductor device writeability through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS through the array VCS driver.

56. 发明授权

US09646885B1 Method to prevent lateral epitaxial growth in semiconductor devices by performing plasma nitridation process on Fin ends 有权
公开(公告)号：US09646885B1
公开(公告)日：2017-05-09
申请号：US15224091
申请日：2016-07-29
申请人： International Business Machines Corporation , GlobalFoundries,Inc.
发明人： Balasubramanian Pranatharthiharan , Hui Zang
IPC分类号： H01L21/8234 , H01L21/033 , H01L21/762 , H01L29/06 , H01L29/66 , H01L29/78 , H01L21/3105 , H01L27/11 , H01L21/8238 , H01L21/84 , H01L21/02
CPC分类号： H01L27/1104 , H01L21/02164 , H01L21/0217 , H01L21/02247 , H01L21/0332 , H01L21/0335 , H01L21/0337 , H01L21/26506 , H01L21/3086 , H01L21/31053 , H01L21/31111 , H01L21/76 , H01L21/762 , H01L21/76224 , H01L21/823418 , H01L21/823431 , H01L21/823814 , H01L21/823821 , H01L21/845 , H01L27/0886 , H01L27/1116 , H01L29/0642 , H01L29/0649 , H01L29/0653 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： A method for preventing epitaxial growth in a semiconductor device is described. The method cuts the fins of a FinFET structure to form a set of exposed fin ends. A plasma nitridation process is performed to the set of exposed fin ends. The plasma nitridation process forms a set of nitride layer covered fin ends. Dielectric material is deposited over the FinFET structure. The dielectric is etched to reveal sidewalls of the fins and the set of nitride layer covered fin ends. The nitride layer prevents epitaxial growth at the set of spacer covered fin ends.

57. 发明授权

US09608086B2 Metal gate structure and method of formation 有权
公开(公告)号：US09608086B2
公开(公告)日：2017-03-28
申请号：US14282257
申请日：2014-05-20
申请人： GLOBALFOUNDRIES Inc.
发明人： Andy Chih-Hung Wei , Dae G. Yang , Mariappan Hariharaputhiran , Jing Wan
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78
CPC分类号： H01L29/785 , H01L21/28247 , H01L27/1104 , H01L29/4238 , H01L29/49 , H01L29/4958 , H01L29/4966 , H01L29/66 , H01L29/66545 , H01L29/66795
摘要： Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut process is performed after the metal gate is formed. This allows for a reduced margin between the end of the gate and an adjacent fin. It enables a thinner sacrificial layer on top of the dummy gate, since the gate cut step is deferred. The thinner sacrificial layer improves device quality by reducing the adverse effect of shadowing during implantation. Furthermore, in this process flow, the work function metal layer is terminated along the semiconductor substrate by a capping layer, which reduces undesirable shifts in threshold voltage that occurred in prior methods and structures.

58. 发明授权

US09589833B1 Preventing leakage inside air-gap spacer during contact formation 有权
标题翻译：在接触形成期间防止气隙间隔件内的泄漏
公开(公告)号：US09589833B1
公开(公告)日：2017-03-07
申请号：US14850093
申请日：2015-09-10
申请人： International Business Machines Corporation , GLOBALFOUNDRIES Inc.
发明人： Kangguo Cheng , Ruilong Xie , Tenko Yamashita
IPC分类号： H01L29/423 , H01L21/768 , H01L29/06 , H01L23/535 , H01L29/78 , H01L29/66
CPC分类号： H01L29/4991 , H01L21/76805 , H01L21/7682 , H01L21/76831 , H01L21/76843 , H01L21/76895 , H01L21/76897 , H01L29/66568
摘要： Techniques for preventing leakage of contact material into air-gap spacers during contact formation. For example, a method comprises forming a contact trench on a semiconductor structure over an air-gap spacer and depositing a liner in the contact trench. The liner deposition material fills a portion of the air-gap spacer pinching off the contact trench to the air-gap spacer.
摘要翻译：在接触形成期间防止接触材料泄漏到气隙间隔物中的技术。例如，一种方法包括在气隙间隔物上的半导体结构上形成接触沟槽，并在接触沟槽中沉积衬垫。衬垫沉积材料填充气隙间隔件的一部分，将接触沟槽夹紧到气隙间隔件。

59. 发明授权

US09505611B1 Integration of electromechanical and CMOS devices in front-end-of-line using replacement metal gate process flow 有权
标题翻译：使用替代金属浇口工艺流程将机电和CMOS器件集成在前端
公开(公告)号：US09505611B1
公开(公告)日：2016-11-29
申请号：US14814083
申请日：2015-07-30
申请人： GLOBALFOUNDRIES Inc.
发明人： Fei Liu , Qiqing C. Ouyang , Keith Kwong Hon Wong
IPC分类号： B81C1/00 , H01L29/66 , B81B7/00
CPC分类号： B81C1/00246 , B81B7/008 , B81B2203/0118 , B81B2207/015 , B81B2207/07 , B81C2201/0132 , B81C2201/056 , B81C2203/0714 , H01L27/0617 , H01L29/66545
摘要： Semiconductor devices and methods are provided for integrally forming electromechanical devices (e.g. MEMS or NEMS devices) with CMOS devices in a FEOL (front-end-of-line) structure as part of a replacement metal gate process flow. For example, a method includes forming an electromechanical device in a first device region of a substrate and forming a transistor device in a second device region of the substrate. The electromechanical device includes a sacrificial anchor structure and a sacrificial cantilever structure formed of a sacrificial material. The transistor device includes a sacrificial gate electrode structure formed of the sacrificial material. A replacement metal gate process is performed to replace the sacrificial gate electrode structure of the transistor device with a metallic gate electrode, and to replace the sacrificial anchor structure and the sacrificial cantilever structure with a metallic anchor structure and a metallic cantilever structure. A release process is performed to release the metallic cantilever structure.
摘要翻译：提供半导体器件和方法，用于在作为替代金属栅极工艺流程的一部分的FEOL（前端线）结构中与CMOS器件一体地形成机电装置（例如MEMS或NEMS器件）。例如，一种方法包括在衬底的第一器件区域中形成机电器件，并在衬底的第二器件区域中形成晶体管器件。机电装置包括牺牲锚结构和由牺牲材料形成的牺牲悬臂结构。晶体管器件包括由牺牲材料形成的牺牲栅电极结构。执行替换金属栅极处理以用金属栅极电极代替晶体管器件的牺牲栅电极结构，并用金属锚结构和金属悬臂结构代替牺牲锚结构和牺牲悬臂结构。执行释放过程以释放金属悬臂结构。

60. 发明授权

US09263344B2 Low threshold voltage CMOS device 有权
标题翻译：低阈值CMOS器件
公开(公告)号：US09263344B2
公开(公告)日：2016-02-16
申请号：US14564603
申请日：2014-12-09
申请人： International Business Machines Corporation , GLOBAL FOUNDRIES Inc
发明人： Takashi Ando , Changhwan Choi , Kisik Choi , Vijay Narayanan
IPC分类号： H01L21/8238 , H01L21/28 , H01L29/49 , H01L29/51 , H01L29/66 , H01L21/02 , H01L29/161
CPC分类号： H01L21/823842 , H01L21/02178 , H01L21/02192 , H01L21/28079 , H01L21/28088 , H01L21/28229 , H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/161 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a PMOS region. Alternatively, after a dummy gate is removed in the NMOS and PMOS regions to leave openings in the NMOS and PMOS regions, lanthanum oxide may be deposited in the NMOS opening or aluminum oxide deposited in the PMOS opening. Thereafter, first work function metals are deposited in the NMOS opening and second work function metals are applied in the PMOS openings. A suitable gate electrode material may then fill the remainder of the NMOS and PMOS openings.
摘要翻译：其中施加高k电介质的替代金属栅极工艺。高k电介质可以在NMOS区域中掺杂镧或在PMOS区域中掺杂铝。或者，在NMOS和PMOS区域中去除伪栅极以在NMOS和PMOS区域中留下开口之后，可以在沉积在PMOS开口中的NMOS开口或氧化铝中沉积氧化镧。此后，第一功函数金属沉积在NMOS开口中，第二功函数金属被施加在PMOS开口中。合适的栅极材料可以填充NMOS和PMOS开口的其余部分。

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