专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

US20130210188A1 Method and Apparatus for Reducing Stripe Patterns 有权
标题翻译：减少条纹图案的方法和装置
公开(公告)号：US20130210188A1
公开(公告)日：2013-08-15
申请号：US13371303
申请日：2012-02-10
申请人： Chung Chien Wang , Yeur-Luen Tu , Cheng-Ta Wu , Chia-Shiung Tsai
发明人： Chung Chien Wang , Yeur-Luen Tu , Cheng-Ta Wu , Chia-Shiung Tsai
IPC分类号： H01L21/268 , B23K26/02
CPC分类号： H01L21/268 , G01B11/14 , H01L27/1464 , H01L27/14643 , H01L27/14689
摘要： A method for reducing stripe patterns comprising receiving scattered light signals from a backside surface of a laser annealed backside illuminated image sensor wafer, generating a backside surface image based upon the scattered light signals, determining a distance between an edge of a sensor array of the laser anneal backside illuminated image sensor wafer and an adjacent boundary of a laser beam and re-calibrating the laser beam if the distance is less than a predetermined value.
摘要翻译：一种用于减少条纹图案的方法，包括从激光退火背面照射图像传感器晶片的背面接收散射光信号，基于散射光信号产生背面图像，确定激光器的传感器阵列的边缘之间的距离退火背面照射的图像传感器晶片和激光束的相邻边界，并且如果距离小于预定值则重新校准激光束。

52. 发明申请

US20130113061A1 IMAGE SENSOR TRENCH ISOLATION WITH CONFORMAL DOPING 有权
公开(公告)号：US20130113061A1
公开(公告)日：2013-05-09
申请号：US13290733
申请日：2011-11-07
申请人： Chih-Yu Lai , Yeur-Luen Tu , Chih-Hui Huang , Cheng-Ta Wu , Chia-Shiung Tsai , Luan C. Tran
发明人： Chih-Yu Lai , Yeur-Luen Tu , Chih-Hui Huang , Cheng-Ta Wu , Chia-Shiung Tsai , Luan C. Tran
IPC分类号： H01L27/146 , H01L31/18 , H01L31/0232
CPC分类号： H01L27/1463 , H01L21/02129 , H01L21/223 , H01L21/2255 , H01L21/76224 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/1464 , H01L27/14685 , H01L31/09
摘要： Provided is a semiconductor image sensor device. The image sensor device includes a substrate. The image sensor device includes a first pixel and a second pixel disposed in the substrate. The first and second pixels are neighboring pixels. The image sensor device includes an isolation structure disposed in the substrate and between the first and second pixels. The image sensor device includes a doped isolation device disposed in the substrate and between the first and second pixels. The doped isolation device surrounds the isolation structure in a conformal manner.

53. 发明申请

US20120258564A1 METHOD TO AVOID FIXED PATTERN NOISE WITHIN BACKSIDE ILLUMINATED (BSI) COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) SENSOR ARRAY 有权
标题翻译：在背光照明（BSI）补充金属氧化物半导体（CMOS）传感器阵列中避免固定图案噪声的方法
公开(公告)号：US20120258564A1
公开(公告)日：2012-10-11
申请号：US13079995
申请日：2011-04-05
申请人： Chung Chien Wang , Yeur-Luen Tu , Chia-Shiung Tsai
发明人： Chung Chien Wang , Yeur-Luen Tu , Chia-Shiung Tsai
IPC分类号： H01L31/18 , H01L21/306 , H01L21/00 , H01L21/304
CPC分类号： H01L27/1464 , H01L27/14687 , H01L27/14698 , Y10T29/41
摘要： The present disclosure provides one embodiment of a method. The method includes providing a semiconductor substrate having a front side and a backside, wherein the front side of the semiconductor substrate includes a plurality of backside illuminated imaging sensors; bonding a carrier substrate to the semiconductor substrate from the front side; thinning the semiconductor substrate from the backside; performing an ion implantation to the semiconductor substrate from the backside; performing a laser annealing process to the semiconductor substrate from the backside; and thereafter, performing a polishing process to the semiconductor substrate from the backside.
摘要翻译：本公开提供了一种方法的实施例。该方法包括提供具有正面和背面的半导体衬底，其中半导体衬底的前侧包括多个背面照明成像传感器; 从前侧将载体衬底接合到半导体衬底; 从背面稀释半导体衬底; 从背面对半导体衬底进行离子注入; 从背面对半导体衬底进行激光退火处理; 然后从背面对半导体基板进行研磨处理。

54. 发明申请

US20120091549A1 FORMATION OF EMBEDDED MICRO-LENS 有权
标题翻译：嵌入式微透镜的形成
公开(公告)号：US20120091549A1
公开(公告)日：2012-04-19
申请号：US12903871
申请日：2010-10-13
申请人： Shih Pei Chou , Shih-Chang Liu , Yeur-Luen Tu , Chia-Shiung Tsai
发明人： Shih Pei Chou , Shih-Chang Liu , Yeur-Luen Tu , Chia-Shiung Tsai
IPC分类号： H01L31/0232 , H01L31/18
CPC分类号： H01L27/14627 , H01L27/14621 , H01L27/14685
摘要： Provided is an image sensor device. The image sensor device includes a pixel formed in a substrate. The image sensor device includes a first micro-lens embedded in a transparent layer over the substrate. The first micro-lens has a first upper surface that has an angular tip. The image sensor device includes a color filter that is located over the transparent layer. The image sensor device includes a second micro-lens that is formed over the color filter. The second micro-lens has a second upper surface that has an approximately rounded profile. The pixel, the first micro-lens, the color filter, and the second micro-lens are all at least partially aligned with one another in a vertical direction.
摘要翻译：提供了一种图像传感器装置。图像传感器装置包括形成在基板中的像素。图像传感器装置包括嵌入在基板上的透明层中的第一微透镜。第一微透镜具有具有角尖的第一上表面。图像传感器装置包括位于透明层上方的滤色器。图像传感器装置包括形成在滤色器上的第二微透镜。第二微透镜具有第二上表面，其具有近似圆形的轮廓。像素，第一微透镜，滤色器和第二微透镜在垂直方向上至少部分地彼此对准。

55. 发明申请

US20120034730A1 Backside Illuminated Sensor Processing 有权
标题翻译：背面照明传感器处理
公开(公告)号：US20120034730A1
公开(公告)日：2012-02-09
申请号：US13275935
申请日：2011-10-18
申请人： Yeur-Luen Tu , Chia-Shiung Tsai , Ching-Chun Wang , Ren-Jie Lin , Shou-Gwo Wuu
发明人： Yeur-Luen Tu , Chia-Shiung Tsai , Ching-Chun Wang , Ren-Jie Lin , Shou-Gwo Wuu
IPC分类号： H01L31/0232
CPC分类号： H01L27/14609 , H01L27/14621 , H01L27/14627 , H01L27/1463 , H01L27/1464 , H01L27/14643
摘要： The present disclosure provides methods and apparatus for reducing dark current in a backside illuminated semiconductor device. In one embodiment, a method of fabricating a semiconductor device includes providing a substrate having a frontside surface and a backside surface, and forming a plurality of sensor elements in the substrate, each of the plurality of sensor elements configured to receive light directed towards the backside surface. The method further includes forming a dielectric layer on the backside surface of the substrate, wherein the dielectric layer is formed to have a compressive stress to induce a tensile stress in the substrate. A backside illuminated semiconductor device fabricated by such a method is also disclosed.
摘要翻译：本公开提供了用于减少背面照明半导体器件中的暗电流的方法和装置。在一个实施例中，制造半导体器件的方法包括提供具有前表面和背面的衬底，以及在衬底中形成多个传感器元件，所述多个传感器元件中的每一个被配置为接收朝向背面的光表面。该方法还包括在衬底的背面形成电介质层，其中介电层形成为具有压应力以在衬底中引起拉伸应力。还公开了通过这种方法制造的背面照明半导体器件。

56. 发明授权

US06362012B1 Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications 有权
标题翻译：用于RF和混合信号应用的螺旋导体内并联垂直电容器的结构
公开(公告)号：US06362012B1
公开(公告)日：2002-03-26
申请号：US09798651
申请日：2001-03-05
申请人： Min-Hwa Chi , Chia-Shiung Tsai , Yeur-Luen Tu
发明人： Min-Hwa Chi , Chia-Shiung Tsai , Yeur-Luen Tu
IPC分类号： H01L2100
CPC分类号： H01L23/5223 , H01L23/5227 , H01L27/08 , H01L28/10 , H01L28/91 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A new method and structure is provided for the simultaneous creation of inductive and capacitive components in a monolithic substrate. The invention provides a method and structure whereby a vertical spiral inductor is created on the surface of a substrate. Multiple capacitors are created inside the coils of the vertical spiral conductor. A base layer of dielectric is deposited over the surface of a semiconductor substrate, contact plugs are provided in the base layer of dielectric. Multiple layers of dielectric are deposited over the surface of the base layer, layers of coils are created in the multiple layers of dielectric. Vias are provided in the layer of dielectric to interconnect overlying coils of the spiral inductor. An etch stop layer is deposited on the surface of the upper layer of dielectric. At least two openings are etched in the multiple layers of dielectric, these at least two openings are surrounded by the coils of the spiral inductor and align with the contact plugs provided in the base layers. Spacers are formed on the sidewalls of the openings, the bottom electrode layer, dielectric layer and top electrode layer of the at least two capacitors are deposited over the spacers. The openings are filled with a conductive material, the surface of the conductive material is polished down to the surface of the etch stop.
摘要翻译：提供了一种新的方法和结构，用于在单片基板中同时产生感应和电容部件。本发明提供一种方法和结构，由此在衬底的表面上产生垂直螺旋电感器。在垂直螺旋导体的线圈内部产生多个电容器。电介质的基底层沉积在半导体衬底的表面上，接触插塞设置在电介质的基底层中。在基层的表面上沉积多层电介质，在多层电介质中形成线圈层。在电介质层中提供通孔以互连螺旋电感器的上覆线圈。蚀刻停止层沉积在电介质上层的表面上。在多层电介质中蚀刻至少两个开口，这些至少两个开口被螺旋电感器的线圈包围，并与设置在基层中的接触插塞对准。隔板形成在开口的侧壁上，至少两个电容器的底部电极层，电介质层和顶部电极层沉积在间隔物上。开口填充有导电材料，导电材料的表面被抛光到蚀刻停止件的表面。

57. 发明授权

US08227850B2 Gated semiconductor device and method of fabricating same 有权
标题翻译：门式半导体器件及其制造方法
公开(公告)号：US08227850B2
公开(公告)日：2012-07-24
申请号：US12723381
申请日：2010-03-12
申请人： Shih-Chang Liu , Ming-Hui Shen , Chi-Hsin Lo , Chia-Shiung Tsai , Yi-Shin Chu
发明人： Shih-Chang Liu , Ming-Hui Shen , Chi-Hsin Lo , Chia-Shiung Tsai , Yi-Shin Chu
IPC分类号： H01L29/76
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/513 , H01L29/6656 , Y10S438/945
摘要： A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.
摘要翻译：一种用于制造门控半导体器件的方法，以及由执行该方法产生的器件。在一个优选实施例中，该方法包括形成用于在基板上形成的交替绝缘和导电材料的一层或多层上形成栅极的硬掩模。硬掩模优选包括三层; 下氮化物层，中间氧化物和上氮化物层。在该实施例中，中间氧化物层与硬掩模的其余部分形成，然后以侧向尺寸减小，优选使用DHF浸渍。形成在栅极结构上方的电介质层，包括硬掩模，然后被回蚀，自对准成为尺寸减小的氧化物层。此外，当存在两个导电（即栅极层）时，下层在至少一侧的横向尺寸上横向减小以产生底切。

58. 发明授权

US08114740B2 Profile of flash memory cells 有权
标题翻译：闪存单元简介
公开(公告)号：US08114740B2
公开(公告)日：2012-02-14
申请号：US13045955
申请日：2011-03-11
申请人： Shih-Chang Liu , Chu-Wei Chang , Chi-Hsin Lo , Chia-Shiung Tsai
发明人： Shih-Chang Liu , Chu-Wei Chang , Chi-Hsin Lo , Chia-Shiung Tsai
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L29/42328 , H01L29/7881
摘要： A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate.
摘要翻译：半导体结构包括半导体衬底; 半导体衬底上的隧道层; 邻近隧道层的源区; 和隧道层上的浮动栅极。浮动门包括具有上部和下部的第一边缘，其中下部从上部凹进。半导体结构还包括在浮置栅极上的阻挡层，其中阻挡层具有面向与浮动栅极的第一边缘相同方向的第一边缘。

59. 发明授权

US07928499B2 Profile of flash memory cells 有权
标题翻译：闪存单元简介
公开(公告)号：US07928499B2
公开(公告)日：2011-04-19
申请号：US11715229
申请日：2007-03-07
申请人： Shih-Chang Liu , Chu-Wei Chang , Chi-Hsin Lo , Chia-Shiung Tsai
发明人： Shih-Chang Liu , Chu-Wei Chang , Chi-Hsin Lo , Chia-Shiung Tsai
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L29/42328 , H01L29/7881
摘要： A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate.
摘要翻译：半导体结构包括半导体衬底; 半导体衬底上的隧道层; 邻近隧道层的源区; 和隧道层上的浮动栅极。浮动门包括具有上部和下部的第一边缘，其中下部从上部凹进。半导体结构还包括在浮置栅极上的阻挡层，其中阻挡层具有面向与浮动栅极的第一边缘相同方向的第一边缘。

60. 发明申请

US20100171167A1 Gated Semiconductor Device and Method of Fabricating Same 有权
标题翻译：门控半导体器件及其制造方法
公开(公告)号：US20100171167A1
公开(公告)日：2010-07-08
申请号：US12723381
申请日：2010-03-12
申请人： Shih-Chang Liu , Ming-Hui Shen , Chi-Hsin Lo , Chia-Shiung Tsai , Yi-Shin Chu
发明人： Shih-Chang Liu , Ming-Hui Shen , Chi-Hsin Lo , Chia-Shiung Tsai , Yi-Shin Chu
IPC分类号： H01L27/088 , H01L21/336 , H01L29/788
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/513 , H01L29/6656 , Y10S438/945
摘要： A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.
摘要翻译：一种用于制造门控半导体器件的方法，以及由执行该方法产生的器件。在一个优选实施例中，该方法包括形成用于在基板上形成的交替绝缘和导电材料的一层或多层上形成栅极的硬掩模。硬掩模优选包括三层; 下氮化物层，中间氧化物和上氮化物层。在该实施例中，中间氧化物层与硬掩模的其余部分形成，然后以侧向尺寸减小，优选使用DHF浸渍。形成在栅极结构上方的电介质层，包括硬掩模，然后被回蚀，自对准成为尺寸减小的氧化物层。此外，当存在两个导电（即栅极层）时，下层在至少一侧的横向尺寸上横向减小以产生底切。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式