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51. 发明申请

US20100249362A1 APPARATUS AND METHOD BOTH RELATING TO POLYMER SYNTHESIS 审中-公开
标题翻译：与聚合物合成相关的装置和方法
公开(公告)号：US20100249362A1
公开(公告)日：2010-09-30
申请号：US12741489
申请日：2008-11-04
申请人： Masayuki Kamikawa , Toshiaki Matsuo , Naruyasu Okamoto , Kenichiro Oka , Takashi Yatsugi , Yasuhiro Fujii , Tatsushi Kawamoto
发明人： Masayuki Kamikawa , Toshiaki Matsuo , Naruyasu Okamoto , Kenichiro Oka , Takashi Yatsugi , Yasuhiro Fujii , Tatsushi Kawamoto
IPC分类号： C07D319/10 , C08G63/08 , B01J8/02 , B01J19/00
CPC分类号： C07D319/12 , B01J19/1862 , B01J19/1887 , B01J19/20 , B01J2219/00009 , B01J2219/00083 , B01J2219/00779 , C08G63/08 , C08G63/78 , C08J11/16 , C08J2367/04 , Y02P20/584 , Y02W30/705
摘要： The present invention provides a method and apparatus for producing polylactic acid by depolymerizing lactic acid oligomers and subjecting the obtained lactide to ring-opening polymerization, through which lactide can be efficiently obtained. The present invention relates to a lactide production apparatus for continuously or intermittently producing lactide, comprising: a depolymerization device 11 for subjecting lactic acid oligomers to a depolymerization reaction; a catalyst regeneration device 27 for subjecting a residue in the depolymerization device to a depolymerization reaction in order to reduce the molecular weights of lactic acid oligomers contained in the residue; and a distillation column 29 for condensing lactide generated in a gas form as a result of the depolymerization reaction.
摘要翻译：本发明提供了一种通过解聚乳酸低聚物并使得到的丙交酯进行开环聚合制备聚乳酸的方法和装置，可以有效地获得丙交酯。本发明涉及一种用于连续或间断地生产丙交酯的丙交酯生产设备，包括：用于使乳酸低聚物进行解聚反应的解聚装置11; 用于使解聚装置中的残余物进行解聚反应以降低残留物中所含的乳酸低聚物的分子量的催化剂再生装置27; 以及用于冷凝由于解聚反应而以气体形式产生的丙交酯的蒸馏塔29。

52. 发明授权

US07577843B2 System and method for controlling contents by plurality of pieces of control information 失效
标题翻译：通过多条控制信息控制内容的系统和方法
公开(公告)号：US07577843B2
公开(公告)日：2009-08-18
申请号：US10862875
申请日：2004-06-08
申请人： Isao Echizen , Takao Arai , Hiroyuki Kimura , Takaaki Yamada , Yasuhiro Fujii
发明人： Isao Echizen , Takao Arai , Hiroyuki Kimura , Takaaki Yamada , Yasuhiro Fujii
IPC分类号： H04N7/167 , G06K9/00
CPC分类号： G06T1/0071 , G06T2201/0064 , H04N5/913 , H04N21/4334 , H04N21/4627 , H04N21/8355 , H04N21/8358 , H04N2005/91328 , H04N2005/91335
摘要： At least one kind of control signal concerning control of contents, added to specific locations inside contents data, is detected as first control information, and at the same time, at least one kind of control information concerning control of contents, embedded inside the contents data by a digital watermark, is detected as second control information. Consistency between the first control information as detected, and the second control information as detected is determined and on the basis of results of the determination, the control of the contents is executed. Thus, it is possible to reduce a possibility of the contents being improperly copied, thereby enabling the control with assurance of still higher safety.
摘要翻译：作为第一控制信息，检测到与内容数据内的特定位置相关的内容的控制中的至少一种控制信号，同时，嵌入在内容数据内的内容的控制的至少一种控制信息被检测为第二控制信息。确定检测到的第一控制信息和检测到的第二控制信息之间的一致性，并且基于确定的结果，执行内容的控制。因此，可以降低内容物的不正确复制的可能性，从而能够进一步确保安全性的控制。

53. 发明授权

US07499565B2 Method of watermarking for binary images 失效
标题翻译：二进制图像水印方法
公开(公告)号：US07499565B2
公开(公告)日：2009-03-03
申请号：US10841842
申请日：2004-05-10
申请人： Yasuhiro Fujii , Kazunori Nakano , Isao Echizen , Hiroshi Yoshiura
发明人： Yasuhiro Fujii , Kazunori Nakano , Isao Echizen , Hiroshi Yoshiura
IPC分类号： G06K9/00
CPC分类号： G06T1/0028 , G06T2201/0051 , G06T2201/0061 , G06T2201/0083
摘要： A technology of digital watermarking for binary images (including documents) is provided, which is capable of adjusting the amount of information to be embedded while avoiding the deterioration of image quality as far as possible. The watermark information is inserted by giving the standard for judgment of modification and the order of preference for modification according to the characteristic properties of the human visual sense for binary images and performing modification on pixels sequentially in the descending order of preference.
摘要翻译：提供了一种用于二进制图像（包括文档）的数字水印技术，其能够尽可能地避免图像质量的恶化来调整要嵌入的信息量。通过给出用于二进制图像的人类视觉特性的修改标准和修改偏好顺序来插入水印信息，并以优先级顺序依次对像素进行修改。

54. 发明授权

US06853022B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06853022B2
公开(公告)日：2005-02-08
申请号：US10352987
申请日：2003-01-29
申请人： Tsuyoshi Koga , Yoshiyuki Ishigaki , Motoi Ashida , Yukio Maki , Yasuhiro Fujii , Tomohiro Hosokawa , Takashi Terada , Makoto Dei , Yasuichi Masuda
发明人： Tsuyoshi Koga , Yoshiyuki Ishigaki , Motoi Ashida , Yukio Maki , Yasuhiro Fujii , Tomohiro Hosokawa , Takashi Terada , Makoto Dei , Yasuichi Masuda
IPC分类号： H01L27/108 , G11C11/402 , G11C11/412 , H01L21/8242 , H01L21/8244 , H01L27/11
CPC分类号： G11C11/4023 , G11C11/412 , H01L27/108 , H01L27/10844 , H01L27/11 , H01L27/1108
摘要： A semiconductor memory device having as its main storage portion a capacitor storing charges as binary information and an access transistor controlling input/output of the charges to/from the capacitor, and eliminating the need for refresh, is obtained. The semiconductor memory device includes a capacitor with a storage node located above a semiconductor substrate and holding the charges corresponding to a logical level of stored binary information, an access transistor located on the semiconductor substrate surface and controlling input/output of the charges accumulated in the capacitor, and a latch circuit located on the semiconductor substrate and maintaining a potential of the capacitor storage node. At least one of circuit elements constituting the latch circuit is located above the access transistor.
摘要翻译：一种半导体存储器件，其主要存储部分是存储电荷作为二进制信息的电容器，以及控制向电容器的电荷输入/输出的存取晶体管，并且不需要刷新。半导体存储器件包括具有存储节点的电容器，该存储节点位于半导体衬底之上，并且保持对应于存储的二进制信息的逻辑电平的电荷，位于半导体衬底表面上的存取晶体管，并控制累积在该半导体衬底表面上的电荷的输入/输出电容器和位于半导体衬底上的锁存电路，并保持电容器存储节点的电位。构成锁存电路的电路元件中的至少一个位于存取晶体管的上方。

55. 发明授权

US06313319B1 Method for purifying lactide and lactide for food additives 失效
标题翻译：纯化丙交酯和丙交酯食品添加剂的方法
公开(公告)号：US06313319B1
公开(公告)日：2001-11-06
申请号：US09554101
申请日：2000-05-24
申请人： Hitomi Ohara , Hisashi Okuyama , Makoto Ogaito , Yasuhiro Fujii , Tatsushi Kawamoto , Takashi Kawabe , Yasumasa Horibe
发明人： Hitomi Ohara , Hisashi Okuyama , Makoto Ogaito , Yasuhiro Fujii , Tatsushi Kawamoto , Takashi Kawabe , Yasumasa Horibe
IPC分类号： C07D31912
CPC分类号： A23J3/08 , A23C11/06 , A23C20/00 , A23C20/025 , A23J3/16 , A23L3/3508 , A23L13/42 , A23L13/65 , A23L15/30 , A23L17/70
摘要： A crude lactide in a solid state or in an at least partially molten state is brought into contact with ethanol to form a slurry mixture, and then a solid form this slurry mixture is separated to yield a purified lactide having a high purity. A crude lactide is recrystallized from a non-denatured or denatured ethanol to obtain a lactide for a food additive. A lactide is applied widely to food additives. A coagulating agent for an animal and/or vegetable protein containing an optically active lactide as a main component, a food foaming agent containing a lactide as a main component, a food preservative containing a lactide as a main component and a pH regulating agent containing a lactide as a main component are provided.
摘要翻译：将固态或至少部分熔融状态的粗丙交酯与乙醇接触以形成浆料混合物，然后将固体形式分离出该浆料混合物，得到纯度高的纯化丙交酯。粗丙交酯从非变性或变性乙醇中重结晶，得到食品添加剂的丙交酯。丙交酯广泛应用于食品添加剂。用于含有光学活性丙交酯作为主要成分的动物和/或植物蛋白质的凝结剂，以丙交酯为主要成分的食品发泡剂，含有丙交酯作为主要成分的食品防腐剂和含有丙交酯作为主要成分。

56. 发明授权

US5973525A Integrated circuit device 失效
标题翻译：集成电路器件
公开(公告)号：US5973525A
公开(公告)日：1999-10-26
申请号：US049383
申请日：1998-03-27
申请人： Yasuhiro Fujii
发明人： Yasuhiro Fujii
IPC分类号： G11C11/407 , H03K5/135 , H03L7/00 , H03L7/081 , H03L7/06
CPC分类号： H03L7/0814 , Y10S331/02
摘要： In the present invention, when a phase comparison circuit, which compares the phase of a reference clock divided by a frequency divider that frequency divides a supplied clock, to that of a variable clock, detects the phase-matching of the two clocks, it generates a phase synchronization detection signal, and this phase synchronization detection signal increases the frequency division ratio of a frequency divider, lowering the frequency of operation of the phase comparator. The present invention is further characterized in that, at reset, when an inactive state becomes an active state, the time required to phase synchronize both clocks is shortened by resetting the above-described phase synchronization detection signal, thereby setting the frequency division ratio of the frequency divider to its original low state, and the frequency of operation of the phase comparator to its original high state. In accordance with the above-described invention, when phase synchronization is detected in an active state, the frequency division ratio of the frequency divider is increased, and the frequency of operation of the phase comparator is lowered, thus curbing power consumption. Then, at reset, this phase synchronization detection signal is reset, thus returning the frequency division ratio of the frequency divider to its original low state, and raising the frequency of phase comparator operation.
摘要翻译：在本发明中，当比较基准时钟除以频率分频时钟的分频器的相位与相位比较电路相比，可以检测出两个时钟的相位匹配时，产生相位同步检测信号，并且该相位同步检测信号增加分频器的分频比，降低相位比较器的工作频率。本发明的特征还在于，在复位时，当非活动状态变为有效状态时，通过复位上述相位同步检测信号来缩短相位同步两个时钟所需的时间，从而将分频器到其原始低电平状态，并将相位比较器的工作频率提高到原来的高电平状态。根据上述发明，当在有效状态下检测到相位同步时，分频器的分频比增加，相位比较器的工作频率降低，从而抑制功耗。然后，在复位时，该相位同步检测信号被复位，从而将分频器的分频比返回到其原始低状态，并提高相位比较器操作的频率。

57. 发明授权

US5828594A Semiconductor memory with hierarchical bit lines 失效
标题翻译：具有分层位线的半导体存储器
公开(公告)号：US5828594A
公开(公告)日：1998-10-27
申请号：US893072
申请日：1997-07-15
申请人： Yasuhiro Fujii
发明人： Yasuhiro Fujii
IPC分类号： G11C7/14 , G11C7/18 , G11C11/4097 , G11C11/4099 , G11C5/06
CPC分类号： G11C11/4097 , G11C11/4099 , G11C7/14 , G11C7/18
摘要： A semiconductor memory with hierarchical bit lines has a plurality of local bit lines, a plurality of global bit lines, a plurality of word lines, a plurality of memory cells each arranged at a connection portion between each local bit line and each word line, and a plurality of transfer gates. The local bit lines are connected to the global bit line through the transfer gates, which are arranged around the centers of the local bit lines. Further, the semiconductor memory has a dummy bit line portion having a dummy bit line that is charged up to a precharging reference voltage during a standby period and is set to a floating state during an active period, to provide the sensing reference voltage. In addition, the semiconductor has sense amplifiers each being formed in an area matching with the interval of a given number of the global bit lines and each receiving signals from a pair of the global bit lines arranged on both sides thereof.
摘要翻译：具有分层位线的半导体存储器具有多个局部位线，多个全局位线，多个字线，每个布置在每个局部位线与每个字线之间的连接部分处的多个存储器单元，以及多个传送门。局部位线通过传输门连接到全局位线，传输门被布置在局部位线的中心附近。此外，半导体存储器具有虚拟位线部分，其具有在待机期间被充电至预充电参考电压的虚拟位线，并且在有效时段期间被设置为浮置状态，以提供感测参考电压。此外，半导体具有读出放大器，每个读出放大器形成在与给定数量的全局位线的间隔匹配的区域中，并且每个接收来自布置在其两侧的一对全局位线的信号。

58. 发明授权

US5701269A Semiconductor memory with hierarchical bit lines 失效
标题翻译：具有分层位线的半导体存储器
公开(公告)号：US5701269A
公开(公告)日：1997-12-23
申请号：US668332
申请日：1996-06-25
申请人： Yasuhiro Fujii
发明人： Yasuhiro Fujii
IPC分类号： G11C7/14 , G11C7/18 , G11C11/4097 , G11C11/4099 , G11C7/00
CPC分类号： G11C11/4097 , G11C11/4099 , G11C7/14 , G11C7/18
摘要： A semiconductor memory with hierarchical bit lines has a plurality of local bit lines, a plurality of global bit lines, a plurality of word lines, a plurality of memory cells each arranged at a connection portion between each local bit line and each word line, and a plurality of transfer gates. The local bit lines are connected to the global bit line through the transfer gates, which are arranged around the centers of the local bit lines. Further, the semiconductor memory has a dummy bit line portion having a dummy bit line that is charged up to a precharging reference voltage during a standby period and is set to a floating state during an active period, to provide the sensing reference voltage. In addition, the semiconductor has sense amplifiers each being formed in an area matching with the interval of a given number of the global bit lines and each receiving signals from a pair of the global bit lines arranged on both sides thereof.
摘要翻译：具有分层位线的半导体存储器具有多个局部位线，多个全局位线，多个字线，每个布置在每个局部位线与每个字线之间的连接部分处的多个存储器单元，以及多个传送门。局部位线通过传输门连接到全局位线，传输门被布置在局部位线的中心附近。此外，半导体存储器具有虚拟位线部分，其具有在待机期间被充电至预充电参考电压的虚拟位线，并且在有效时段期间被设置为浮置状态，以提供感测参考电压。此外，半导体具有读出放大器，每个读出放大器形成在与给定数量的全局位线的间隔匹配的区域中，并且每个接收来自布置在其两侧的一对全局位线的信号。

59. 发明授权

US5663917A Semiconductor circuit having MOS circuit for use in strong electric field 失效
标题翻译：具有用于强电场的MOS电路的半导体电路
公开(公告)号：US5663917A
公开(公告)日：1997-09-02
申请号：US510862
申请日：1995-08-03
申请人： Tomoharu Oka , Hirohiko Mochizuki , Yasuhiro Fujii , Makoto Yanagisawa
发明人： Tomoharu Oka , Hirohiko Mochizuki , Yasuhiro Fujii , Makoto Yanagisawa
IPC分类号： G11C11/407 , G11C8/10 , H01L21/822 , H01L27/04 , H03K17/0812 , H03K17/10 , H03K19/00 , G11C8/00 , H03K5/00
CPC分类号： H03K17/102 , G11C8/10 , H03K17/08122
摘要： A semiconductor circuit has a first transistor, a second transistor, a third transistor, and a fourth transistor. The first and fourth transistors are a first conduction type, and the second and third transistors are a second conduction type opposite to the first conduction type. The semiconductor circuit employs a first power supply line for supplying a first voltage, a second power supply line for supplying a second voltage, and a third power supply line for supplying a third voltage outside of the range determined by the first voltage and the second voltage. The first, second, and third transistors are connected in series between the second power supply line and the third power supply line, and the fourth transistor is connected between an input terminal and a control electrode of the first transistor.
摘要翻译：半导体电路具有第一晶体管，第二晶体管，第三晶体管和第四晶体管。第一和第四晶体管是第一导电类型，第二和第三晶体管是与第一导电类型相反的第二导电类型。半导体电路采用用于提供第一电压的第一电源线，用于提供第二电压的第二电源线，以及用于将由第一电压和第二电压确定的范围之外的第三电压提供的第三电源线。第一，第二和第三晶体管串联连接在第二电源线和第三电源线之间，第四晶体管连接在第一晶体管的输入端和控制电极之间。

60. 发明授权

US5552557A Process for preparing 2-cyanoimidazole compounds by reaction of an amino ketone compound 失效
标题翻译：通过氨基酮化合物反应制备2-氰基咪唑化合物的方法
公开(公告)号：US5552557A
公开(公告)日：1996-09-03
申请号：US337523
申请日：1994-11-09
申请人： Yasuhiro Fujii , Toyoshi Tanimura
发明人： Yasuhiro Fujii , Toyoshi Tanimura
IPC分类号： C07D233/64 , C07D233/96 , C07D233/90 , C07D233/68
CPC分类号： C07D233/96
摘要： A process for preparing 2-cyanoimidazole compounds represented by the following formula (I): ##STR1## wherein R.sup.1 and R.sup.2 each independently represents a hydrogen atom, an alkyl group which may be substituted, a phenyl group which may be substituted or a heterocyclic group which may be substituted and R.sup.1 and R.sup.2 may join together to form an alkylene group which may be substituted, which comprises undergoing reaction of a compound represented by the following formula (II): ##STR2## wherein R.sup.1 and R.sup.2 are as defined above or salt thereof with cyanogen.
摘要翻译：一种制备由下式（I）表示的2-氰基咪唑化合物的方法：其中R 1和R 2各自独立地表示氢原子，可被取代的烷基，可被取代的苯基或可被取代的苯基可以被取代的杂环基，并且R 1和R 2可以连接在一起以形成可被取代的亚烷基，该杂环基包括由下式（II）表示的化合物进行反应：其中R1和R2 如上所定义，或其盐与氰。

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