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51. 发明申请

US20140264724A1 DEEP TRENCH ISOLATION 有权
标题翻译：深层分离分离
公开(公告)号：US20140264724A1
公开(公告)日：2014-09-18
申请号：US13801514
申请日：2013-03-13
申请人： Xu Cheng , Daniel J. Blomberg , Zhihong Zhang , Jiang-Kai Zuo
发明人： Xu Cheng , Daniel J. Blomberg , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/06 , H01L21/76
CPC分类号： H01L29/0638 , H01L21/761 , H01L21/76224 , H01L21/76237 , H01L21/763 , H01L21/82285 , H01L21/823878 , H01L21/8249 , H01L27/10876 , H01L29/0611 , H01L29/0649 , H01L29/1083 , H01L29/66272
摘要： An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type.
摘要翻译：集成半导体器件包括第一导电类型的衬底，位于衬底上的掩埋层，位于掩埋层的第一部分上方的隔离区域和位于隔离区域周围的隔离沟槽。穿透结构位于隔离沟槽的至少一部分周围。所述穿通结构包括所述掩埋层的第二部分，位于所述掩埋层的所述第二部分上方的第一区域，所述第一区域具有第二导电类型，以及位于所述第一区域上方的第二区域，所述第二区域具有第一种导电类型。

52. 发明授权

US09601595B2 High breakdown voltage LDMOS device 有权
公开(公告)号：US09601595B2
公开(公告)日：2017-03-21
申请号：US14968343
申请日：2015-12-14
申请人： Hongning Yang , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Hongning Yang , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L29/66 , H01L29/78 , H01L29/10 , H01L21/762 , H01L29/06
CPC分类号： H01L29/66689 , H01L21/76229 , H01L21/76264 , H01L29/0653 , H01L29/1083 , H01L29/66484 , H01L29/66772 , H01L29/7824
摘要： A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region (81) and a substantially asymmetric, laterally edge-proximate, second LDMOS region (83). A deep trench isolation (DTI) wall (60) substantially laterally terminates the laterally edge-proximate second LDMOS region (83). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region (83) associated with the DTI wall (60) are avoided by providing a doped SC buried layer region (86) in the SOI support structure (21) proximate the DTI wall (60), underlying a portion of the laterally edge-proximate second LDMOS region (83) and of opposite conductivity type than a drain region (31) of the laterally edge-proximate second LDMOS region (83).

53. 发明申请

US20150097238A1 Mergeable Semiconductor Device with Improved Reliability 有权
标题翻译：具有提高可靠性的可合并半导体器件
公开(公告)号：US20150097238A1
公开(公告)日：2015-04-09
申请号：US14047348
申请日：2013-10-07
申请人： Zhihong Zhang , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
发明人： Zhihong Zhang , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/66 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66659 , H01L21/26513 , H01L21/761 , H01L21/76224 , H01L21/823418 , H01L21/823481 , H01L27/088 , H01L29/0642 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1095 , H01L29/36 , H01L29/66575 , H01L29/6659 , H01L29/7833 , H01L29/7835 , H01L29/786 , H01L29/78615 , H01L29/78624 , H01L29/78654
摘要： A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite body region disposed in the semiconductor substrate and having a second conductivity type. The composite body region includes a first well region that extends laterally across the source and drain regions and a second well region disposed in the first well region. The drain region is disposed in the second well region such that charge carriers flow from the first well region into the second well region to reach the drain region. The second well region includes dopant of the first conductivity type to have a lower net dopant concentration level than the first well region. A pocket may be disposed in a drain extension region and configured to establish a depletion region along an edge of a gate structure.
摘要翻译：一种器件包括半导体衬底，设置在半导体衬底中的源极和漏极区域，具有第一导电类型，并且彼此横向间隔开;以及复合体区域，设置在半导体衬底中并且具有第二导电类型。复合体区域包括沿着源极和漏极区域横向延伸的第一阱区域和设置在第一阱区域中的第二阱区域。漏极区域设置在第二阱区域中，使得载流子从第一阱区域流入第二阱区域以到达漏极区域。第二阱区域包括具有比第一阱区域更低的净掺杂剂浓度水平的第一导电类型的掺杂剂。凹槽可以设置在漏极延伸区域中并且被配置成沿着栅极结构的边缘建立耗尽区域。

54. 发明申请

US20140001545A1 HIGH BREAKDOWN VOLTAGE LDMOS DEVICE 有权
标题翻译：高电压LDMOS器件
公开(公告)号：US20140001545A1
公开(公告)日：2014-01-02
申请号：US13537619
申请日：2012-06-29
申请人： Hongning Yang , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Hongning Yang , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66689 , H01L21/76229 , H01L21/76264 , H01L29/0653 , H01L29/1083 , H01L29/66484 , H01L29/66772 , H01L29/7824
摘要： A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region (81) and a substantially asymmetric, laterally edge-proximate, second LDMOS region (83). A deep-trench isolation (DTI) wall (60) substantially laterally terminates the laterally edge-proximate second LDMOS region (83). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region (83) associated with the DTI wall (60) are avoided by providing a doped SC buried layer region (86) in the SOI support structure (21) proximate the DTI wall (60), underlying a portion of the laterally edge-proximate second LDMOS region (83) and of opposite conductivity type than a drain region (31) of the laterally edge-proximate second LDMOS region (83).
摘要翻译：多区域（81,83）横向扩散金属氧化物半导体（LDMOS）器件（40）具有绝缘体上半导体（SOI）支撑结构（21），其上形成有基本上对称的横向内部的第一LDMOS区域（81）和基本不对称的横向边缘邻近的第二LDMOS区域（83）。深沟槽隔离（DTI）壁（60）基本上横向地终止横向边缘邻近的第二LDMOS区域（83）。通过在SOI中提供掺杂的SC掩埋层区域（86）来避免由与DTI壁（60）相关联的横向边缘邻近的第二LDMOS区域（83）表现出的电场增强和较低的源极 - 漏极击穿电压（BVDSS）靠近DTI壁（60）的支撑结构（21），位于横向边缘邻近的第二LDMOS区域（83）的一部分下方并且具有与横向边缘邻近的第二LDMOS区域的漏极区域（31）相反的导电类型 83）。

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