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51. 发明申请

US20050149915A1 Methods and apparatus for optimizing a program undergoing dynamic binary translation using profile information 审中-公开
标题翻译：用于使用简档信息优化正在进行动态二进制翻译的程序的方法和装置
公开(公告)号：US20050149915A1
公开(公告)日：2005-07-07
申请号：US10747598
申请日：2003-12-29
申请人： Youfeng Wu , Orna Etzion
发明人： Youfeng Wu , Orna Etzion
IPC分类号： G06F9/45
CPC分类号： G06F9/45516
摘要： Methods and apparatus for optimizing a program undergoing dynamic binary translation using profile information are disclosed. A disclosed system optimizes foreign program instructions through an enhanced dynamic binary translation process. The foreign program instructions are translated into native program instructions. Loops within the native program instructions are instrumented with profiling instructions and optimized. The profiling information is collected during execution of the loop. After profiling information is collected, the loop may be further optimized by inserting prefetching instructions into the optimized loop. The prefetched loop is then linked back into the native program instructions and is executable.
摘要翻译：公开了使用简档信息优化正在进行动态二进制翻译的程序的方法和装置。所公开的系统通过增强的动态二进制翻译过程来优化外部程序指令。外部程序指令被翻译成本机程序指令。本地程序指令中的循环使用分析说明进行了优化。在循环执行期间收集分析信息。在收集了分析信息之后，可以通过将预取指令插入到优化的循环中来进一步优化循环。然后将预取的循环链接回本机程序指令，并且是可执行的。

52. 发明授权

US06332214B1 Accurate invalidation profiling for cost effective data speculation 失效
标题翻译：精确的无效分析，用于成本有效的数据投机
公开(公告)号：US06332214B1
公开(公告)日：2001-12-18
申请号：US09075147
申请日：1998-05-08
申请人： Youfeng Wu
发明人： Youfeng Wu
IPC分类号： G06F9445
CPC分类号： G06F8/433 , G06F8/445
摘要： In one implementation, the invention involves a computer implemented method used in compiling a program. The method includes selecting conflict regions of the program. The method further includes performing invalidation profiling of load instructions with respect to certain ones of the conflict regions to determine invalidation rates of the load instructions. The method may further include a feedback step in which the invalidation rates are used by a scheduler of the compiler to determine whether to move the load instructions to target locations.
摘要翻译：在一个实现中，本发明涉及用于编译程序的计算机实现的方法。该方法包括选择程序的冲突区域。该方法还包括执行关于某些冲突区域的加载指令的无效分析，以确定加载指令的无效率。该方法还可以包括反馈步骤，其中编译器的调度器使用无效率来确定是否将加载指令移动到目标位置。

53. 发明授权

US09519467B2 Efficient and consistent software transactional memory 有权
标题翻译：高效一致的软件事务内存
公开(公告)号：US09519467B2
公开(公告)日：2016-12-13
申请号：US13246678
申请日：2011-09-27
申请人： Cheng Wang , Youfeng Wu , Wei-Yu Chen , Bratin Saha , Ali Reza Adl-Tabatabai
发明人： Cheng Wang , Youfeng Wu , Wei-Yu Chen , Bratin Saha , Ali Reza Adl-Tabatabai
IPC分类号： G06F7/00 , G06F17/30 , G06F9/45 , G06F9/46 , G06F9/30
CPC分类号： G06F8/458 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/3863 , G06F9/467
摘要： A method and apparatus for efficient and consistent validation/conflict detection in a Software Transactional Memory (STM) system is herein described. A version check barrier is inserted after a load to compare versions of loaded values before and after the load. In addition, a global timestamp (GTS) is utilized to track a latest committed transaction. Each transaction is associated with a local timestamp (LTS) initialized to the GTS value at the start of a transaction. As a transaction commits it updates the GTS to a new value and sets versions of modified locations to the new value. Pending transactions compare versions determined in read barriers to their LTS. If the version is greater than their LTS indicating another transaction has committed after the pending transaction started and initialized the LTS, then the pending transaction validates its read set to maintain efficient and consistent transactional execution.
摘要翻译：这里描述了用于在软件事务存储器（STM）系统中有效且一致的验证/冲突检测的方法和装置。在加载之后插入版本检查障碍，以便在加载之前和之后比较加载值的版本。此外，使用全局时间戳（GTS）来跟踪最近提交的事务。每个事务与在事务开始时初始化为GTS值的本地时间戳（LTS）相关联。作为事务提交，将GTS更新为新值，并将修改的位置的版本设置为新值。待处理的交易将比较其在LTS阅读障碍中确定的版本。如果版本大于其LTS，指示在挂起事务启动并初始化LTS之后另一个事务已经提交，则挂起的事务会验证其读取集合以保持有效且一致的事务执行。

54. 发明申请

US20160116964A1 DYNAMIC CORE SELECTION FOR HETEROGENEOUS MULTI-CORE SYSTEMS 审中-公开
公开(公告)号：US20160116964A1
公开(公告)日：2016-04-28
申请号：US14986677
申请日：2016-01-02
申请人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
发明人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
IPC分类号： G06F1/32 , G06F9/50 , G06F9/48 , G06F9/38
CPC分类号： G06F1/329 , G06F1/3287 , G06F9/3851 , G06F9/445 , G06F9/4893 , G06F9/5027 , G06F9/5094 , G06F11/3409 , G06F11/3452 , G06F11/3466 , G06F2201/81 , G06F2201/865 , G06F2201/88 , G06F2209/501 , Y02D10/171 , Y02D10/22 , Y02D10/34 , Y02D50/20
摘要： Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

55. 发明申请

US20160116963A1 DYNAMIC CORE SELECTION FOR HETEROGENEOUS MULTI-CORE SYSTEMS 审中-公开
标题翻译：异构多核系统的动态核心选择
公开(公告)号：US20160116963A1
公开(公告)日：2016-04-28
申请号：US14986676
申请日：2016-01-02
申请人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
发明人： Youfeng Wu , Shiliang Hu , Edson Borin , Cheng Wang
IPC分类号： G06F1/32 , G06F9/50
摘要： Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.
摘要翻译：可以通过在第一处理核上执行程序代码来执行异构多核处理系统上的动态切换核。可以用信号通知第二处理核心的加电。可以收集执行程序代码的第一处理核心的第一性能度量。当第一性能指标优于先前确定的核心性能指标时，可以发信号通知第二处理核心的掉电，并且可以在第一处理核心上继续执行程序代码。当第一性能度量不比先前确定的核心性能指标更好时，程序代码的执行可以从第一处理核心切换到第二处理核心。

56. 发明授权

US09152417B2 Expediting execution time memory aliasing checking 有权
标题翻译：加快执行时间内存混叠检查
公开(公告)号：US09152417B2
公开(公告)日：2015-10-06
申请号：US13996610
申请日：2011-09-27
申请人： Cheng Wang , Youfeng Wu
发明人： Cheng Wang , Youfeng Wu
IPC分类号： G06F9/45 , G06F9/30 , G06F9/455 , G06F9/38
CPC分类号： G06F9/30098 , G06F8/434 , G06F8/4441 , G06F9/3834 , G06F9/45516
摘要： Embodiments of apparatus, computer-implemented methods, systems, and computer-readable media are described herein for expediting execution time memory alias checking. A sequence of instructions targeted for execution on an execution processor may be received or retrieved. The execution processor may include a plurality of alias registers and circuitry configured to check entries in the alias register for memory aliasing. One or more optimizations may be performed on the received or retrieved sequence of instructions to optimize execution performance of the received or retrieved sequence of instructions. This may include a reorder of a plurality of memory instructions in the received or retrieved sequence of instructions. After the optimization, one or more move instructions may be inserted in the optimized sequence of instructions to move one or more entries among the alias registers during execution, to expedite alias checking at execution time. Other embodiments may be described and/or claimed.
摘要翻译：本文描述了装置，计算机实现的方法，系统和计算机可读介质的实施例，用于加速执行时间存储器别名检查。可以接收或检索针对执行处理器执行的指令序列。执行处理器可以包括多个别名寄存器和被配置为检查别名寄存器中的条目以用于存储器混叠的电路。可以对所接收或检索的指令序列执行一个或多个优化，以优化所接收或检索的指令序列的执行性能。这可以包括在接收或检索的指令序列中的多个存储器指令的重排序。在优化之后，可以在优化的指令序列中插入一个或多个移动指令以在执行期间移动别名寄存器中的一个或多个条目，以在执行时加速别名检查。可以描述和/或要求保护其他实施例。

57. 发明申请

US20150277866A1 CO-DESIGNED DYNAMIC LANGUAGE ACCELERATOR FOR A PROCESSOR 有权
标题翻译：用于处理器的CO设计动态语言加速器
公开(公告)号：US20150277866A1
公开(公告)日：2015-10-01
申请号：US14225755
申请日：2014-03-26
申请人： Cheng Wang , Youfeng Wu , Hongbo Rong , Hyunchul Park
发明人： Cheng Wang , Youfeng Wu , Hongbo Rong , Hyunchul Park
IPC分类号： G06F9/45 , G06F9/455
CPC分类号： G06F9/45516 , G06F9/4411 , G06F9/4552 , G06F13/10
摘要： In an embodiment, a processor includes at least one core and a dynamic language accelerator to execute a bytecode responsive to a memory mapped input/output (MMIO) operation on a file descriptor associated with the dynamic language accelerator. The processor may block execution of native code while the dynamic language accelerator executes the bytecode. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括至少一个核心和动态语言加速器，以响应于与动态语言加速器相关联的文件描述符的存储器映射的输入/输出（MMIO）操作来执行字节码。当动态语言加速器执行字节码时，处理器可能会阻止本地代码的执行。描述和要求保护其他实施例。

58. 发明申请

US20150039861A1 ALLOCATION OF ALIAS REGISTERS IN A PIPELINED SCHEDULE 有权
标题翻译：在管道附表中分配ALIAS注册
公开(公告)号：US20150039861A1
公开(公告)日：2015-02-05
申请号：US14126466
申请日：2013-05-30
申请人： Hongbo Rong , Cheng Wang , Hyunchul Park , Youfeng Wu
发明人： Hongbo Rong , Cheng Wang , Hyunchul Park , Youfeng Wu
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3838 , G06F8/434 , G06F8/441 , G06F8/443 , G06F9/30127 , G06F9/3017 , G06F9/3834 , G06F9/384
摘要： In an embodiment, a system includes a processor including one or more cores and a plurality of alias registers to store memory range information associated with a plurality of operations of a loop. The memory range information references one or more memory locations within a memory. The system also includes register assignment means for assigning each of the alias registers to a corresponding operation of the loop, where the assignments are made according to a rotation schedule, and one of the alias registers is assigned to a first operation in a first iteration of the loop and to a second operation in a subsequent iteration of the loop. The system also includes the memory coupled to the processor. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，系统包括处理器，其包括一个或多个核和多个别名寄存器，用于存储与循环的多个操作相关联的存储器范围信息。存储器范围信息引用存储器内的一个或多个存储器位置。该系统还包括寄存器分配装置，用于将每个别名寄存器分配给循环的对应操作，其中根据旋转调度进行分配，并且在第一次迭代中将一个别名寄存器分配给第一操作循环和循环的后续迭代中的第二操作。该系统还包括耦合到处理器的存储器。描述和要求保护其他实施例。

59. 发明申请

US20140359591A1 DYNAMIC OPTIMIZATION OF PIPELINED SOFTWARE 有权
标题翻译：管道软件动态优化
公开(公告)号：US20140359591A1
公开(公告)日：2014-12-04
申请号：US14126463
申请日：2013-05-30
申请人： Hyunchul Park , Hongbo Rong , Youfeng Wu
发明人： Hyunchul Park , Hongbo Rong , Youfeng Wu
IPC分类号： G06F9/45
CPC分类号： G06F8/4452 , G06F8/441 , G06F8/443 , G06F8/4451 , G06F9/3836 , G06F9/384 , G06F9/3863
摘要： In an embodiment, a system includes a processor including at least one core to execute operations of a loop that includes S stages. The system also includes stage insertion means for adding a delay stage to the loop to increase a lifetime of a corresponding register associated with a first variable of the loop and to delay storage of contents of the register. The system also includes a dynamic random access memory (DRAM). Other embodiments are described and claimed.
摘要翻译：在一个实施例中，系统包括处理器，其包括至少一个核，以执行包括S级的循环的操作。该系统还包括阶段插入装置，用于向环路增加延迟级，以增加与循环的第一变量相关联的相应寄存器的寿命并延迟存储寄存器的内容。该系统还包括动态随机存取存储器（DRAM）。描述和要求保护其他实施例。

60. 发明申请

US20140032885A1 METHODS AND APPARATUS TO MANAGE PARTIAL-COMMIT CHECKPOINTS WITH FIXUP SUPPORT 有权
标题翻译：使用固定支持管理部分提交检查的方法和设备
公开(公告)号：US20140032885A1
公开(公告)日：2014-01-30
申请号：US14041170
申请日：2013-09-30
申请人： Edson Borin , Youfeng Wu
发明人： Edson Borin , Youfeng Wu
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3834 , G06F9/3842 , G06F9/3857 , G06F9/3863
摘要： Example methods and apparatus to manage partial commit-checkpoints are disclosed. A disclosed example method includes identifying a commit instruction associated with a region of instructions executed by a processor, identifying candidate instructions from the region of instructions, and generating a processor partial commit-checkpoint to save a current state of the processor, the checkpoint based on calculated register values associated with live instructions, and including instruction reference addresses to link the candidate instructions.
摘要翻译：公开了用于管理部分提交检查点的示例性方法和装置。所公开的示例性方法包括识别与由处理器执行的指令区域相关联的提交指令，从指令区域识别候选指令，以及生成处理器部分提交检查点以保存处理器的当前状态，所述检查点基于与实时指令相关联的计算寄存器值，并包括链接候选指令的指令参考地址。

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