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51. 发明申请

US20060208785A1 VARIABLE DELAY CIRCUITRY 有权
标题翻译：可变延迟电路
公开(公告)号：US20060208785A1
公开(公告)日：2006-09-21
申请号：US11083482
申请日：2005-03-18
申请人： Andy Lee , Gary Lai , Changsong Zhang , Vaughn Betz , Ryan Fung
发明人： Andy Lee , Gary Lai , Changsong Zhang , Vaughn Betz , Ryan Fung
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00058
摘要： Circuitry for providing an input data signal to other circuitry on an integrated circuit includes a course delay chain and a fine delay chain. These two delay chains are cascadable, if desired, to provide a very wide range of possible amounts of delay which can be finely graded by use of the fine delay chain.
摘要翻译：用于向集成电路上的其它电路提供输入数据信号的电路包括一个课程延迟链和一个精细延迟链。如果需要，这两个延迟链是可级联的，以提供可以通过使用精细延迟链精细分级的可能的延迟量的非常宽的范围。

52. 发明授权

US06937064B1 Versatile logic element and logic array block 有权
公开(公告)号：US06937064B1
公开(公告)日：2005-08-30
申请号：US10280723
申请日：2002-10-24
申请人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
发明人： David M. Lewis , Paul Leventis , Andy L. Lee , Henry Kim , Bruce Pedersen , Chris Wysocki , Christopher F. Lane , Alexander Marquardt , Vikram Santurkar , Vaughn Betz
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17764 , H03K19/1737 , H03K19/17728 , H03K19/17736
摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

53. 发明授权

US06828824B2 Heterogeneous interconnection architecture for programmable logic devices 失效
公开(公告)号：US06828824B2
公开(公告)日：2004-12-07
申请号：US10449753
申请日：2003-05-30
申请人： Vaughn Betz , Jonathan Rose
发明人： Vaughn Betz , Jonathan Rose
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K19/17704
摘要： An interconnection architecture for programmable logic devices (PLDs) is presented in which heterogeneous interconnect resources can be programmably connected to function blocks in accordance with two or more operational parameters, such as, for example, signal propagation speed, circuit area, signal routing flexibility, and PLD reliability. Programmable interconnect resources include unbalanced multiplexers, different types of interface buffers, and signal wires of different widths and different wire-to-wire spacings.

54. 发明授权

US06826741B1 Flexible I/O routing resources 有权
标题翻译：灵活的I / O路由资源
公开(公告)号：US06826741B1
公开(公告)日：2004-11-30
申请号：US10289629
申请日：2002-11-06
申请人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Triet Nguyen , David Jefferson , Paul Leventis , David Lewis , Vaughn Betz , Michael Chan
发明人： Brian D. Johnson , Andy L. Lee , Cameron McClintock , Triet Nguyen , David Jefferson , Paul Leventis , David Lewis , Vaughn Betz , Michael Chan
IPC分类号： G06F1750
CPC分类号： H03K19/17736 , H03K19/17744
摘要： In one aspect, flexible routing resources provided are comprising an arrangement of staggered line segments on a periphery of an electronic device. In another aspect, I/O bus lines a re coupled to receive signals from and to provide signals to other bus lines, core routing, and I/O circuitry, thus facilitating the use of the I/O bus for a variety of routes that may include I/O-to-core, core-to-I/O and core-to-core routes. In another aspect, a length of I/O bus lines is optimized for speed over long signal routes with high fanout. In another aspect, the loading effects of high fanout are minimized by using a plurality of tapping buffers to couple lines to both core routing and to I/O circuitry. In another aspect, a spiraling technique is provided that allows a continuous bus having line segments of consistent length whether or not the number of I/O blocks is an integral multiple of the selected logical length for line segments.
摘要翻译：在一个方面，提供的灵活路由资源包括在电子设备的外围上的交错线段的布置。在另一方面，I / O总线线路被耦合以从其接收信号并向其它总线线路，核心路由和I / O电路提供信号，从而便于将I / O总线用于各种路由，可能包括I / O到核心，核到I / O和核心到核心的路由。在另一方面，I / O总线的长度针对具有高扇出的长信号路由的速度被优化。在另一方面，通过使用多个分接缓冲器来将线耦合到核心路由和I / O电路两者，高扇出的负载效应被最小化。在另一方面，提供一种螺旋式技术，其允许具有一致长度的线段的连续总线，无论I / O块的数量是否为线段的所选逻辑长度的整数倍。

55. 发明授权

US09594859B1 Apparatus and associated methods for parallelizing clustering and placement 有权
标题翻译：用于并行聚类和放置的装置和相关方法
公开(公告)号：US09594859B1
公开(公告)日：2017-03-14
申请号：US12040730
申请日：2008-02-29
申请人： Ketan Padalia , Adrian Ludwin , Ryan Fung , Vaughn Betz
发明人： Ketan Padalia , Adrian Ludwin , Ryan Fung , Vaughn Betz
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/5036 , G06F9/46 , G06F17/10 , G06F17/504 , G06F17/505 , G06F17/5054 , G06F17/5072
摘要： A system for parallelizing software in computer-aided design (CAD) software for circuit design includes a computer. The computer is configured to form or optimize a plurality of clusters in parallel. Each cluster in the plurality of clusters includes a set of nodes in a netlist in a design. The computer is configured to determine placements for blocks in a netlist in parallel, based on iterative improvement, partitioning, or analytic techniques.
摘要翻译：用于电路设计的计算机辅助设计（CAD）软件中并行化软件的系统包括计算机。计算机被配置为并行地形成或优化多个簇。多个群集中的每个群集包括设计中网表中的一组节点。计算机被配置为基于迭代改进，分区或分析技术来并行地确定网表中的块的布局。

56. 发明授权

US08572530B1 Method and apparatus for performing path-level skew optimization and analysis for a logic design 有权
标题翻译：用于执行逻辑设计的路径级偏移优化和分析的方法和装置
公开(公告)号：US08572530B1
公开(公告)日：2013-10-29
申请号：US12928245
申请日：2010-12-06
申请人： Ryan Fung , Vaughn Betz , David Karchmer
发明人： Ryan Fung , Vaughn Betz , David Karchmer
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F1/10
摘要： A method for designing a system including optimizing path-level skew in the system and analyzing path-level skew in the system. Other embodiments are also disclosed.
摘要翻译：一种用于设计系统的方法，包括优化系统中的路径级偏差并分析系统中的路径级偏差。还公开了其他实施例。

57. 发明授权

US08271821B2 Flexible RAM clock enable 有权
标题翻译：灵活的RAM时钟使能
公开(公告)号：US08271821B2
公开(公告)日：2012-09-18
申请号：US12145440
申请日：2008-06-24
申请人： Jinyong Yuan , Christopher F. Lane , David E. Jefferson , Vaughn Betz
发明人： Jinyong Yuan , Christopher F. Lane , David E. Jefferson , Vaughn Betz
IPC分类号： G06F1/04 , G06F1/12
CPC分类号： G11C7/1075 , G11C8/18 , H03K19/1737
摘要： A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block.
摘要翻译：第一组配置逻辑可配置为提供用于控制存储器块的第一端口的输入寄存器的第一端口输入时钟信号。第二组配置逻辑可配置为提供用于控制存储器块的第二端口的输入寄存器的第二端口输入时钟信号。

58. 发明授权

US08250500B1 Method and apparatus for deriving signal activities for power analysis and optimization 有权
标题翻译：用于导出功率分析和优化的信号活动的方法和装置
公开(公告)号：US08250500B1
公开(公告)日：2012-08-21
申请号：US11414803
申请日：2006-05-01
申请人： David Neto , Vaughn Betz , Jennifer Farrugia , Meghal Varia
发明人： David Neto , Vaughn Betz , Jennifer Farrugia , Meghal Varia
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method for managing simulation includes modifying a design for a system to allow for a path pulse filter to filter a pathpulse delay, on a signal transmitted to a component, that is greater than an IOpath delay.
摘要翻译：一种用于管理仿真的方法包括修改系统的设计以允许路径脉冲滤波器对发送到组件的信号滤波大于IO路径延迟的路径脉冲延迟。

59. 发明申请

US20120089958A1 Apparatus and Methods for Optimizing the Performance of Programmable Logic Devices 审中-公开
标题翻译：用于优化可编程逻辑器件性能的装置和方法
公开(公告)号：US20120089958A1
公开(公告)日：2012-04-12
申请号：US13326082
申请日：2011-12-14
申请人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
发明人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5077 , H03K19/17784
摘要： A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least one of the first and second supply voltages is determined by a PLD computer-aided design (CAD) flow used to implement the user's design in the PLD.
摘要翻译：可编程逻辑器件（PLD）包括第一和第二电路。第一和第二电路是使用PLD资源实现的用户设计的一部分。第一个电路由第一个电源供电。第二电路由第二电源供电。第一和第二电源电压中的至少一个由用于在PLD中实现用户设计的PLD计算机辅助设计（CAD）流确定。

60. 发明授权

US08103975B2 Apparatus and methods for optimizing the performance of programmable logic devices using multiple supply voltage 有权
标题翻译：使用多电源电压优化可编程逻辑器件的性能的装置和方法
公开(公告)号：US08103975B2
公开(公告)日：2012-01-24
申请号：US12165664
申请日：2008-07-01
申请人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
发明人： David Lewis , Vaughn Betz , Paul Leventis , Christopher Lane , Andy Lee , Jeffrey Watt , Timothy Vanderhoek
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5077 , H03K19/17784
摘要： A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least one of the first and second supply voltages is determined by a PLD computer-aided design (CAD) flow used to implement the user's design in the PLD.
摘要翻译：可编程逻辑器件（PLD）包括第一和第二电路。第一和第二电路是使用PLD资源实现的用户设计的一部分。第一个电路由第一个电源供电。第二电路由第二电源供电。第一和第二电源电压中的至少一个由用于在PLD中实现用户设计的PLD计算机辅助设计（CAD）流确定。

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