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51. 发明授权

US07659167B2 Method for improving the performance of flash memory by using microcrystalline silicon film as a floating gate 有权
标题翻译：通过使用微晶硅膜作为浮动栅极来提高闪存性能的方法
公开(公告)号：US07659167B2
公开(公告)日：2010-02-09
申请号：US11422059
申请日：2006-06-02
申请人： Tzung-Ting Han , Chin-Ta Su , Yun-Chi Yang
发明人： Tzung-Ting Han , Chin-Ta Su , Yun-Chi Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/4916 , H01L21/02532 , H01L21/02576 , H01L21/02595 , H01L21/0262 , H01L21/28273 , H01L29/42324
摘要： This invention provides a method for forming polysilicon by using silane with introducing hydrogen, such that polysilicon is microcrystalline. This microcrystal polysilicon can be applied to floating gate of flash memory to improve the character of flash memory.
摘要翻译：本发明提供了一种通过使用硅烷引入氢来形成多晶硅的方法，使得多晶硅是微晶的。这种微晶多晶硅可以应用于闪存的浮动栅极，以提高闪存的性能。

52. 发明申请

US20060063390A1 HDPCVD PROCESS AND METHOD FOR IMPROVING UNIFORMITY OF FILM THICKNESS 有权
标题翻译： HDPCVD方法和改善膜厚度均匀性的方法
公开(公告)号：US20060063390A1
公开(公告)日：2006-03-23
申请号：US10711512
申请日：2004-09-23
申请人： Chien-Hung Lu , Chin-Ta Su
发明人： Chien-Hung Lu , Chin-Ta Su
IPC分类号： H01L21/469
CPC分类号： C23C16/50 , C23C16/4584
摘要： A high density plasma chemical vapor deposition (HDPCVD) process is disclosed. First, a first deposition step is performed on a wafer. Then, the wafer is rotated with an angle. A second deposition step is performed for completing the deposition. By the rotation of the wafer, the thin film is formed with a desired uniformity.
摘要翻译：公开了一种高密度等离子体化学气相沉积（HDPCVD）工艺。首先，在晶片上进行第一沉积步骤。然后，晶片以一定角度旋转。执行第二沉积步骤以完成沉积。通过晶片的旋转，以期望的均匀性形成薄膜。

53. 发明授权

US06624023B1 Method for improving the performance of flash memory 有权
标题翻译：提高闪存性能的方法
公开(公告)号：US06624023B1
公开(公告)日：2003-09-23
申请号：US10152585
申请日：2002-05-23
申请人： Tzung-Ting Han , Chun-Lein Su , Chin-Ta Su
发明人： Tzung-Ting Han , Chun-Lein Su , Chin-Ta Su
IPC分类号： H01L21336
CPC分类号： H01L27/115 , H01L27/11521 , Y10S438/954
摘要： The method for improving the performance of flash memory. A substrate is proved. A tunnel oxide layer is formed on the substrate. There two gate, structure are formed on the tunnel oxide layer. The gate structure including a first polysilicon layer as a floating gate, an interpoly dielectric layer such as ONO layer on the floating gate, a second polysilicon layer as a control gate on the interpoly dielectric layer. Moreover, the poly stringer is exit between the gates, wherein the poly stringer is unmovied after etched. Next, the oxygen free radical process cell oxidation is processed. The results ONO encroachment is very slightly then improvement of 6% GCR with pre-mixing gas process cell oxidation can increase operation speed by more than 5 times and eliminated poly stringer.
摘要翻译：提高闪存性能的方法。证明了底物。在衬底上形成隧道氧化物层。在隧道氧化层上形成两个门，结构。栅极结构包括作为浮置栅极的第一多晶硅层，浮置栅极上的诸如ONO层的多晶硅间介质层，作为在多晶硅间介电层上的控制栅极的第二多晶硅层。此外，多晶硅在栅极之间离开，其中多晶硅在蚀刻后不被剥离。接下来，处理氧自由基过程电池氧化。结果ONO侵蚀非常轻微，然后改进6％GCR，预混合气体处理池氧化可以将操作速度提高5倍以上，消除多边形。

54. 发明授权

US08288280B2 Conductor removal process 有权
标题翻译：导体去除过程
公开(公告)号：US08288280B2
公开(公告)日：2012-10-16
申请号：US11780024
申请日：2007-07-19
申请人： Yung-Tai Hung , Chin-Tsan Yeh , Chin-Ta Su , Ling-Wu Yang , Tung-Han Chuang
发明人： Yung-Tai Hung , Chin-Tsan Yeh , Chin-Ta Su , Ling-Wu Yang , Tung-Han Chuang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/3212 , H01L21/32105
摘要： A conductor removal process is described, which is applied to a substrate that has thereon a plurality of patterns and a blanket conductor layer covering the patterns. An upper portion of the blanket conductor layer entirely over the patterns is oxidized to form a dielectric layer. A CMP step is performed to remove the dielectric layer and a portion of the remaining conductor layer in turn and thereby expose the patterns.
摘要翻译：描述了导体去除工艺，其应用于其上具有多个图案的基板和覆盖图案的覆盖层导体层。橡皮布导体层的整个图案上方的上部被氧化以形成电介质层。执行CMP步骤以依次去除电介质层和剩余导体层的一部分，从而暴露图案。

55. 发明授权

US07341910B2 Method for forming a flash memory by using a microcrystalline polysilicon layer as a floating gate 有权
标题翻译：通过使用微晶多晶硅层作为浮动栅极形成闪速存储器的方法
公开(公告)号：US07341910B2
公开(公告)日：2008-03-11
申请号：US10192565
申请日：2002-07-11
申请人： Tzung-Ting Han , Chin-Ta Su , Yun-Chi Yang
发明人： Tzung-Ting Han , Chin-Ta Su , Yun-Chi Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/4916 , H01L21/02532 , H01L21/02576 , H01L21/02595 , H01L21/0262 , H01L21/28273 , H01L29/42324
摘要： This invention provides a method for forming a microcrystalline polysilicon layer by using silane or dislane with introducing hydrogen gas. This microcrystalline polysilicon layer can be used as a floating gate of a flash memory to improve the character of the flash memory.
摘要翻译：本发明提供一种通过使用硅烷或二异氰酸酯引入氢气来形成微晶多晶硅层的方法。该微晶多晶硅层可以用作闪存的浮动栅极以改善闪存的特性。

56. 发明授权

US07235496B2 HDPCVD process and method for improving uniformity of film thickness 有权
标题翻译： HDPCVD工艺和提高膜厚均匀性的方法
公开(公告)号：US07235496B2
公开(公告)日：2007-06-26
申请号：US10711512
申请日：2004-09-23
申请人： Chien-Hung Lu , Chin-Ta Su
发明人： Chien-Hung Lu , Chin-Ta Su
IPC分类号： H01L21/31
CPC分类号： C23C16/50 , C23C16/4584
摘要： A high density plasma chemical vapor deposition (HDPCVD) process is disclosed. First, a first deposition step is performed on a wafer. Then, the wafer is rotated with an angle. A second deposition step is performed for completing the deposition. By the rotation of the wafer, the thin film is formed with a desired uniformity.
摘要翻译：公开了一种高密度等离子体化学气相沉积（HDPCVD）工艺。首先，在晶片上进行第一沉积步骤。然后，晶片以一定角度旋转。执行第二沉积步骤以完成沉积。通过晶片的旋转，以期望的均匀性形成薄膜。

57. 发明申请

US20060094232A1 Methods of forming planarized multilevel metallization in an integrated circuit 有权
标题翻译：在集成电路中形成平面化多层金属化的方法
公开(公告)号：US20060094232A1
公开(公告)日：2006-05-04
申请号：US10976539
申请日：2004-10-29
申请人： Chin-Ta Su , Jerry Lai , Yu-Lin Yen
发明人： Chin-Ta Su , Jerry Lai , Yu-Lin Yen
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/0276 , H01L21/32139 , H01L21/7685
摘要： A method is provided for forming a semiconductor device that reduces metal-stress-induced photo misalignment by incorporating a multi-layered anti-reflective coating over a metal layer. The method includes providing a substrate with a conductive layer formed over the substrate, depositing a multi-layered anti-reflective coating (including alternating layers of titanium and titanium nitride), defining a plurality of conductive lines in connection with a first etching step, depositing a dielectric layer, and defining at least one via in connection with a second etching step.
摘要翻译：提供了一种形成半导体器件的方法，该半导体器件通过在金属层上并入多层抗反射涂层来减少金属应力诱导的光失准。该方法包括：在衬底上形成导电层的衬底，沉积多层抗反射涂层（包括钛和氮化钛的交替层），与第一蚀刻步骤相结合形成多条导电线，沉积介电层，并且与第二蚀刻步骤相关地限定至少一个通孔。

58. 发明申请

US20050109608A1 Method of improving thermal stability for cobalt salicide 审中-公开
标题翻译：改善钴硅化物热稳定性的方法
公开(公告)号：US20050109608A1
公开(公告)日：2005-05-26
申请号：US10719759
申请日：2003-11-20
申请人： Chin-Ta Su
发明人： Chin-Ta Su
IPC分类号： C23C14/32 , H01L21/336 , H01L29/78
CPC分类号： H01L29/665 , H01L29/78
摘要： A method of improving thermal stability for cobalt salicide includes providing a substrate which has a silicon layer formed thereon. A cobalt layer is formed over the silicon layer, and TiNx layer is formed over the cobalt layer. The TiNx layer includes x atoms of nitrogen for each atom of titanium in a TiNx molecule, and a value of x is greater than 0.9. A first thermal process is then performed to form a cobalt salicide layer over the silicon layer. Any non-reactive cobalt is removed, and a second thermal process is performed to enhance the conductivity of the cobalt salicide layer.
摘要翻译：提供钴硅化物的热稳定性的方法包括提供其上形成有硅层的衬底。在硅层上形成钴层，在钴层上形成TiN层。 TiN x分子中的TiN x分子中的每个钛原子包含x个氮原子，x的值大于0.9。然后执行第一热处理以在硅层上形成钴自对准硅层。去除任何非反应性钴，并且进行第二热处理以增强钴化硅化物层的导电性。

59. 发明申请

US20090023289A1 CONDUCTOR REMOVAL PROCESS 有权
标题翻译：导线器拆卸过程
公开(公告)号：US20090023289A1
公开(公告)日：2009-01-22
申请号：US11780024
申请日：2007-07-19
申请人： Yung-Tai Hung , Chin-Tsan Yeh , Chin-Ta Su , Ling-Wu Yang , Tung-Han Chuang
发明人： Yung-Tai Hung , Chin-Tsan Yeh , Chin-Ta Su , Ling-Wu Yang , Tung-Han Chuang
IPC分类号： H01L21/461
CPC分类号： H01L21/3212 , H01L21/32105
摘要： A conductor removal process is described, which is applied to a substrate that has thereon a plurality of patterns and a blanket conductor layer covering the patterns. An upper portion of the blanket conductor layer entirely over the patterns is oxidized to form a dielectric layer. A CMP step is performed to remove the dielectric layer and a portion of the remaining conductor layer in turn and thereby expose the patterns.
摘要翻译：描述了导体去除工艺，其应用于其上具有多个图案的基板和覆盖图案的覆盖层导体层。橡皮布导体层的整个图案上方的上部被氧化以形成电介质层。执行CMP步骤以依次去除电介质层和剩余导体层的一部分，从而暴露图案。

60. 发明申请

US20070128887A1 Spin-on glass passivation process 审中-公开
标题翻译：旋涂玻璃钝化工艺
公开(公告)号：US20070128887A1
公开(公告)日：2007-06-07
申请号：US11295963
申请日：2005-12-07
申请人： Lee-Jen Chen , Chin-Ta Su
发明人： Lee-Jen Chen , Chin-Ta Su
IPC分类号： H01L21/31
CPC分类号： H01L21/316 , H01L21/02126 , H01L21/02216 , H01L21/02282 , H01L21/02304 , H01L21/02362 , H01L21/3122 , H01L21/76801 , H01L21/76829 , H01L21/76834
摘要： Integrated circuits and methods of making an integrated circuit are disclosed. The disclosed methods include providing a substrate having at least one device structure thereon; providing a first barrier layer over the substrate and the at least one device structure; providing a dielectric layer formed by a spin-on-glass process; and providing a second barrier layer over the dielectric layer, wherein the second barrier layer is a compressive layer. Integrated circuits described herein include a first barrier layer over the substrate and the at least one device structure; a dielectric layer formed by a spin-on-glass process; and a second barrier layer over the dielectric layer, wherein the second barrier layer is a compressive layer.
摘要翻译：公开了集成电路和制造集成电路的方法。所公开的方法包括提供其上具有至少一个器件结构的衬底; 在所述衬底和所述至少一个器件结构上提供第一阻挡层; 提供通过旋涂工艺形成的介电层; 以及在所述电介质层上提供第二阻挡层，其中所述第二阻挡层是压缩层。本文描述的集成电路包括衬底上的第一阻挡层和至少一个器件结构; 通过旋涂工艺形成的介电层; 以及在介电层上的第二阻挡层，其中第二阻挡层是压缩层。

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