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51. 发明申请

US20140042446A1 HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME 有权
标题翻译：高电子移动性晶体管及其形成方法
公开(公告)号：US20140042446A1
公开(公告)日：2014-02-13
申请号：US13571169
申请日：2012-08-09
申请人： Chen-Hao Chiang , Han-Chin Chiu , Po-Chun Liu , Chi-Ming Chen , Chung-Yi Yu
发明人： Chen-Hao Chiang , Han-Chin Chiu , Po-Chun Liu , Chi-Ming Chen , Chung-Yi Yu
IPC分类号： H01L29/778 , H01L21/335 , H01L29/20
CPC分类号： H01L29/7784 , H01L29/0891 , H01L29/2003 , H01L29/66462 , H01L29/7787
摘要： A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are in contact with the second III-V compound layer. A n-type doped region underlies each source feature and drain feature in the second III-V compound layer. A p-type doped region underlies each n-type doped region in the first III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the source feature and the drain feature.
摘要翻译：高电子迁移率晶体管（HEMT）包括第一III-V族化合物层。第二III-V化合物层设置在第一III-V化合物层上，并且与组合物中的第一III-V化合物层不同。源特征和漏极特征与第二III-V复合层接触。在第二III-V化合物层中的每个源特征和漏极特征的n型掺杂区域。 p型掺杂区域位于第一III-V化合物层中的每个n型掺杂区域的正下方。栅电极设置在源特征和漏极特征之间的第二III-V化合物层的一部分上。

52. 发明授权

US08629037B2 Forming a protective film on a back side of a silicon wafer in a III-V family fabrication process 有权
标题翻译：在III-V族制造工艺中在硅晶片的背面形成保护膜
公开(公告)号：US08629037B2
公开(公告)日：2014-01-14
申请号：US13244340
申请日：2011-09-24
申请人： Chun-Feng Nieh , Chung-Yi Yu , Hung-Ta Lin
发明人： Chun-Feng Nieh , Chung-Yi Yu , Hung-Ta Lin
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： Provided is a method of fabricating a semiconductor device. The method includes forming a first dielectric layer over a first surface and a second surface of a silicon substrate. the first and second surfaces being opposite surfaces. A first portion of the first dielectric layer covers the first surface of the substrate, and a second portion of the first dielectric layer covers the second surface of the substrate. The method includes forming openings that extend into the substrate from the first surface. The method includes filling the openings with a second dielectric layer. The method includes removing the first portion of the first dielectric layer without removing the second portion of the first dielectric layer.
摘要翻译：提供一种制造半导体器件的方法。该方法包括在硅衬底的第一表面和第二表面上形成第一电介质层。第一和第二表面是相对的表面。第一介电层的第一部分覆盖基板的第一表面，并且第一介电层的第二部分覆盖基板的第二表面。该方法包括形成从第一表面延伸到基底中的开口。该方法包括用第二介电层填充开口。该方法包括在不去除第一介电层的第二部分的情况下去除第一介电层的第一部分。

53. 发明申请

US20140001439A1 Graded Aluminum-Gallium-Nitride and Superlattice Buffer Layer for III-V Nitride Layer on Silicon Substrate 有权
标题翻译：硅衬底上III-V氮化物层的分级铝 - 氮化镓和超晶格缓冲层
公开(公告)号：US20140001439A1
公开(公告)日：2014-01-02
申请号：US13534368
申请日：2012-06-27
申请人： Chi-Ming Chen , Po-Chun Liu , Chung-Yi Yu
发明人： Chi-Ming Chen , Po-Chun Liu , Chung-Yi Yu
IPC分类号： H01L29/205 , H01L21/20
CPC分类号： B82Y10/00 , B82Y40/00 , H01L21/02381 , H01L21/02458 , H01L21/02507 , H01L21/0251 , H01L21/0254 , H01L29/1075 , H01L29/2003 , H01L29/66462 , H01L29/7786
摘要： The present disclosure is directed to an integrated circuit and a method for the fabrication of the integrated circuit. The integrated circuit includes a lattice matching structure. The lattice matching structure can include a first buffer region, a second buffer region and a superlattice structure formed from AlxGa1−xN/AlyGa1−yN layer pairs.
摘要翻译：本公开涉及用于制造集成电路的集成电路和方法。集成电路包括晶格匹配结构。晶格匹配结构可以包括由Al x Ga 1-x N / Al y Ga 1-y N层对形成的第一缓冲区，第二缓冲区和超晶格结构。

54. 发明申请

US20130099283A1 III-V Multi-Channel FinFETs 有权
公开(公告)号：US20130099283A1
公开(公告)日：2013-04-25
申请号：US13278601
申请日：2011-10-21
申请人： Hung-Ta Lin , Chun-Feng Nieh , Chung-Yi Yu , Chi-Ming Chen
发明人： Hung-Ta Lin , Chun-Feng Nieh , Chung-Yi Yu , Chi-Ming Chen
IPC分类号： H01L29/205 , H01L21/20
CPC分类号： H01L29/267 , H01L21/02546 , H01L21/30612 , H01L21/76224 , H01L29/0653 , H01L29/155 , H01L29/205 , H01L29/66462 , H01L29/66522 , H01L29/66795 , H01L29/7783 , H01L29/785
摘要： A device includes insulation regions over portions of a semiconductor substrate, and a III-V compound semiconductor region over top surfaces of the insulation regions, wherein the III-V compound semiconductor region overlaps a region between opposite sidewalls of the insulation regions. The III-V compound semiconductor region includes a first and a second III-V compound semiconductor layer formed of a first III-V compound semiconductor material having a first band gap, and a third III-V compound semiconductor layer formed of a second III-V compound semiconductor material between the first and the second III-V compound semiconductor layers. The second III-V compound semiconductor material has a second band gap lower than the first band gap. A gate dielectric is formed on a sidewall and a top surface of the III-V compound semiconductor region. A gate electrode is formed over the gate dielectric.

55. 发明申请

US20070262364A1 METHOD OF MAKING WAFER STRUCTURE FOR BACKSIDE ILLUMINATED COLOR IMAGE SENSOR 失效
标题翻译：制造背面照明彩色图像传感器的波形结构的方法
公开(公告)号：US20070262364A1
公开(公告)日：2007-11-15
申请号：US11626664
申请日：2007-01-24
申请人： Tzu-Hsuan Hsu , Chris Hsieh , Dun-Nian Yaung , Chung-Yi Yu
发明人： Tzu-Hsuan Hsu , Chris Hsieh , Dun-Nian Yaung , Chung-Yi Yu
IPC分类号： H01L31/113 , H01L31/062
CPC分类号： H01L31/18 , H01L27/1203 , H01L27/1461 , H01L27/14621 , H01L27/14627 , H01L27/1464 , H01L27/14645 , H01L27/14685 , H01L27/14689 , H01L27/148
摘要： A backside illuminated sensor includes a semiconductor substrate having a front surface and a back surface, and a plurality of pixels formed on the front surface of the semiconductor substrate. The sensor further includes a plurality of absorption depths formed within the back surface of the semiconductor substrate. Each of the plurality of absorption depths is arranged according to each of the plurality of pixels. A method for forming a backside illuminated includes providing a semiconductor substrate having a front surface and a back surface and forming a first, second, and third pixel on the front surface of the semiconductor substrate. The method further includes forming a first, second, and third thickness within the back surface of the semiconductor substrate, wherein the first, second, and third thickness lies beneath the first, second, and third pixel, respectively.
摘要翻译：背面照明传感器包括具有前表面和后表面的半导体衬底和形成在半导体衬底的前表面上的多个像素。传感器还包括形成在半导体衬底的后表面内的多个吸收深度。多个吸收深度中的每一个根据多个像素中的每一个排列。用于形成背面照明的方法包括提供具有前表面和后表面的半导体衬底，并在半导体衬底的前表面上形成第一，第二和第三像素。该方法还包括在半导体衬底的后表面内形成第一，第二和第三厚度，其中第一，第二和第三厚度分别位于第一，第二和第三像素之下。

56. 发明授权

US07153744B2 Method of forming self-aligned poly for embedded flash 有权
标题翻译：用于嵌入式闪光灯的自对准聚酰亚胺的方法
公开(公告)号：US07153744B2
公开(公告)日：2006-12-26
申请号：US10822505
申请日：2004-04-12
申请人： Han-Ping Chen , Chung-Yi Yu
发明人： Han-Ping Chen , Chung-Yi Yu
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11521 , H01L27/11534 , H01L27/1203 , H01L29/42324 , H01L29/7885
摘要： A method of manufacturing a microelectronic device including, in one embodiment, providing a substrate having a plurality of partially completed microelectronic devices including at least one partially completed memory device and at least one partially completed transistor. At least a portion of the partially completed transistor is protected by forming a first layer over the portion of the partially completed transistor to be protected during a subsequent material removal step. A second layer is formed substantially covering the partially completed memory device and the partially completed transistor. Portions of the second layer are removed leaving a portion of the second layer over the partially completed memory device. At least a substantial portion of the first layer is removed from the partially completed transistor after the portions of the second layer are removed.
摘要翻译：一种制造微电子器件的方法，在一个实施例中包括提供具有多个部分完成的微电子器件的衬底，所述微电子器件包括至少一个部分完成的存储器件和至少一个部分完成的晶体管。通过在随后的材料去除步骤期间在待保护的部分完成的晶体管的部分上形成第一层来保护部分完成的晶体管的至少一部分。形成基本覆盖部分完成的存储器件和部分完成的晶体管的第二层。去除第二层的部分，留下部分完成的存储器件上的第二层的一部分。在去除第二层的部分之后，第一层的至少大部分被从部分完成的晶体管中去除。

57. 发明申请

US20060014314A1 Image sensor with light guides 有权
标题翻译：带导光板的图像传感器
公开(公告)号：US20060014314A1
公开(公告)日：2006-01-19
申请号：US11229655
申请日：2005-09-20
申请人： Dun-Nian Yaung , Chung-Yi Yu
发明人： Dun-Nian Yaung , Chung-Yi Yu
IPC分类号： H01L21/00
CPC分类号： H01L27/14685 , H01L27/1462 , H01L27/14623 , H01L27/14625
摘要： An image sensor device and fabrication method thereof. An image sensing array is formed in a substrate, wherein the image sensing array comprises a plurality of photosensors with spaces therebetween. A first dielectric layer with a first refractive index is formed overlying the spaces but not the photosensors. A conformal second dielectric layer with a second refractive index is formed on a sidewall of the first dielectric layer. A third dielectric layer with a third refractive index is formed overlying the photosensors but not the spaces. The third refractive index is greater than the second refractive index. A light guide constructed by the second and third dielectric layers is formed overlying each photosensor, thereby preventing incident light from striking other photosensors.
摘要翻译：一种图像传感器装置及其制造方法。图像感测阵列形成在基板中，其中图像感测阵列包括在其间具有间隔的多个光电传感器。具有第一折射率的第一介电层形成在空间上而不是光电传感器上。在第一介电层的侧壁上形成具有第二折射率的共形的第二介电层。形成具有第三折射率的第三介电层，覆盖光电传感器而不是空间。第三折射率大于第二折射率。由第二和第三电介质层构成的导光体形成在每个光电传感器上，从而防止入射光撞击其他感光体。

58. 发明授权

US08629013B2 Junction leakage reduction through implantation 有权
标题翻译：通过植入减少结漏电
公开(公告)号：US08629013B2
公开(公告)日：2014-01-14
申请号：US13273463
申请日：2011-10-14
申请人： Chun-Feng Nieh , Chung-Yi Yu , Hung-Ta Lin
发明人： Chun-Feng Nieh , Chung-Yi Yu , Hung-Ta Lin
IPC分类号： H01L21/338
CPC分类号： H01L29/66522 , H01L21/2654 , H01L29/267
摘要： Provided is a method of fabricating a semiconductor device. The method includes forming a first III-V family layer over a substrate. The first III-V family layer includes a surface having a first surface morphology. The method includes performing an ion implantation process to the first III-V family layer through the surface. The ion implantation process changes the first surface morphology into a second surface morphology. After the ion implantation process is performed, the method includes forming a second III-V family layer over the first III-V family layer. The second III-V family layer has a material composition different from that of the first III-V family layer.
摘要翻译：提供一种制造半导体器件的方法。该方法包括在衬底上形成第一III-V族层。第一III-V族层包括具有第一表面形态的表面。该方法包括通过表面对第一III-V族层执行离子注入工艺。离子注入工艺将第一表面形态变为第二表面形态。在执行离子注入工艺之后，该方法包括在第一III-V族层上形成第二III-V族层。第二III-V族层具有不同于第一III-V族层的材料组成。

59. 发明申请

US20070241386A1 Method for reducing topography of non-volatile memory and resulting memory cells 有权
标题翻译：减少非易失性存储器和结果存储单元的形貌的方法
公开(公告)号：US20070241386A1
公开(公告)日：2007-10-18
申请号：US11716164
申请日：2007-03-09
申请人： Shih Wei Wang , Derek Lin , Chen-Ming Huang , Chang-Jen Hsieh , Chi-Hsin Lo , Chung-Yi Yu , Feng-Jia Shiu , Yeur-Luen Tu , Yi-Shin Chu , Jen-Sheng Yang
发明人： Shih Wei Wang , Derek Lin , Chen-Ming Huang , Chang-Jen Hsieh , Chi-Hsin Lo , Chung-Yi Yu , Feng-Jia Shiu , Yeur-Luen Tu , Yi-Shin Chu , Jen-Sheng Yang
IPC分类号： H01L29/76
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11521 , H01L27/11526 , H01L27/11573
摘要： A method for forming a semiconductor structure includes providing a substrate; forming a gate stack of a flash memory cell, wherein a top portion of the gate stack comprises a capping layer; forming a gate having at least a portion over the capping layer; and reducing a thickness of the portion of the gate over the capping layer. The topography height difference between the flash memory cell and MOS devices on the same chip is reduced.
摘要翻译：一种形成半导体结构的方法包括：提供衬底; 形成闪存单元的栅极堆叠，其中所述栅极堆叠的顶部部分包括覆盖层; 形成具有覆盖层上方的至少一部分的栅极; 并且在所述封盖层上减小所述栅极的所述部分的厚度。闪存单元和同一芯片上的MOS器件之间的地形高差减小。

60. 发明申请

US20060186547A1 Light shield for CMOS imager 有权
公开(公告)号：US20060186547A1
公开(公告)日：2006-08-24
申请号：US11066432
申请日：2005-02-24
申请人： Wen-De Wang , Dun-Nian Yaung , Shou-Gwo Wuu , Chung-Yi Yu
发明人： Wen-De Wang , Dun-Nian Yaung , Shou-Gwo Wuu , Chung-Yi Yu
IPC分类号： H01L23/52
CPC分类号： H01L27/14654 , H01L27/14623 , H01L27/14636 , H01L2924/0002 , H01L2924/00
摘要： System and method for providing a light shield for a CMOS imager is provided. The light shield comprises a structure formed above a point between a photo-sensitive element and adjacent circuitry. The structure is formed of a light-blocking material, such as a metal, metal alloy, metal compound, or the like, formed in dielectric layers over the photo-sensitive elements.

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