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51. 发明申请

US20110201138A1 MASK VERIFYING METHOD, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM PRODUCT 有权
标题翻译：掩模验证方法，半导体器件的制造方法和计算机程序产品
公开(公告)号：US20110201138A1
公开(公告)日：2011-08-18
申请号：US13024604
申请日：2011-02-10
申请人： Shigeki Nojima , Tetsuaki Matsunawa , Shigeru Hasebe , Masahiro Miyairi
发明人： Shigeki Nojima , Tetsuaki Matsunawa , Shigeru Hasebe , Masahiro Miyairi
IPC分类号： H01L21/66 , G06F17/50
CPC分类号： G03F1/36 , H01L22/12 , H01L22/20
摘要： According to a mask verifying method of the embodiment, a difference between an actual dimension of a mask pattern and a simulation dimension is calculated as a computational estimated value. Moreover, a difference between an actual dimension of the mask pattern that is actually measured and a dimension on pattern data is calculated as an actually-measured difference. Then, it is verified whether a mask pattern dimension passes or fails based on the calculated value. When calculating the computational estimated value, a model function, which is set based on each correspondence relationship between an actual dimension and a mask simulation dimension of a test pattern, which includes a plurality of types of pattern ambient environments, to the mask pattern.
摘要翻译：根据本实施例的掩模验证方法，计算掩模图案的实际尺寸与模拟尺寸之间的差异作为计算估计值。此外，将实际测量的掩模图案的实际尺寸与图案数据上的尺寸之间的差计算为实际测量的差。然后，根据计算值验证掩模图案尺寸是否通过或失败。当计算计算估计值时，将基于包括多种图案环境环境的测试图案的实际尺寸和掩模模拟尺寸之间的每个对应关系设置的模型函数提供给掩模图案。

52. 发明授权

US07895541B2 Semiconductor integrated circuit pattern verification method, photomask manufacturing method, semiconductor integrated circuit device manufacturing method, and program for implementing semiconductor integrated circuit pattern verification method 有权
标题翻译：半导体集成电路图案验证方法，光掩模制造方法，半导体集成电路器件制造方法以及用于实现半导体集成电路图案验证方法的程序
公开(公告)号：US07895541B2
公开(公告)日：2011-02-22
申请号：US11901030
申请日：2007-09-14
申请人： Shigeki Nojima
发明人： Shigeki Nojima
IPC分类号： G06F17/50
CPC分类号： G06T7/001 , G03F1/36 , G06F17/5081 , G06T2207/30148
摘要： A semiconductor integrated circuit pattern verification method includes executing simulation to obtain a simulation pattern to be formed on a substrate on the basis of a semiconductor integrated circuit design pattern, comparing the simulation pattern and the design pattern that is required on the substrate to detect a first difference value, extracting error candidates at which the first difference value is not less than a first predetermined value, comparing pattern shapes at the error candidates to detect a second difference value, combining, into one group, patterns whose second difference values are not more than a second predetermined value, and extracting a predetermined number of patterns from each group and verifying error candidates of the extracted patterns.
摘要翻译：半导体集成电路图案验证方法包括执行模拟，以基于半导体集成电路设计图案获得要在基板上形成的模拟图案，比较基板上所需的模拟图案和设计图案，以检测第一差分值，提取第一差值不小于第一预定值的错误候选，比较错误候选的图案形状以检测第二差值，将第二差值不大于第二预定值，并且从每个组提取预定数量的模式并验证提取的模式的错误候选。

53. 发明授权

US07008731B2 Method of manufacturing a photomask and method of manufacturing a semiconductor device using the photomask 有权
公开(公告)号：US07008731B2
公开(公告)日：2006-03-07
申请号：US10374094
申请日：2003-02-27
申请人： Shigeki Nojima , Osamu Ikenaga
发明人： Shigeki Nojima , Osamu Ikenaga
IPC分类号： G03F9/00 , G03C5/00
CPC分类号： G03F1/84 , G03F7/705 , G03F7/70625
摘要： A method of manufacturing a photomask includes determining dimensions of a pattern in a photomask, determining an exposure latitude on the basis of the dimensions of the mask, and judging if the photomask is defective or non-defective on the basis of whether or not the exposure latitude falls within a prescribed exposure latitude. The pattern in the photomask includes dimensions of critical pattern portions in which an exposure latitude is low.

54. 发明授权

US08336004B2 Dimension assurance of mask using plurality of types of pattern ambient environment 有权
标题翻译：使用多种图案周边环境的面膜尺寸保证
公开(公告)号：US08336004B2
公开(公告)日：2012-12-18
申请号：US13024604
申请日：2011-02-10
申请人： Shigeki Nojima , Tetsuaki Matsunawa , Shigeru Hasebe , Masahiro Miyairi
发明人： Shigeki Nojima , Tetsuaki Matsunawa , Shigeru Hasebe , Masahiro Miyairi
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , H01L22/12 , H01L22/20
摘要： According to a mask verifying method of the embodiment, a difference between an actual dimension of a mask pattern and a simulation dimension is calculated as a computational estimated value. Moreover, a difference between an actual dimension of the mask pattern that is actually measured and a dimension on pattern data is calculated as an actually-measured difference. Then, it is verified whether a mask pattern dimension passes or fails based on the calculated value. When calculating the computational estimated value, a model function, which is set based on each correspondence relationship between an actual dimension and a mask simulation dimension of a test pattern, which includes a plurality of types of pattern ambient environments, to the mask pattern.
摘要翻译：根据本实施例的掩模验证方法，计算掩模图案的实际尺寸与模拟尺寸之间的差异作为计算估计值。此外，将实际测量的掩模图案的实际尺寸与图案数据上的尺寸之间的差计算为实际测量的差。然后，根据计算值验证掩模图案尺寸是否通过或失败。当计算计算估计值时，将基于包括多种图案环境环境的测试图案的实际尺寸和掩模模拟尺寸之间的每个对应关系设置的模型函数提供给掩模图案。

55. 发明申请

US20110175247A1 SEMICONDUCTOR INTEGRATED CIRCUIT PATTERN VERIFICATION METHOD, PHOTOMASK MANUFACTURING METHOD, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE MANUFACTURING METHOD, AND PROGRAM FOR IMPLEMENTING SEMICONDUCTOR INTEGRATED CIRCUIT PATTERN VERIFICATION METHOD 有权
标题翻译：半导体集成电路图形验证方法，光电二极管制造方法，半导体集成电路设备制造方法和实现半导体集成电路图形验证方法的程序
公开(公告)号：US20110175247A1
公开(公告)日：2011-07-21
申请号：US13010130
申请日：2011-01-20
申请人： Shigeki Nojima
发明人： Shigeki Nojima
IPC分类号： H01L21/66
CPC分类号： G06T7/001 , G03F1/36 , G06F17/5081 , G06T2207/30148
摘要： A semiconductor integrated circuit pattern verification method includes executing simulation to obtain a simulation pattern to be formed on a substrate on the basis of a semiconductor integrated circuit design pattern, comparing the simulation pattern and the design pattern that is required on the substrate to detect a first difference value, extracting error candidates at which the first difference value is not less than a first predetermined value, comparing pattern shapes at the error candidates to detect a second difference value, combining, into one group, patterns whose second difference values are not more than a second predetermined value, and extracting a predetermined number of patterns from each group and verifying error candidates of the extracted patterns.
摘要翻译：半导体集成电路图案验证方法包括执行模拟，以基于半导体集成电路设计图案获得要在基板上形成的模拟图案，比较基板上所需的模拟图案和设计图案，以检测第一差分值，提取第一差值不小于第一预定值的错误候选，比较错误候选的图案形状以检测第二差值，将第二差值不大于第二预定值，并且从每个组提取预定数量的模式并验证提取的模式的错误候选。

56. 发明授权

US07730445B2 Pattern data verification method for semiconductor device, computer-readable recording medium having pattern data verification program for semiconductor device recorded, and semiconductor device manufacturing method 失效
标题翻译：用于半导体器件的图案数据验证方法，具有用于半导体器件的图案数据验证程序的计算机可读记录介质和半导体器件制造方法
公开(公告)号：US07730445B2
公开(公告)日：2010-06-01
申请号：US11798725
申请日：2007-05-16
申请人： Shigeki Nojima
发明人： Shigeki Nojima
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A pattern data verification method for a semiconductor device, including extracting, from design data, design data corresponding to an edge portion of a mask pattern to obtain an edge portion of a pattern on a substrate to be processed, when the pattern is obtained on the substrate to be processed by using at least two masks each having the mask pattern corresponding to the design data, setting allowable errors with respect to the extracted design data and the design data which is not extracted, respectively, calculating a pattern formed on the substrate to be processed by using at least one mask by process simulation, and comparing an error between the pattern calculated by the simulation and the design data with the allowable error set for the design data.
摘要翻译：一种用于半导体器件的图案数据验证方法，包括从设计数据中提取与掩模图案的边缘部分相对应的设计数据，以获得待处理的基板上的图案的边缘部分，通过使用至少两个具有对应于设计数据的掩模图案的掩模来处理的基板，分别设置相对于所提取的设计数据和未提取的设计数据的允许误差，计算在基板上形成的图案，通过过程模拟使用至少一个掩模进行处理，并将由仿真计算的图案与设计数据之间的误差与设计数据的容许误差进行比较。

57. 发明授权

US07600213B2 Pattern data verification method, pattern data creation method, exposure mask manufacturing method, semiconductor device manufacturing method, and computer program product 有权
标题翻译：图案数据验证方法，图案数据生成方法，曝光掩模制造方法，半导体器件制造方法和计算机程序产品
公开(公告)号：US07600213B2
公开(公告)日：2009-10-06
申请号：US11287205
申请日：2005-11-28
申请人： Shigeki Nojima , Akira Hamaguchi
发明人： Shigeki Nojima , Akira Hamaguchi
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A pattern data verification method includes preparing exposure data related to a circuit pattern to be formed on a substrate, calculating a characteristic of an image of an exposure pattern on a resist film to be applied on the substrate, the exposure pattern corresponding to the exposure data, calculating a film thickness of the resist film after being developed based on the characteristic of the image of the exposure pattern, and determining whether the exposure data is acceptable or rejectable based on the film thickness of the resist film after being developed.
摘要翻译：模式数据验证方法包括：准备与要在基板上形成的电路图案有关的曝光数据，计算要施加在基板上的抗蚀剂膜上的曝光图案的图像的特性，对应于曝光数据的曝光图案基于曝光图案的图像的特性，计算显影后的抗蚀剂膜的膜厚度，并且基于显影后的抗蚀剂膜的膜厚确定曝光数据是否可接受或可否认。

58. 发明申请

US20080022244A1 Semiconductor integrated circuit pattern verification method, photomask manufacturing method, semiconductor integrated circuit device manufacturing method, and program for implementing semiconductor integrated circuit pattern verification method 有权
标题翻译：半导体集成电路图案验证方法，光掩模制造方法，半导体集成电路器件制造方法以及用于实现半导体集成电路图案验证方法的程序
公开(公告)号：US20080022244A1
公开(公告)日：2008-01-24
申请号：US11901030
申请日：2007-09-14
申请人： Shigeki Nojima
发明人： Shigeki Nojima
IPC分类号： G06F17/50
CPC分类号： G06T7/001 , G03F1/36 , G06F17/5081 , G06T2207/30148
摘要： A semiconductor integrated circuit pattern verification method includes executing simulation to obtain a simulation pattern to be formed on a substrate on the basis of a semiconductor integrated circuit design pattern, comparing the simulation pattern and the design pattern that is required on the substrate to detect a first difference value, extracting error candidates at which the first difference value is not less than a first predetermined value, comparing pattern shapes at the error candidates to detect a second difference value, combining, into one group, patterns whose second difference values are not more than a second predetermined value, and extracting a predetermined number of patterns from each group and verifying error candidates of the extracted patterns.
摘要翻译：半导体集成电路图案验证方法包括执行模拟，以基于半导体集成电路设计图案获得要在基板上形成的模拟图案，比较基板上所需的模拟图案和设计图案，以检测第一差分值，提取第一差值不小于第一预定值的错误候选，比较错误候选的图案形状以检测第二差值，将第二差值不大于第二预定值，并且从每个组提取预定数量的模式并验证提取的模式的错误候选。

59. 发明授权

US07278125B2 Semiconductor integrated circuit pattern verification method, photomask manufacturing method, semiconductor integrated circuit device manufacturing method, and program for implementing semiconductor integrated circuit pattern verification method 有权
标题翻译：半导体集成电路图案验证方法，光掩模制造方法，半导体集成电路器件制造方法以及用于实现半导体集成电路图案验证方法的程序
公开(公告)号：US07278125B2
公开(公告)日：2007-10-02
申请号：US11176181
申请日：2005-07-08
申请人： Shigeki Nojima
发明人： Shigeki Nojima
IPC分类号： G06F17/50
CPC分类号： G06T7/001 , G03F1/36 , G06F17/5081 , G06T2207/30148
摘要： A semiconductor integrated circuit pattern verification method includes executing simulation to obtain a simulation pattern to be formed on a substrate on the basis of a semiconductor integrated circuit design pattern, comparing the simulation pattern and the design pattern that is required on the substrate to detect a first difference value, extracting error candidates at which the first difference value is not less than a first predetermined value, comparing pattern shapes at the error candidates to detect a second difference value, combining, into one group, patterns whose second difference values are not more than a second predetermined value, and extracting a predetermined number of patterns from each group and verifying error candidates of the extracted patterns.
摘要翻译：半导体集成电路图案验证方法包括执行模拟，以基于半导体集成电路设计图案获得要在基板上形成的模拟图案，比较基板上所需的模拟图案和设计图案，以检测第一差分值，提取第一差值不小于第一预定值的错误候选，比较错误候选的图案形状以检测第二差值，将第二差值不大于第二预定值，并且从每个组提取预定数量的模式并验证提取的模式的错误候选。

60. 发明授权

US07229721B2 Method for evaluating photo mask and method for manufacturing semiconductor device 失效
标题翻译：评估光掩膜的方法和制造半导体器件的方法
公开(公告)号：US07229721B2
公开(公告)日：2007-06-12
申请号：US10705954
申请日：2003-11-13
申请人： Shoji Mimotogi , Shigeki Nojima , Osamu Ikenaga
发明人： Shoji Mimotogi , Shigeki Nojima , Osamu Ikenaga
IPC分类号： G03F1/00
CPC分类号： G03F7/70625 , G03F1/44 , G03F1/68 , G03F1/78 , G03F7/705
摘要： A method for evaluating a photo mask comprises preparing a photo mask including a unit drawing pattern, finding a dimensional variation relating to the photo mask, the dimensional variation including first and second dimensional variations, the first dimensional variation occurring due to a positional displacement and size mismatch of the unit drawing pattern in the photo mask and the second dimensional variation occurring due to etching and development relating to a manufacturing of the photo mask, estimating a deteriorated amount of an exposure latitude occurring due to the dimensional variation of the photo mask using the dimensional variation and a degree of influence of the dimensional variation for the exposure latitude, and judging quality of the photo mask by comparing the deteriorated amount of the exposure latitude and an allowable deteriorated amount of the exposure latitude.
摘要翻译：一种用于评估光掩模的方法包括制备包括单元绘图图案的光掩模，找到与光掩模相关的尺寸变化，包括第一和第二尺寸变化的尺寸变化，由于位置偏移和尺寸而发生的第一尺寸变化光掩模中的单位绘图图案的不匹配以及由于与光掩模的制造相关的蚀刻和显影而发生的第二尺寸变化，估计由于光掩膜的尺寸变化而产生的曝光宽容度的恶化量，通过比较曝光宽容度的劣化量和曝光宽容度的允许恶化量来判断曝光宽容度的尺寸变化和影响程度，以及判断光掩模的质量。

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