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51. 发明授权

US06291877B1 Flexible IC chip between flexible substrates 失效
标题翻译：柔性基板之间的柔性IC芯片
公开(公告)号：US06291877B1
公开(公告)日：2001-09-18
申请号：US09542296
申请日：2000-04-04
申请人： Mitsuo Usami , Takashi Tase
发明人： Mitsuo Usami , Takashi Tase
IPC分类号： H01L2302
CPC分类号： G06K19/07728 , G06K19/077 , G06K19/07749 , H01L21/6835 , H01L23/49855 , H01L23/5388 , H01L23/5389 , H01L23/562 , H01L24/24 , H01L24/45 , H01L24/48 , H01L24/82 , H01L2221/6835 , H01L2221/68354 , H01L2221/68359 , H01L2224/24051 , H01L2224/24225 , H01L2224/24226 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/3511 , H01L2924/00 , H01L2224/05599
摘要： A thin-film semiconductor device comprising at least a semiconductor element and a wiring is disclosed. A thin film of a protective insulating material is formed on the lower surface of the semiconductor element, and a substrate is bonded on the lower surface of the thin film. A method for fabricating the thin-film semiconductor device is also disclosed, in which a thin-film semiconductor circuit is formed on a silicon-on-insulator wafer, the silicon substrate on the reverse side of the silicon-on-insulator wafer is etched off, a thin-film semiconductor chip is formed and attached to the substrate, and the thin-film semi conductor chip and the substrate are wired to each other by printing.
摘要翻译：公开了至少包括半导体元件和布线的薄膜半导体器件。在半导体元件的下表面上形成保护性绝缘材料的薄膜，并且在薄膜的下表面上接合基板。还公开了一种制造薄膜半导体器件的方法，其中在绝缘体上硅晶片上形成薄膜半导体电路，蚀刻绝缘体上硅晶片背面的硅衬底关闭，形成薄膜半导体芯片并将其附着到基板上，并且通过印刷将薄膜半导体芯片和基板彼此布线。

52. 发明授权

US5909052A Semiconductor device having plural chips with the sides of the chips in face-to-face contact with each other in the same crystal plane 失效
标题翻译：具有多个芯片的半导体器件，其芯片的侧面在相同的晶面内彼此面对面地接触
公开(公告)号：US5909052A
公开(公告)日：1999-06-01
申请号：US449722
申请日：1995-05-24
申请人： Hiroyuki Ohta , Hideo Miura , Mitsuo Usami , Masatsugu Kametani , Munetoshi Zen , Noriaki Okamoto
发明人： Hiroyuki Ohta , Hideo Miura , Mitsuo Usami , Masatsugu Kametani , Munetoshi Zen , Noriaki Okamoto
IPC分类号： G06F9/38 , G06F15/167 , H01L21/98 , H01L25/065 , H01L29/06 , H01L29/04
CPC分类号： G06F9/3879 , G06F15/167 , G06F9/3877 , H01L24/24 , H01L24/82 , H01L25/0652 , H01L25/0655 , H01L25/50 , H01L2223/54426 , H01L2224/24137 , H01L2224/24225 , H01L2224/24227 , H01L2224/95136 , H01L29/0657 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/04953 , H01L2924/10157 , H01L2924/10158 , H01L2924/10329 , H01L2924/12042 , H01L2924/12043 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/351
摘要： Prevention of reduction in the production yield due to the increase in the area of a semiconductor chip permits a sophisticated-performance single-chip semiconductor device to be fabricated. This also permits a many-kind small-amount production of semiconductor devices to be implemented. After plural semiconductor chips 2 and 3 are fabricated separately, only defect-free chips of them are selected. The selected defect-free chips are connected in contact between their side walls of their densest faces of atoms of their substrates so that the surfaces 4a and 4b where elements are to be formed are located in the same plane. Thus, even when the chip area is increased, reduction of the production yield can be prevented, thereby permitting a large-area sophisticated-performance single chip semiconductor device to be fabricated. If many kinds of semiconductor chips are prepared and connected in their combination in a variety of forms, it is possible to realize a many-kind small-amount production of semiconductor devices.
摘要翻译：由于半导体芯片面积的增加，防止生产成品率的下降，可以制造精密性能的单芯片半导体器件。这也允许实现多种少量的半导体器件的生产。在单独制造多个半导体芯片2和3之后，仅选择它们的无缺陷芯片。所选择的无缺陷芯片在它们的基板的最密实面的侧壁之间接触连接，使得要形成元件的表面4a和4b位于同一平面中。因此，即使在芯片面积增加的情况下，也可以防止生产成品率的降低，从而可以制造大面积复杂性能的单芯片半导体器件。如果准备多种半导体芯片并以各种形式组合连接，则可以实现多种少量的半导体器件的制造。

53. 发明授权

US5298802A Semiconductor integrated circuit device with a plurality of logic circuits having active pull-down functions 失效
标题翻译：具有多个具有主动下拉功能的逻辑电路的半导体集成电路器件
公开(公告)号：US5298802A
公开(公告)日：1994-03-29
申请号：US56798
申请日：1993-05-03
申请人： Mitsuo Usami , Noboru Shiozawa , Toshio Yamada , Hiromasa Katoh , Kazuyoshi Satoh , Tohru Kobayashi , Tatsuya Kimura , Masato Hamamoto , Atsushi Shimizu , Kaoru Koyu
发明人： Mitsuo Usami , Noboru Shiozawa , Toshio Yamada , Hiromasa Katoh , Kazuyoshi Satoh , Tohru Kobayashi , Tatsuya Kimura , Masato Hamamoto , Atsushi Shimizu , Kaoru Koyu
IPC分类号： H03K3/2885 , H03K17/0412 , H03K17/66 , H03K19/013 , H03K19/086
CPC分类号： H03K19/086 , H03K17/04126 , H03K17/666 , H03K19/0136 , H03K3/2885
摘要： In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element. The signal received by the active pull-down transistor has a phase reverse to that of the input signal supplied to the base of said output transistor. Between the base and emitter of the active pull-down transistor, there is disposed a bias circuit formed of a transistor receiving at its base a predetermined bias voltage and an emitter resistor. Further, between a junction point of the emitter follower output transistor and the active pull-down transistor and the emitter of the transistor as a constituent of the bias circuit, there is disposed a capacitance element for feeding back the output signal.
摘要翻译：根据本发明的一个方面，提供一种半导体集成电路，其中输入电路由具有从集电极输出反相输出的双极晶体管和来自发射极的非反相输出的相位分离电路形成。射极跟随器输出电路由相位分离电路的反相输出驱动。同时，射极跟随器输出电路的发射极负载由晶体管形成，并且发射极负载晶体管由相分离的非反相输出的上升沿的待充电电容的充电电流导通地临时驱动电路。作为本发明的第二方面，逻辑电路由逻辑部分和输出部分组成。输出部分包括接收由逻辑部分产生的输出信号的射极跟随器输出晶体管和有源下拉晶体管，在其底部接收通过电容元件提供给它的信号。由有源下拉晶体管接收的信号与提供给所述输出晶体管的基极的输入信号的相位相反。在有源下拉晶体管的基极和发射极之间设置偏置电路，该偏置电路由其基极接收预定偏置电压的晶体管和发射极电阻构成。此外，在射极跟随器输出晶体管的连接点和有源下拉晶体管和作为偏置电路的组成部分的晶体管的发射极之间，设置有用于反馈输出信号的电容元件。

54. 发明授权

US5283480A Semiconductor integrated circuit device with a plurality of logic circuits having active pull-down functions 失效
公开(公告)号：US5283480A
公开(公告)日：1994-02-01
申请号：US557109
申请日：1990-07-25
申请人： Mitsuo Usami , Noboru Shiozawa , Toshio Yamada , Hiromasa Katoh , Kazuyoshi Satoh , Tohru Kobayashi , Tatsuya Kimura , Masato Hamamoto , Atsushi Shimizu , Kaoru Koyu
发明人： Mitsuo Usami , Noboru Shiozawa , Toshio Yamada , Hiromasa Katoh , Kazuyoshi Satoh , Tohru Kobayashi , Tatsuya Kimura , Masato Hamamoto , Atsushi Shimizu , Kaoru Koyu
IPC分类号： H03K3/2885 , H03K17/0412 , H03K17/66 , H03K19/013 , H03K19/086
CPC分类号： H03K19/086 , H03K17/04126 , H03K17/666 , H03K19/0136 , H03K3/2885
摘要： In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element. The signal received by the active pull-down transistor has a phase reverse to that of the input signal supplied to the base of said output transistor. Between the base and emitter of the active pull-down transistor, there is disposed a bias circuit formed of a transistor receiving at its base a predetermined bias voltage and an emitter resistor. Further, between a junction point of the emitter follower output transistor and the active pull-down transistor and the emitter of the transistor as a constituent of the bias circuit, there is disposed a capacitance element for feeding back the output signal.

55. 发明授权

US5208178A Manufacturing a semiconductor integrated circuit device having on chip logic correction 失效
标题翻译：制造具有片上逻辑校正的半导体集成电路器件
公开(公告)号：US5208178A
公开(公告)日：1993-05-04
申请号：US738570
申请日：1991-07-31
申请人： Mitsuo Usami
发明人： Mitsuo Usami
IPC分类号： G01R31/3185 , G11C29/00 , H01L27/02
CPC分类号： G01R31/318505 , G11C29/006 , H01L27/0207
摘要： The present invention relates to a logic correction for a random logic IC of a high integration density, and more particularly to an on-chip logic correction method wherein the upper surface of a chip is divided into a large number of macrocells, testing of the macrocells is made and each defective macrocell is corrected by replacement. Testing is performed after a primary wiring process that connects semiconductor elements into macrocells but before a secondary wiring process interconnecting the macrocells. After the testing, defective macrocells are replaced, and thereafter the secondary wiring process is performed. Testing is performed using testing pads in each macrocell, connected to the main circuit portion of the macrocell through shift register circuit portions. The macrocells are arranged in a lattice pattern. Wirings formed in the secondary wiring process have a larger cross-sectional area than wirings formed in the primary wiring process.
摘要翻译：本发明涉及高积分密度的随机逻辑IC的逻辑校正，更具体地说，涉及一种片上逻辑校正方法，其中芯片的上表面被划分成大量的宏单元，宏单元的测试并且通过更换来校正每个有缺陷的宏单元。在将半导体元件连接到宏单元之后但在将宏单元互连的次级布线处理之间的主要布线处理之后执行测试。在测试之后，更换有缺陷的宏单元，然后进行二次布线处理。使用每个宏单元中的测试焊盘进行测试，通过移位寄存器电路部分连接到宏单元的主电路部分。宏单元被布置成格子图案。在二次布线工艺中形成的布线具有比在主布线工艺中形成的布线更大的横截面面积。

56. 发明授权

US5206546A Logic circuit including variable impedance means 失效
标题翻译：逻辑电路包括可变阻抗装置
公开(公告)号：US5206546A
公开(公告)日：1993-04-27
申请号：US739195
申请日：1991-08-01
申请人： Mitsuo Usami
发明人： Mitsuo Usami
IPC分类号： H03K19/013 , H03K19/0944
CPC分类号： H03K19/09448 , H03K19/0136
摘要： A SPL (or Super Push-pull Logic) circuit is provided which includes: a first variable resistor circuit connected between the collector of an input transistor and a first supply voltage terminal (GND) a second variable resistor circuit connected between the emitter of the input transistor and a second supply voltage terminal (V.sub.EE) and a push-pull output circuit. The second variable resistor circuit includes an N-channel MOSFET which has its gate electrode made receptive of any of the output signals of the SPL circuit, a differentiated signal of the output signal, and an inverted signal of the input signal.
摘要翻译：提供了一种SPL（或超级推挽逻辑）电路，其包括：连接在输入晶体管的集电极和第一电源电压端（GND）之间的第一可变电阻电路，连接在输入端的发射极之间的第二可变电阻电路晶体管和第二电源电压端子（VEE）和推挽输出电路。第二可变电阻电路包括一个N沟道MOSFET，其栅电极接受SPL电路的任何输出信号，输出信号的微分信号和输入信号的反相信号。

57. 发明授权

US07692545B2 Wireless IC tag and process for manufacturing the same 失效
标题翻译：无线IC标签及其制造工艺
公开(公告)号：US07692545B2
公开(公告)日：2010-04-06
申请号：US11596111
申请日：2004-05-18
申请人： Mitsuo Usami
发明人： Mitsuo Usami
IPC分类号： G08B13/14
CPC分类号： H01Q9/16 , G06K19/0775 , H01L2224/16225 , H01L2224/16227 , H01L2924/07811 , H01Q1/22 , H01L2924/00
摘要： There is a problem related to radio wave interference, e.g. the shade of radio wave of a radio IC tag, when a plurality of radio IC tags are present in a region of electromagnetic wave. When a plurality of antennas each having a large area are present in the vicinity of the radio IC tag, the radio IC tag easily receives the affect of an antenna conductor. In a plurality of radio IC tags present in a radio wave area, width of the antenna conductor of the radio IC tag is set at 1.0 mm or less. Furthermore, in order to realize an antenna conductor having a small width, an IC tag chip of both side electrode structure having electrodes on the front surface and rear surface of a chip is sandwiched between antennas.
摘要翻译：存在与无线电波干扰有关的问题，例如，当多个无线电IC标签存在于电磁波区域时，无线电IC标签的无线电波的阴影。当在无线IC标签附近存在各自具有大面积的多个天线时，无线IC标签易于接收天线导体的影响。在无线电波区域中存在的多个无线电IC标签中，将无线IC标签的天线导体的宽度设定为1.0mm以下。此外，为了实现宽度窄的天线导体，在天线之间夹有在芯片的前表面和背面具有电极的两侧电极结构的IC标签芯片。

58. 发明申请

US20090146794A1 READING METHOD, RESPONDER, AND INTERROGATOR 失效
标题翻译：读取方法，响应者和INTERROGATOR
公开(公告)号：US20090146794A1
公开(公告)日：2009-06-11
申请号：US12370263
申请日：2009-02-12
申请人： Mitsuo Usami
发明人： Mitsuo Usami
IPC分类号： H04Q5/22 , G08B13/14
CPC分类号： G06K7/0008 , G06K7/10039 , G06K19/0723
摘要： Transmission and reception of the identification number to/from an interrogator includes an interrogator that reads a recognition number from a responder by radio. When a clock pulse is modulated on a high-frequency carrier and transmitted to the responder from the antenna of the interrogator, there are a first case when the clock pulse interval is short and a second case when the clock pulse interval is long. By combining the clock pulse of the first case and the clock pulse of the second case so as to control the read of the recognition number from the interrogator, it is possible to realize reduction of the semiconductor chip size of the responder and suppress the cost of the semiconductor chip
摘要翻译：向/从询问器发送和接收识别号码包括通过无线电从应答器读取识别号码的询问器。当在高频载波上调制时钟脉冲并从询问器的天线发送到应答器时，存在时钟脉冲间隔短的第一种情况，当时钟脉冲间隔较长时，存在第二种情况。通过组合第一种情况的时钟脉冲和第二种情况下的时钟脉冲，以便控制来自询问器的识别号码的读取，可以实现响应者的半导体芯片尺寸的减小并抑制成本半导体芯片

59. 发明申请

US20090140300A1 ELECTRONIC TAG CHIP 失效
标题翻译：电子标签芯片
公开(公告)号：US20090140300A1
公开(公告)日：2009-06-04
申请号：US11719693
申请日：2005-02-16
申请人： Mitsuo Usami
发明人： Mitsuo Usami
IPC分类号： H01L29/786 , H01L27/12
CPC分类号： H01L29/94 , H01L24/33 , H01L27/0688 , H01L27/0811 , H01L27/1203 , H01L27/1255 , H01L29/861 , H01L2924/13091 , H01L2924/14 , Y10S257/922 , H01L2924/00
摘要： In order to extend the communication distance of an electronic tag chip, it is required to reduce power consumption of the electronic tag chip. After having formed capacitors and diodes on an SOI (Silicon on Insulator), remove a silicon substrate of the SOI. It becomes possible to reduce the capacitors and diodes of the electronic tag chip in parasitic capacitance relative to the ground, which makes it possible to reduce the power consumption of the electronic tag chip, thereby enabling the electronic tag chip to increase in communication distance thereof.
摘要翻译：为了延长电子标签芯片的通信距离，需要降低电子标签芯片的功耗。在SOI（绝缘体上硅）上形成电容器和二极管后，移除SOI的硅衬底。可以减小电子标签芯片相对于地面的寄生电容的电容器和二极管，从而可以降低电子标签芯片的功耗，从而能够使电子标签芯片的通信距离增加。

60. 发明授权

US07442959B2 Semiconductor device having identification number, manufacturing method thereof and electronic device 失效
标题翻译：具有识别号码的半导体装置及其制造方法以及电子装置
公开(公告)号：US07442959B2
公开(公告)日：2008-10-28
申请号：US10610631
申请日：2003-07-02
申请人： Mitsuo Usami
发明人： Mitsuo Usami
IPC分类号： H01L29/00
CPC分类号： H01L23/544 , H01L2223/54413 , H01L2223/54433 , H01L2223/54473 , H01L2924/0002 , H01L2924/00
摘要： An electronic device includes a semiconductor chip storing an identification number of N-bits and an antenna coupled to the semiconductor chip that sends out the identification number of N-bits. In order to provide a secure and efficient data storage arrangement, the identification number of N-bits is stored in accordance with the presence or absence of through holes that connect wirings to transistors included in the semiconductor chip through an insulating film formed over the transistors.
摘要翻译：电子设备包括存储N位的识别号的半导体芯片和耦合到半导体芯片的天线，其发送N位的标识号。为了提供安全有效的数据存储装置，根据存在或不存在通过形成在晶体管上的绝缘膜将配线连接到包括在半导体芯片中的晶体管的通孔而存储N位的标识号。

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