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51. 发明授权

US5094879A Method of activating at least one gas to produce different charged species, selecting specific species, decelerating the species, and chemically reacting the species to form a thin film 失效
标题翻译：至少生产一种气体来生产不同充电物种的方法，选择特定物种，减少物种，并化学反应物种形成薄膜
公开(公告)号：US5094879A
公开(公告)日：1992-03-10
申请号：US544595
申请日：1990-06-27
申请人： Tetsuo Matsuda , Haruo Okano , Tokuhisa Ohiwa
发明人： Tetsuo Matsuda , Haruo Okano , Tokuhisa Ohiwa
IPC分类号： C23C16/50 , C23C14/22 , C23C16/452 , C23C16/511 , H01J37/32 , H01L21/205 , H01L21/31
CPC分类号： H01J37/32422 , C23C14/221 , C23C16/452 , H01J37/32357
摘要： According to a thin film forming method, at least one type of gas is activated to produce a plurality of species having positive or negative charges. The plurality of species pass through an electric field or magnetic field to extract specific species. The specific species are supplied to a substrate surface. Thereafter, the specific species are chemically reacted with each other to form a thin film. This extraction is performed using a difference in track corresponding to a ratio of mass to charge of the species passing through the electric field.
摘要翻译：根据薄膜形成方法，至少一种类型的气体被激活以产生具有正或负电荷的多种物质。多个物种通过电场或磁场提取特定物种。特定的物质被提供给基底表面。此后，特定物质彼此化学反应以形成薄膜。使用对应于通过电场的物质的质量与电荷的比率的轨迹差进行该提取。

52. 发明授权

US4866009A Multilayer wiring technique for a semiconductor device 失效
标题翻译：半导体器件的多层布线技术
公开(公告)号：US4866009A
公开(公告)日：1989-09-12
申请号：US306211
申请日：1989-02-03
申请人： Tetsuo Matsuda
发明人： Tetsuo Matsuda
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522
CPC分类号： H01L21/76879 , Y10S148/05 , Y10S148/06
摘要： A method of manufacturing a semiconductor device includes the steps of (a) forming a first conductive pattern on a semiconductor substrate, (b) forming a first interlayer insulating film, covering the first conductive pattern, (c) forming a second conductive pattern, composed of a refractory metal, on the first interlayer insulating film, (d) forming a contact hole reaching the first conductive pattern through the second conductive pattern and the first interlayer insulating film at a predetermined position, (e) performing an annealing step before or after formation of the contact hole in step (d), and (f) covering in the contact hole with a metal film, after annealing step (e), to connect the second conductive pattern to the first conductive pattern. In this method, annealing step--for example, gettering--is performed before the wiring layer of the refractory metal is placed in contact with the semiconductor layer. For this reason, even if the other semiconductor layers are made of silicon, silicification of the refractory metal can be prevented.
摘要翻译：一种制造半导体器件的方法包括以下步骤：（a）在半导体衬底上形成第一导电图案，（b）形成第一层间绝缘膜，覆盖第一导电图案，（c）形成第二导电图案，在第一层间绝缘膜上，（d）在预定位置形成通过第二导电图案到达第一导电图案的接触孔和第一层间绝缘膜，（e）在前后进行退火步骤在步骤（d）中形成接触孔，和（f）在退火步骤（e）之后用金属膜覆盖接触孔，以将第二导电图案连接到第一导电图案。在该方法中，在难熔金属的布线层与半导体层接触之前进行退火步骤，例如吸杂。因此，即使其他半导体层由硅制成，也可以防止难熔金属的硅化。

53. 发明授权

US4118336A Novel cellulose microcapsules and preparation thereof 失效
标题翻译：新型纤维素微胶囊及其制备方法
公开(公告)号：US4118336A
公开(公告)日：1978-10-03
申请号：US750588
申请日：1976-12-15
申请人： Masataka Morishita , Yasuo Yokokawa , Tokio Nishikawa , Masahiro Mishiro , Shigeyasu Ohashi , Mitsuru Fukushima , Yoshihito Inaba , Tetsuo Matsuda
发明人： Masataka Morishita , Yasuo Yokokawa , Tokio Nishikawa , Masahiro Mishiro , Shigeyasu Ohashi , Mitsuru Fukushima , Yoshihito Inaba , Tetsuo Matsuda
IPC分类号： B01J13/06 , B01J20/28 , B01J13/02
CPC分类号： B01J20/28026 , B01J13/06 , B01J20/28004 , B01J20/2805 , B01J20/28078 , Y10T428/2989
摘要： A novel cellulose microcapsule having adsorbing capacity, consisting of outer semipermeable barrier layer of cellulose and adsorbent powders dispersed within inner cellulose gel matrix, is prepared by ester hydrolysis of a precursor microcapsule consisting of cellulose ester derivative and adsorbent powders. It is excellent in resistance to chemicals such as acids, alkalis or organic solvents and is useful for various purposes.
摘要翻译：通过由纤维素酯衍生物和吸附剂粉末组成的前体微胶囊的酯水解制备具有吸附能力的新型纤维素微胶囊，其由纤维素的外部半透膜阻隔层和分散在内部纤维素凝胶基质内的吸附剂粉末组成。它对耐酸性，碱性或有机溶剂的耐化学性是优异的，可用于各种目的。

54. 发明授权

US3988309A EEL calcitonin 失效
标题翻译： EEL降钙素
公开(公告)号：US3988309A
公开(公告)日：1976-10-26
申请号：US536889
申请日：1974-12-17
申请人： Tetsuo Matsuda , Susumu Watanabe , Shunpei Sakakibara , Eisuke Munekata , Tadanori Morikawa , Masaru Otani , Toshiharu Noda , Hirose Yamauchi , Tosio Meguro , Shuichi Kitazawa
发明人： Tetsuo Matsuda , Susumu Watanabe , Shunpei Sakakibara , Eisuke Munekata , Tadanori Morikawa , Masaru Otani , Toshiharu Noda , Hirose Yamauchi , Tosio Meguro , Shuichi Kitazawa
IPC分类号： A61K38/00 , C07K14/585 , C07C103/52 , C07G7/00
CPC分类号： C07K14/585 , A61K38/00 , Y10S514/808 , Y10S530/857
摘要： A polypeptide having calcitonin activity of the formula ##EQU1## and the salts thereof with pharmaceutically acceptable acids.
摘要翻译：具有式H-Cys-Ser-Asn-Leu-Ser-Thr-Cys-Val -Leu-Gly-Lys-Leu-Ser-Gln-Glu-Leu-His-Lys-Leu-Gln- Thr-Tyr-Pro-Arg-Thr-Asp-Val-Gly-Ala-Gly-Thr-Pro-NH 2及其盐与药学上可接受的酸。

55. 发明授权

US08415247B2 Semiconductor device and method for manufacturing of same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08415247B2
公开(公告)日：2013-04-09
申请号：US13234099
申请日：2011-09-15
申请人： Tomomi Imamura , Tetsuo Matsuda , Yoshinosuke Nishijo
发明人： Tomomi Imamura , Tetsuo Matsuda , Yoshinosuke Nishijo
IPC分类号： H01L21/4763
CPC分类号： H01L23/53209 , H01L21/76852 , H01L21/76883 , H01L21/76885 , H01L29/66666 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a semiconductor device, includes: forming a first metal layer on a semiconductor substrate, the semiconductor substrate including a diffusion layer; forming an insulating layer having an opening on the first metal layer; forming a second metal layer on the first metal layer in the opening of the insulating layer; removing the insulating layer; covering an exposed surface of the second metal layer with a third metal layer, the third metal layer including a metal having an ionization tendency lower than that of the second metal layer; and forming an electrode interconnect including the first metal layer, the second metal layer, and the third metal layer by removing the first metal layer using the third metal layer as a mask.
摘要翻译：一种制造半导体器件的方法，包括：在半导体衬底上形成第一金属层，所述半导体衬底包括扩散层; 在所述第一金属层上形成具有开口的绝缘层; 在绝缘层的开口中的第一金属层上形成第二金属层; 去除绝缘层; 用第三金属层覆盖第二金属层的暴露表面，第三金属层包括电离倾向低于第二金属层的金属; 以及通过使用第三金属层作为掩模去除第一金属层，形成包括第一金属层，第二金属层和第三金属层的电极互连。

56. 发明申请

US20120313162A1 SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING METAL FILM, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件，制造金属膜的方法和制造半导体器件的方法
公开(公告)号：US20120313162A1
公开(公告)日：2012-12-13
申请号：US13425226
申请日：2012-03-20
申请人： Tetsuo Matsuda , Tomomi Kuraguchi
发明人： Tetsuo Matsuda , Tomomi Kuraguchi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/2254 , H01L21/28518 , H01L21/28556 , H01L21/28568 , H01L29/086 , H01L29/0878 , H01L29/167 , H01L29/41741 , H01L29/41766 , H01L29/456 , H01L29/66727 , H01L29/66734
摘要： According to one embodiment, a semiconductor device includes: a semiconductor substrate; an arsenic diffusion layer formed in the semiconductor substrate and containing arsenic; and a metal film formed on the arsenic diffusion layer. The metal film includes at least one metal selected from the group consisting of tungsten, titanium, ruthenium, hafnium, and tantalum, and arsenic.
摘要翻译：根据一个实施例，半导体器件包括：半导体衬底; 形成在所述半导体衬底中并含有砷的砷扩散层; 以及形成在砷扩散层上的金属膜。金属膜包括选自钨，钛，钌，铪和钽中的至少一种金属和砷。

57. 发明申请

US20120217575A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US20120217575A1
公开(公告)日：2012-08-30
申请号：US13238525
申请日：2011-09-21
申请人： Tetsuo Matsuda
发明人： Tetsuo Matsuda
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0856 , H01L29/086 , H01L29/0878 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/66727 , H01L29/66734 , H01L29/66787
摘要： According to one embodiment, a method is disclosed for manufacturing semiconductor device. The method can include preparing a semiconductor layer having a drain layer, and a drift region provided from a surface to an inside of the drain layer, the drift region having a first trench extending from a surface to an inside of the drift region. The method can include implanting impurities into the drift region through an opening of the first trench to form a source region for an exposed face of the drift region exposed on an inside wall of the first trench, and implanting impurities into the drift region through the opening of the first trench to form a base region between the source region and the drift region. The method can include forming gate electrode.
摘要翻译：根据一个实施例，公开了一种用于制造半导体器件的方法。该方法可以包括制备具有漏极层的半导体层和从漏极层的表面到内部提供的漂移区域，漂移区域具有从漂移区域的表面延伸到内部的第一沟槽。该方法可以包括通过第一沟槽的开口将杂质注入到漂移区域中，以形成暴露在第一沟槽的内壁上的漂移区域的暴露面的源极区域，以及通过开口将杂质注入漂移区域以形成源极区域和漂移区域之间的基极区域。该方法可以包括形成栅电极。

58. 发明授权

US07898031B2 Semiconductor device with tapered trenches and impurity concentration gradients 有权
标题翻译：具有锥形沟槽和杂质浓度梯度的半导体器件
公开(公告)号：US07898031B2
公开(公告)日：2011-03-01
申请号：US12821708
申请日：2010-06-23
申请人： Kenichi Tokano , Tetsuo Matsuda , Wataru Saito
发明人： Kenichi Tokano , Tetsuo Matsuda , Wataru Saito
IPC分类号： H01L29/772
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1095 , H01L29/66712
摘要： A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.
摘要翻译：第一导电类型的单晶半导体层设置在半导体衬底的表面上。在半导体层中设置多个沟槽，以在与该表面平行的方向上间隔地形成第一导电类型的多个第一半导体区域。外延层被埋在多个沟槽中以形成多个第二导电类型的第二半导体区域。多个第二半导体区域各自包括形成在沟槽的内壁上的具有高杂质浓度的外部部分，并且内部部分具有比外部部分内部形成的内部部分。

59. 发明授权

US07595530B2 Power semiconductor device with epitaxially-filled trenches 有权
标题翻译：具有外延填充沟槽的功率半导体器件
公开(公告)号：US07595530B2
公开(公告)日：2009-09-29
申请号：US11364203
申请日：2006-03-01
申请人： Kenichi Tokano , Tetsuo Matsuda , Wataru Saito
发明人： Kenichi Tokano , Tetsuo Matsuda , Wataru Saito
IPC分类号： H01L29/38
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1095 , H01L29/66712
摘要： A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.
摘要翻译：第一导电类型的单晶半导体层设置在半导体衬底的表面上。在半导体层中设置多个沟槽，以在与该表面平行的方向上间隔地形成第一导电类型的多个第一半导体区域。外延层被埋在多个沟槽中以形成多个第二导电类型的第二半导体区域。多个第二半导体区域各自包括形成在沟槽的内壁上的具有高杂质浓度的外部部分，并且内部部分具有比外部部分内部形成的内部部分。

60. 发明授权

US07486663B2 Remote access server wherein the number of logical link resources is set higher than the number of physical link resources 失效
标题翻译：远程访问服务器，其中将逻辑链路资源的数量设置为高于物理链路资源的数量
公开(公告)号：US07486663B2
公开(公告)日：2009-02-03
申请号：US10786364
申请日：2004-02-26
申请人： Tetsuo Matsuda , Masayuki Yamada , Kazuhiko Azuma , Toshikazu Maruyama
发明人： Tetsuo Matsuda , Masayuki Yamada , Kazuhiko Azuma , Toshikazu Maruyama
IPC分类号： H04L12/66
CPC分类号： H04L12/2872 , H04L12/12 , H04L12/2856 , Y02D50/40
摘要： In a remote access server (RAS), the number of logical link resources, which are circuit resources between the RAS and an ISP server, is set greater than the number of physical link resources, which are circuit resources between the RAS and each terminal device. In the RAS, when a particular circuit undergoes a transition to the dormant state, only the physical link resource is released to allow use by other terminal devices while the logical link resource is maintained unchanged in a connected state, whereby the loss probability is reduced without increasing the number of physical link resources.
摘要翻译：在远程访问服务器（RAS）中，将RAS与ISP服务器之间的电路资源的逻辑链路资源的数量设置为大于物理链路资源的数量，这些物理链路资源是RAS与每个终端设备之间的电路资源。在RAS中，当特定电路经历到休眠状态的转换时，只有物理链路资源被释放以允许其他终端设备使用，而逻辑链路资源在连接状态下保持不变，从而丢失概率降低而没有增加物理链路资源的数量。

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