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51. 发明授权

US08053865B2 MOM capacitors integrated with air-gaps 有权
标题翻译： MOM电容器与气隙集成
公开(公告)号：US08053865B2
公开(公告)日：2011-11-08
申请号：US12045547
申请日：2008-03-10
申请人： Chung-Long Chang , Ming-Shih Yeh , Chia-Yi Chen , David Ding-Chung Lu
发明人： Chung-Long Chang , Ming-Shih Yeh , Chia-Yi Chen , David Ding-Chung Lu
IPC分类号： H01L29/72
CPC分类号： H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure combining air-gaps and metal-oxide-metal (MOM) capacitors is provided. The integrated circuit structure includes a semiconductor substrate; a first metallization layer over the semiconductor substrate; first metal features in the first metallization layer; a second metallization layer over the first metallization layer; second metal features in the second metallization layer, wherein the first and the second metal features are non-capacitor features; a MOM capacitor having an area in at least one of the first and the second metallization layers; and an air-gap in the first metallization layer and between the first metal features.
摘要翻译：提供了一种组合气隙和金属氧化物金属（MOM）电容器的集成电路结构。集成电路结构包括半导体衬底; 半导体衬底上的第一金属化层; 第一金属层中的第一金属特征; 第一金属化层上的第二金属化层; 在第二金属化层中的第二金属特征，其中第一和第二金属特征是非电容器特征; MOM电容器，其具有在所述第一和第二金属化层中的至少一个中的区域; 以及在第一金属化层中和第一金属特征之间的气隙。

52. 发明授权

US08022458B2 Capacitors integrated with metal gate formation 有权
标题翻译：电容器与金属栅极结合
公开(公告)号：US08022458B2
公开(公告)日：2011-09-20
申请号：US11868856
申请日：2007-10-08
申请人： Chung-Long Chang , David Ding-Chung Lu , Chia-Yi Chen , I-Lu Wu
发明人： Chung-Long Chang , David Ding-Chung Lu , Chia-Yi Chen , I-Lu Wu
IPC分类号： H01L27/108
CPC分类号： H01L27/11568 , H01L23/5223 , H01L27/0629 , H01L27/105 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate; and a capacitor over the substrate. The capacitor includes a first layer including a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode is formed of a metal-containing material and is free from polysilicon. The semiconductor structure further includes a MOS device including a gate dielectric over the substrate; and a metal-containing gate electrode on the gate dielectric, wherein the metal-containing gate electrode is formed of a same material, and has a same thickness, as the first capacitor electrode.
摘要翻译：提供了包括具有增加的电容和改善的电性能的电容器的半导体结构。半导体结构包括基板; 以及在基板上的电容器。电容器包括：第一层，包括第一电容器电极和第二电容器电极，其中第一电容器电极由含金属的材料形成并且不含多晶硅。所述半导体结构还包括：在所述基板上包括栅电介质的MOS器件; 以及栅极电介质上的含金属的栅电极，其中所述含金属的栅电极由与所述第一电容器电极相同的材料形成，并且具有相同的厚度。

53. 发明申请

US20080100989A1 Layout for capacitor pair with high capacitance matching 有权
标题翻译：具有高电容匹配的电容器对的布局
公开(公告)号：US20080100989A1
公开(公告)日：2008-05-01
申请号：US11591643
申请日：2006-11-01
申请人： Chia-Yi Chen , Chung-Long Chang , Chih-Ping Chao
发明人： Chia-Yi Chen , Chung-Long Chang , Chih-Ping Chao
IPC分类号： H01G4/38
CPC分类号： H01L27/0805 , H01G4/38 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device includes a capacitor array, which includes unit capacitors arranged in rows and columns, wherein each unit capacitor is formed of two electrically insulated capacitor plates. The unit capacitors include at least one first unit capacitor in each row and in each column of the capacitor array; the at least one first unit capacitor being interconnected, wherein each row of the capacitor array comprises a same number of the at least one first unit capacitors as other rows and columns have, and wherein each column of the capacitor array comprises a same number of the at least one first unit capacitors as other rows and columns have. The unit capacitors further include at least one second unit capacitor in each row and in each column of the capacitor array, wherein the at least one second unit is interconnected and evenly distributed throughout the array.
摘要翻译：集成电路装置包括电容器阵列，其包括以行和列排列的单位电容器，其中每个单位电容器由两个电绝缘电容器板形成。单位电容器包括电容器阵列的每一行和每列中的至少一个第一单位电容器; 所述至少一个第一单元电容器互连，其中所述电容器阵列的每一行包括与其它行和列具有相同数量的所述至少一个第一单位电容器，并且其中所述电容器阵列的每列包括相同数量的其他行和列具有至少一个第一单位电容器。单元电容器还包括在电容器阵列的每一列和每列中的至少一个第二单位电容器，其中该至少一个第二单元互连并均匀分布在整个阵列中。

54. 发明申请

US20080099879A1 Capacitor pairs with improved mismatch performance 有权
标题翻译：具有改善失配性能的电容对
公开(公告)号：US20080099879A1
公开(公告)日：2008-05-01
申请号：US11591644
申请日：2006-11-01
申请人： Chia-Yi Chen , Chung-Long Chang , Chih-Ping Chao
发明人： Chia-Yi Chen , Chung-Long Chang , Chih-Ping Chao
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first capacitor comprising a plurality of first unit capacitors interconnected to each other, each having a first unit capacitance; and a second capacitor comprising a plurality of second unit capacitors interconnected to each other, each having a second unit capacitance, wherein the first unit capacitors and the second unit capacitors have equal numbers of unit capacitors. The first unit capacitors and the second unit capacitors are arranged in an array with rows and columns and placed in an alternating pattern in each row and each column. The first and the second unit capacitors each have a total number greater than two.
摘要翻译：半导体器件包括：第一电容器，包括彼此互连的多个第一单位电容器，每个具有第一单位电容; 以及包括彼此互连的多个第二单位电容器的第二电容器，每个具有第二单位电容，其中所述第一单位电容器和所述第二单位电容器具有相等数目的单位电容器。第一单元电容器和第二单元电容器以具有行和列的阵列排列并且以每行和每列置于交替图案中。第一和第二单元电容器的总数大于2。

55. 发明申请

US20070158783A1 Interdigitated capacitive structure for an integrated circuit 有权
标题翻译：用于集成电路的交叉电容结构
公开(公告)号：US20070158783A1
公开(公告)日：2007-07-12
申请号：US11328502
申请日：2006-01-09
申请人： Yueh-You Chen , Chung-Long Chang , Chih-Ping Chao
发明人： Yueh-You Chen , Chung-Long Chang , Chih-Ping Chao
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： System and method for an improved interdigitated capacitive structure for an integrated circuit. A preferred embodiment comprises a first layer of a sequence of substantially parallel interdigitated strips, each strip of either a first polarity or a second polarity, the sequence alternating between a strip of the first polarity and a strip of the second polarity. A first dielectric layer is deposited over each strip of the first layer of strips. A first extension layer of a sequence of substantially interdigitated extension strips is deposited over the first dielectric layer, each extension strip deposited over a strip of the first layer of the opposite polarity. A first sequence of vias is coupled to the first extension layer, each via deposited over an extension strip of the same polarity. A second layer of a sequence of substantially parallel interdigitated strips can be coupled to the first sequence of vias.
摘要翻译：用于集成电路的改进的互指电容结构的系统和方法。优选实施例包括基本上平行的叉指序列序列的第一层，每个条带具有第一极性或第二极性，该序列在第一极性的条带和第二极性的条之间交替。第一介电层沉积在第一层条带的每条上。基本上交错的延伸条的序列的第一延伸层沉积在第一介电层上，每个延伸条沉积在具有相反极性的第一层的条上。通孔的第一序列耦合到第一延伸层，每个通孔沉积在相同极性的延伸条上。基本上平行的叉指序列序列的第二层可以耦合到第一序列通孔。

56. 发明授权

US07050290B2 Integrated capacitor 有权
标题翻译：集成电容
公开(公告)号：US07050290B2
公开(公告)日：2006-05-23
申请号：US10768916
申请日：2004-01-30
申请人： Denny Tang , Wen-Chin Lin , Li-Shyue Lai , Chun-Hon Chen , Chung-Long Chang
发明人： Denny Tang , Wen-Chin Lin , Li-Shyue Lai , Chun-Hon Chen , Chung-Long Chang
IPC分类号： H01G4/008 , H01G4/20
CPC分类号： H01L28/60 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A new capacitor device having two terminals is achieved. The device comprises a plurality of first conductive lines overlying a substrate. Each of the first conductive lines is connected to one of the capacitor device terminals. The adjacent first conductive lines are connected to opposite terminals. The first conductive lines comprise a plurality of conductive materials. A plurality of second conductive lines overlie the plurality of first conductive lines. Each of the second conductive lines is connected to one of the capacitive device terminals. Adjacent second conductive lines are connected to opposite terminals. Any second conductive line overlying any first conductive line is connected to an opposite terminal. The second conductive lines comprises a plurality of conductive materials. A first dielectric layer overlies the substrate and lies between the adjacent first conductive lines. A second dielectric layer lies between the first conductive lines and the second conductive lines.
摘要翻译：实现了具有两个端子的新的电容器装置。该器件包括覆盖衬底的多个第一导电线。每个第一导线连接到电容器装置端子之一。相邻的第一导线连接到相对的端子。第一导线包括多个导电材料。多个第二导线覆盖多个第一导线。每个第二导线连接到电容器件端子中的一个。相邻的第二导线连接到相对的端子。覆盖任何第一导线的任何第二导线连接到相对的端子。第二导线包括多个导电材料。第一电介质层覆盖在基板之间并且位于相邻的第一导电线之间。第二介电层位于第一导线和第二导线之间。

57. 发明申请

US20050282396A1 Micro-etching method to replicate alignment marks for semiconductor wafer photolithography 有权
标题翻译：用于复制半导体晶片光刻的对准标记的微蚀刻方法
公开(公告)号：US20050282396A1
公开(公告)日：2005-12-22
申请号：US10872238
申请日：2004-06-18
申请人： Yu-Liang Lin , Henry Lo , Chung-Long Chang , Gorge Huang , Tony Lu , Gnesh Yeh , Candy Liang , Chun-Hsien Lin , Mei Sheng Zhou , Sunny Wu , Ai-Sen Liu , Cheng-Lin Huang , Li-Jui Chen , Shih Wang
发明人： Yu-Liang Lin , Henry Lo , Chung-Long Chang , Gorge Huang , Tony Lu , Gnesh Yeh , Candy Liang , Chun-Hsien Lin , Mei Sheng Zhou , Sunny Wu , Ai-Sen Liu , Cheng-Lin Huang , Li-Jui Chen , Shih Wang
IPC分类号： H01L21/00 , H01L21/302 , H01L21/311 , H01L21/336 , H01L21/461 , H01L23/544
CPC分类号： H01L23/544 , H01L21/31111 , H01L21/67282 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for locally etching a substrate area the method including providing a substrate comprising a process surface; depositing a material layer over the process surface; and, applying a wet etchant to cover a targeted etching portion of the process surface while excluding an adjacent surrounding area to selectively etch the material layer overlying the targeted etching portion.
摘要翻译：一种用于局部蚀刻衬底区域的方法和装置，该方法包括提供包含工艺表面的衬底; 在工艺表面上沉积材料层; 以及施加湿蚀刻剂以覆盖所述工艺表面的目标蚀刻部分，同时排除相邻的周围区域以选择性地蚀刻覆盖所述目标蚀刻部分的所述材料层。

58. 发明申请

US20050168914A1 Integrated capacitor 有权
标题翻译：集成电容
公开(公告)号：US20050168914A1
公开(公告)日：2005-08-04
申请号：US10768916
申请日：2004-01-30
申请人： Denny Tang , Wen-Chin Lin , Li-Shyue Lai , Chun-Hon Chen , Chung-Long Chang
发明人： Denny Tang , Wen-Chin Lin , Li-Shyue Lai , Chun-Hon Chen , Chung-Long Chang
IPC分类号： H01G4/228 , H01L21/02 , H01L23/522
CPC分类号： H01L28/60 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A new capacitor device having two terminals is achieved. The device comprises a plurality of first conductive lines overlying a substrate. Each of the first conductive lines is connected to one of the capacitor device terminals. The adjacent first conductive lines are connected to opposite terminals. The first conductive lines comprise a plurality of conductive materials. A plurality of second conductive lines overlie the plurality of first conductive lines. Each of the second conductive lines is connected to one of the capacitive device terminals. Adjacent second conductive lines are connected to opposite terminals. Any second conductive line overlying any first conductive line is connected to an opposite terminal. The second conductive lines comprises a plurality of conductive materials. A first dielectric layer overlies the substrate and lies between the adjacent first conductive lines. A second dielectric layer lies between the first conductive lines and the second conductive lines.
摘要翻译：实现了具有两个端子的新的电容器装置。该器件包括覆盖衬底的多个第一导电线。每个第一导线连接到电容器装置端子之一。相邻的第一导线连接到相对的端子。第一导线包括多个导电材料。多个第二导线覆盖多个第一导线。每个第二导线连接到电容器件端子中的一个。相邻的第二导线连接到相对的端子。覆盖任何第一导线的任何第二导线连接到相对的端子。第二导线包括多个导电材料。第一电介质层覆盖在基板之间并且位于相邻的第一导电线之间。第二介电层位于第一导线和第二导线之间。

59. 发明授权

US5933744A Alignment method for used in chemical mechanical polishing process 失效
标题翻译：用于化学机械抛光工艺的对准方法
公开(公告)号：US5933744A
公开(公告)日：1999-08-03
申请号：US54302
申请日：1998-04-02
申请人： Jeng-Horng Chen , Tsu Shih , Jui-Yu Chang , Chung-Long Chang
发明人： Jeng-Horng Chen , Tsu Shih , Jui-Yu Chang , Chung-Long Chang
IPC分类号： H01L21/3105 , H01L23/544 , H01L21/465 , H01L21/76
CPC分类号： H01L23/544 , H01L21/31053 , H01L2223/54453 , H01L2924/0002 , Y10S438/975
摘要： A method of alignment for a chemical mechanical polishing includes previously patterning a primary zero alignment mark on a surface of a wafer. A first dielectric layer is deposited on the wafer for isolation. Then, an etching is used to etch the first dielectric layer using a photoresist as a mask. First conductive plugs are formed in the first dielectric layer. Next, a first conductive layer is formed on the surface of the first dielectric layer and on the tungsten plugs. Thus, the first non-zero alignment mark pattern is formed on the surface of the first conductive layer and aligned to the first conductive plugs. Next, a second non-zero alignment mark pattern is thus formed on the surface of a second conductive layer and aligned to the a second conductive plugs. By repeating the aforementioned method, odd non-zero alignment mark patterns will be formed over the first non-zero alignment mark pattern, and even non-zero alignment mark patterns will be formed over the second non-zero alignment mark pattern. Therefore, the present invention save space to put non-zero alignment marks in multilevel interconnection and planarization processes.
摘要翻译：用于化学机械抛光的对准方法包括预先对晶片表面上的初级零对准标记进行图案化。第一介电层沉积在晶片上用于隔离。然后，使用蚀刻来使用光致抗蚀剂作为掩模蚀刻第一介电层。在第一电介质层中形成第一导电插塞。接下来，在第一电介质层的表面和钨插塞上形成第一导电层。因此，第一非零对准标记图案形成在第一导电层的表面上并与第一导电插塞对准。接下来，在第二导电层的表面上形成第二非零对准标记图案，并与第二导电插塞对准。通过重复上述方法，将在第一非零对准标记图案上形成奇数非零对准标记图案，并且甚至在第二非零对准标记图案上形成非零对准标记图案。因此，本发明节省空间，将非零对准标记放置在多层互连和平面化处理中。

60. 发明授权

US5709755A Method for CMP cleaning improvement 失效
标题翻译： CMP清洗改进方法
公开(公告)号：US5709755A
公开(公告)日：1998-01-20
申请号：US694728
申请日：1996-08-09
申请人： So Wein Kuo , Tsu Shih , Chung-Long Chang
发明人： So Wein Kuo , Tsu Shih , Chung-Long Chang
IPC分类号： B08B1/04 , H01L21/00 , H01L21/304 , H01L21/306 , H01L21/30
CPC分类号： H01L21/02052 , B08B1/04 , H01L21/02024 , H01L21/67046
摘要： Using an APM solution to clean both the front and backside of a semiconductor wafer significantly reduces the residue from chemical mechanical polishing. A low residue count holds the wafer more securely to the electrostatic chuck, thus improving processing, reducing wear on the electrostatic chuck, and increasing its lifetime.
摘要翻译：使用APM解决方案清洁半导体晶片的正面和背面显着减少化学机械抛光的残留物。低残留数量将晶片更牢固地保持在静电卡盘上，从而改善处理，减少静电卡盘上的磨损，并延长其使用寿命。

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