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51. 发明授权

US07511340B2 Semiconductor devices having gate structures and contact pads that are lower than the gate structures 失效
标题翻译：具有栅极结构的半导体器件和低于栅极结构的接触焊盘
公开(公告)号：US07511340B2
公开(公告)日：2009-03-31
申请号：US11779477
申请日：2007-07-18
申请人： Deok-Hyung Lee , Si-Young Choi , Byeong-Chan Lee , Chul-Sung Kim , In-Soo Jung , Jong-Ryeol Yoo
发明人： Deok-Hyung Lee , Si-Young Choi , Byeong-Chan Lee , Chul-Sung Kim , In-Soo Jung , Jong-Ryeol Yoo
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/10888 , H01L21/28525 , H01L21/76829 , H01L21/76832 , H01L21/76895 , H01L23/485 , H01L27/10894 , H01L2924/0002 , Y10S257/90 , H01L2924/00
摘要： Semiconductor devices have gate structures on a semiconductor substrate with first spacers on sidewalls of the respective gate structures. First contact pads are positioned between the gate structures and have heights lower than the heights of the gate structures. Second spacers are disposed on sidewalls of the first spacers and on exposed sidewalls of the first contact pads. Second contact pads are disposed on the first contact pads.
摘要翻译：半导体器件在半导体衬底上具有栅极结构，在相应栅极结构的侧壁上具有第一间隔物。第一接触垫位于栅极结构之间并且具有低于栅极结构的高度的高度。第二间隔件设置在第一间隔件的侧壁和第一接触垫的暴露的侧壁上。第二接触垫设置在第一接触垫上。

52. 发明申请

US20090072294A1 Method of manufacturing a non-volatile memory device 审中-公开
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20090072294A1
公开(公告)日：2009-03-19
申请号：US11974636
申请日：2007-10-15
申请人： Sang-Ryol Yang , Sung-Kweon Baek , Si-Young Choi , Bon-Young Koo , Ki-Hyun Hwang
发明人： Sang-Ryol Yang , Sung-Kweon Baek , Si-Young Choi , Bon-Young Koo , Ki-Hyun Hwang
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of manufacturing a non-volatile memory device employing a relatively thin polysilicon layer as a floating gate is disclosed, wherein a tunnel oxide layer is formed on a substrate and a polysilicon layer having a thickness of about 35 Å to about 200 Å is then formed on the tunnel oxide layer using a trisilane (Si3H8) gas as a silicon source gas. The tunnel oxide layer and the polysilicon layer are then patterned into a tunnel oxide layer pattern and a polysilicon layer pattern, respectively. A dielectric layer and a conductive layer corresponding to a control gate are subsequently formed on the polysilicon layer pattern. The polysilicon layer is formed using trisilane (Si3H8) gas as a result of which the polysilicon layer may be formed to have a relatively thin thickness while maintaining a thickness uniformity and realizing a superior morphology thus producing a floating gate having enhanced performance.
摘要翻译：公开了一种使用相对薄的多晶硅层作为浮动栅极的非易失性存储器件的制造方法，其中在衬底上形成隧道氧化物层，然后形成厚度为约至大约的厚度的多晶硅层使用丙硅烷（Si 3 H 8）气体作为硅源气体在隧道氧化物层上形成。然后将隧道氧化物层和多晶硅层分别图案化为隧道氧化物层图案和多晶硅层图案。随后在多晶硅层图案上形成对应于控制栅的电介质层和导电层。使用丙硅烷（Si 3 H 8）气体形成多晶硅层，结果可以形成多晶硅层以具有相对较薄的厚度，同时保持厚度均匀性并实现优异的形态，从而产生具有增强性能的浮栅。

53. 发明申请

US20090068823A1 Plasma Ion Doping Method and Apparatus 审中-公开
标题翻译：等离子体离子掺杂法和仪器
公开(公告)号：US20090068823A1
公开(公告)日：2009-03-12
申请号：US12145914
申请日：2008-06-25
申请人： Soo Jin Hong , Si-Young Choi , Tai-Su Park , Jin-Wook Lee , Jong-Hoon Kang , Mi-Jin Kim
发明人： Soo Jin Hong , Si-Young Choi , Tai-Su Park , Jin-Wook Lee , Jong-Hoon Kang , Mi-Jin Kim
IPC分类号： H01L21/02 , H01J37/08
CPC分类号： H01L21/2236 , H01J37/32412 , H01J37/32449
摘要： In plasma ion doping operations, a wafer is positioned on a susceptor within a reaction chamber and an ion doping source gas is plasmalyzed in an upper part of the reaction chamber above a major surface of the wafer while supplying a control gas into the reaction chamber in a lower part of the reaction chamber opposite the major surface of the wafer to thereby dope ions into the major surface of the wafer. The ion doping source gas may comprise at least one halide gas, and the control gas may comprise at least one depositing gas, such as a silane gas. In further embodiments, a diluent gas, such as an inert gas, may be supplied to the reaction chamber while supplying the ion doping source gas and the control gas. Related plasma ion doping apparatus are described.
摘要翻译：在等离子体离子掺杂操作中，将晶片定位在反应室内的基座上，并且将离子掺杂源气体在晶片的主表面上方的反应室上部进行等离子化，同时将控制气体供应到反应室中反应室的下部与晶片的主表面相对，从而将离子掺杂到晶片的主表面。离子掺杂源气体可以包括至少一种卤化物气体，并且控制气体可以包括至少一种沉积气体，例如硅烷气体。在另外的实施方案中，可以向反应室供应诸如惰性气体的稀释气体，同时供应离子掺杂源气体和控制气体。描述了相关的等离子体离子掺杂装置。

54. 发明申请

US20090014781A1 Nonvolatile memory devices and methods for fabricating nonvolatile memory devices 有权
标题翻译：用于制造非易失性存储器件的非易失存储器件和方法
公开(公告)号：US20090014781A1
公开(公告)日：2009-01-15
申请号：US12216945
申请日：2008-07-14
申请人： Seung-Jae Baik , Hong-Suk Kim , Si-Young Choi , Ki-Hyun Hwang , Sang-Jin Hyun
发明人： Seung-Jae Baik , Hong-Suk Kim , Si-Young Choi , Ki-Hyun Hwang , Sang-Jin Hyun
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/42348 , H01L29/513 , H01L29/66833
摘要： A nonvolatile memory device may include: a tunnel insulating layer on a semiconductor substrate; a charge storage layer on the tunnel insulating layer; a blocking insulating layer on the charge storage layer; and a control gate electrode on the blocking insulating layer. The tunnel insulating layer may include a first tunnel insulating layer and a second tunnel insulating layer. The first tunnel insulating layer and the second tunnel insulating layer may be sequentially stacked on the semiconductor substrate. The second tunnel insulating layer may have a larger band gap than the first tunnel insulating layer. A method for fabricating a nonvolatile memory device may include: forming a tunnel insulating layer on a semiconductor substrate; forming a charge storage layer on the tunnel insulating layer; forming a blocking insulating layer on the charge storage layer; and forming a control gate electrode on the blocking insulating layer.
摘要翻译：非易失性存储器件可以包括：半导体衬底上的隧道绝缘层; 隧道绝缘层上的电荷存储层; 电荷存储层上的阻挡绝缘层; 以及在所述阻挡绝缘层上的控制栅电极。隧道绝缘层可以包括第一隧道绝缘层和第二隧道绝缘层。第一隧道绝缘层和第二隧道绝缘层可以顺序地堆叠在半导体衬底上。第二隧道绝缘层可以具有比第一隧道绝缘层更大的带隙。非易失性存储器件的制造方法可以包括：在半导体衬底上形成隧道绝缘层; 在隧道绝缘层上形成电荷存储层; 在电荷存储层上形成阻挡绝缘层; 以及在所述阻挡绝缘层上形成控制栅电极。

55. 发明申请

US20080308845A1 Heterogeneous Group IV Semiconductor Substrates 审中-公开
标题翻译：异质IV族半导体基片
公开(公告)号：US20080308845A1
公开(公告)日：2008-12-18
申请号：US12195790
申请日：2008-08-21
申请人： Sung-Min Kim , Kyoung-Hwan Yeo , In-Soo Jung , Si-Young Choi , Dong-Won Kim , Yong-Hoon Son , Young-Eun Lee , Byeong-Chan Lee , Jong-Wook Lee
发明人： Sung-Min Kim , Kyoung-Hwan Yeo , In-Soo Jung , Si-Young Choi , Dong-Won Kim , Yong-Hoon Son , Young-Eun Lee , Byeong-Chan Lee , Jong-Wook Lee
IPC分类号： H01L29/00
CPC分类号： H01L29/0653 , H01L29/78
摘要： Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.
摘要翻译：本发明的实施例包括异质衬底，在这种异质衬底上形成的集成电路。根据本发明的某些实施方案的异质衬底包括第一组IV半导体层（例如，硅），第二组IV图案（例如硅 - 锗图案），其包括第一组IV上的多个单独元件半导体层和第二组IV模式上的第三组IV半导体层（例如，硅外延层）和第一组IV半导体层的多个暴露部分上。在本发明的实施例中可以去除第二组IV图案。在本发明的这些和其它实施例中，第三组IV半导体层可以被平坦化。

56. 发明申请

US20080194083A1 Methods of Laterally Forming Single Crystalline Thin Film Regions from Seed Layers 失效
标题翻译：从种子层单面形成单晶薄膜区域的方法
公开(公告)号：US20080194083A1
公开(公告)日：2008-08-14
申请号：US12061253
申请日：2008-04-02
申请人： Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee , Pil-Kyu Kang
发明人： Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee , Pil-Kyu Kang
IPC分类号： H01L21/36
CPC分类号： H01L21/8221 , H01L21/02381 , H01L21/02532 , H01L21/02667 , H01L27/0688 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/1285 , H01L29/78675
摘要： In a method of manufacturing a semiconductor device, a string structure including a selection transistor and a memory cell on a substrate. An insulation layer pattern is formed on the substrate to cover the string structure. The insulation layer pattern includes at least one opening exposing a portion of the substrate adjacent to the selection transistor. A seed layer including a single-crystalline material is formed in the opening. An amorphous thin film including an amorphous material is formed on the insulation layer pattern and the seed layer. The amorphous thin film is transformed into a single-crystalline thin film, using the single-crystalline material in the seed layer as a seed during a phase transition of the amorphous thin film, to form a channel layer on the insulation layer pattern and the seed layer. Therefore, the semiconductor device including the channel layer having the single-crystalline thin film may be manufactured.
摘要翻译：在制造半导体器件的方法中，包括在衬底上的选择晶体管和存储单元的串联结构。在衬底上形成绝缘层图案以覆盖串结构。绝缘层图案包括暴露基板的与选择晶体管相邻的部分的至少一个开口。在开口中形成包括单晶材料的晶种层。在绝缘层图案和种子层上形成包含非晶材料的非晶态薄膜。在非晶薄膜的相变期间，将晶种层中的单晶材料作为种子，将非晶薄膜转变为单晶薄膜，以在绝缘层图案和种子上形成沟道层层。因此，可以制造包括具有单晶薄膜的沟道层的半导体器件。

57. 发明申请

US20080093601A1 Integrated circuit devices including a transcription-preventing pattern and methods of manufacturing the same 失效
标题翻译：包括转录阻止图案的集成电路装置及其制造方法
公开(公告)号：US20080093601A1
公开(公告)日：2008-04-24
申请号：US11974293
申请日：2007-10-12
申请人： Pil-Kyu Kang , Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee , Byeong-Chan Lee , In-Soo Jung
发明人： Pil-Kyu Kang , Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee , Byeong-Chan Lee , In-Soo Jung
IPC分类号： H01L29/786 , H01L29/12 , H01L21/84
CPC分类号： H01L21/823425 , H01L21/823475
摘要： Integrated circuit devices are provided including a first single-crystalline layer and an insulating layer pattern on the first single-crystalline layer. The insulating layer pattern has an opening therein that partially exposes the first single-crystalline layer. A seed layer is in the opening. A second single-crystalline layer is on the insulating layer pattern and the seed layer. The second single-crystalline layer has a crystalline structure substantially the same as that of the seed layer. A transcription-preventing pattern is on the second single-crystalline layer and a third single-crystalline layer on the transcription-preventing pattern and the second single-crystalline layer. The transcription-preventing pattern is configured to limit transcription of defective portions in the second single-crystalline layer into the third single-crystalline layer.
摘要翻译：在第一单晶层上提供包括第一单晶层和绝缘层图案的集成电路器件。绝缘层图案在其中具有部分地暴露第一单晶层的开口。种子层在开口处。第二单晶层位于绝缘层图案和籽晶层上。第二单晶层具有与种子层基本相同的晶体结构。转录阻止图案位于转录阻止图案和第二单晶层上的第二单晶层和第三单晶层上。转录阻止图案被配置为将第二单晶层中的缺陷部分的转录限制为第三单晶层。

58. 发明申请

US20080085584A1 OXIDATION/HEAT TREATMENT METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES 审中-公开
标题翻译：制造非易失性存储器件的氧化/热处理方法
公开(公告)号：US20080085584A1
公开(公告)日：2008-04-10
申请号：US11857824
申请日：2007-09-19
申请人： Young-Jin Noh , Chul-Sung Kim , Si-Young Choi , Bon-Young Koo , Ki-Hyun Hwang , Sung-Kweon Baek
发明人： Young-Jin Noh , Chul-Sung Kim , Si-Young Choi , Bon-Young Koo , Ki-Hyun Hwang , Sung-Kweon Baek
IPC分类号： H01L21/336
CPC分类号： H01L21/28247 , H01L29/40114
摘要： Methods of manufacturing non-volatile memory devices are disclosed which may at least partially cure etch damage and may at least partially remove defect sites in gate structures of the devices caused during manufacturing of the devices. An exemplary method of manufacturing a non-volatile memory device includes forming a gate structure on a substrate, the gate structure including a control gate electrode, a blocking layer pattern, a floating gate electrode, and a tunnel insulating layer pattern. An oxidation process is performed that at least partially cures damage caused to the substrate and to the gate structure during formation of the gate structure. A first heat treatment is performed under a gas atmosphere including nitrogen to at least partially remove defect sites on the gate structure caused by the oxidation process. A second heat treatment is performed under a gas atmosphere including chlorine to at least partially remove remaining defect sites on the gate structure caused by the oxidation process.
摘要翻译：公开了制造非易失性存储器件的方法，其可以至少部分地固化蚀刻损伤，并且可以至少部分地去除在器件的制造期间引起的器件的栅极结构中的缺陷位置。制造非易失性存储器件的示例性方法包括在衬底上形成栅极结构，栅极结构包括控制栅电极，阻挡层图案，浮栅电极和隧道绝缘层图案。进行氧化处理，其至少部分地固化在栅极结构形成期间对衬底和栅极结构的损伤。在包括氮气的气体气氛下进行第一热处理，以至少部分地去除由氧化过程引起的栅极结构上的缺陷部位。在包括氯的气体气氛下进行第二热处理，以至少部分地去除由氧化过程引起的栅极结构上的剩余缺陷部位。

59. 发明申请

US20080048262A1 Fin field effect transistor and method of forming the same 审中-公开
标题翻译： Fin场效应晶体管及其形成方法
公开(公告)号：US20080048262A1
公开(公告)日：2008-02-28
申请号：US11892320
申请日：2007-08-22
申请人： Deok-Hyung Lee , Sun-Ghil Lee , Gyeong-Ho Buh , Jong-Ryeol Yoo , Si-Young Choi , Tai-Su Park
发明人： Deok-Hyung Lee , Sun-Ghil Lee , Gyeong-Ho Buh , Jong-Ryeol Yoo , Si-Young Choi , Tai-Su Park
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/7851 , H01L29/41791 , H01L29/66636 , H01L29/66795 , H01L2029/7858
摘要： Provided are a fin field effect transistor (FinFET) with recess source/drain regions, and a method of forming the same. One example embodiment may provide a semiconductor device including a fin provided on a substrate and extending in a first direction, the fin including a stepped portion, and a gate electrode extending in a second direction crossing the first direction, and provided on a top surface and side surfaces of the stepped portion of the fin.
摘要翻译：提供具有凹陷源极/漏极区域的鳍式场效应晶体管（FinFET）及其形成方法。一个示例性实施例可以提供一种半导体器件，其包括设置在基板上并沿第一方向延伸的鳍，所述鳍包括台阶部分，以及沿与第一方向交叉的第二方向延伸的栅电极，并且设置在顶表面上翅片的台阶部分的侧表面。

60. 发明授权

US07320908B2 Methods of forming semiconductor devices having buried oxide patterns 有权
标题翻译：形成具有掩埋氧化物图案的半导体器件的方法
公开(公告)号：US07320908B2
公开(公告)日：2008-01-22
申请号：US11072103
申请日：2005-03-04
申请人： Yong-Hoon Son , Si-Young Choi , Byeong-Chan Lee , Jong-Wook Lee , In-Soo Jung , Deok-Hyung Lee
发明人： Yong-Hoon Son , Si-Young Choi , Byeong-Chan Lee , Jong-Wook Lee , In-Soo Jung , Deok-Hyung Lee
IPC分类号： H01L21/338
CPC分类号： H01L29/7851 , H01L21/823481 , H01L29/0653 , H01L29/66545 , H01L29/66621
摘要： Methods for forming semiconductor devices are provided. A semiconductor substrate is etched such that the semiconductor substrate defines a trench and a preliminary active pattern. The trench has a floor and a sidewall. An insulating layer is provided on the floor and the sidewall of the trench and a spacer is formed on the insulating layer such that the spacer is on the sidewall of the trench and on a portion of the floor of the trench. The insulating layer is removed on the floor of the trench and beneath the spacer such that a portion of the floor of the trench is at least partially exposed, the spacer is spaced apart from the floor of the trench and a portion of the preliminary active pattern is partially exposed. A portion of the exposed portion of the preliminary active pattern is partially removed to provide an active pattern that defines a recessed portion beneath the spacer. A buried insulating layer is formed in the recessed portion of the active pattern. Related devices are also provided.
摘要翻译：提供了形成半导体器件的方法。蚀刻半导体衬底，使得半导体衬底限定沟槽和初步活性图案。沟槽具有地板和侧壁。绝缘层设置在地板上，并且沟槽的侧壁和间隔件形成在绝缘层上，使得间隔件位于沟槽的侧壁和沟槽底部的一部分上。绝缘层在沟槽的地板上移除并且在间隔物的下面被移除，使得沟槽的底部的一部分至少部分地露出，间隔物与沟槽的底部间隔开，并且预活性图案的一部分部分暴露。部分地去除预活性图案的暴露部分的一部分以提供在间隔物下方限定凹陷部分的活性图案。在活性图案的凹部中形成掩埋绝缘层。还提供了相关设备。

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