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51. 发明授权

US08392476B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08392476B2
公开(公告)日：2013-03-05
申请号：US12885941
申请日：2010-09-20
申请人： Shigehiro Asano , Kenichiro Yoshii , Kazuhiro Fukutomi , Shinichi Kanno
发明人： Shigehiro Asano , Kenichiro Yoshii , Kazuhiro Fukutomi , Shinichi Kanno
IPC分类号： G06F17/30
CPC分类号： G06F12/0246 , G06F2212/7205
摘要： According to one embodiment, a semiconductor memory device performs writing of data to a semiconductor memory element in response to a request to write the data with a specified logical block address from a host and performs writing of valid data to the semiconductor memory element for compaction according to a log-structured method. The semiconductor memory device adjusts a frequency of the writing response to a request from the host and a frequency of the writing for compaction according to a predetermined ratio.
摘要翻译：根据一个实施例，半导体存储器件响应于从主机以指定的逻辑块地址写入数据的请求，执行将数据写入到半导体存储器元件，并且执行将有效数据写入半导体存储元件以进行压缩以日志结构的方式。半导体存储器装置根据预定的比例调整来自主机的请求的写入响应的频率和用于压缩的写入频率。

52. 发明授权

US08341497B2 Semiconductor storage 失效
标题翻译：半导体存储
公开(公告)号：US08341497B2
公开(公告)日：2012-12-25
申请号：US12713631
申请日：2010-02-26
申请人： Kazuhiro Fukutomi , Hideaki Sato , Shinichi Kanno , Shigehiro Asano
发明人： Kazuhiro Fukutomi , Hideaki Sato , Shinichi Kanno , Shigehiro Asano
IPC分类号： G11C29/00 , G06F11/00
CPC分类号： G06F11/108 , G06F11/1052
摘要： A semiconductor storage includes a receiver configured to receive a write request from a host device; a storage unit configured to hold redundancy data generation/non-generation information; a writing unit configured to write data in a semiconductor memory array and write redundancy data generation/non-generation information of the written data in the storage unit; a first data extracting unit configured to extract data whose redundancy data is not generated from among the data held by the semiconductor memory array; a first redundancy data generating unit configured to generate redundancy data; a first redundancy data writing unit configured to write the generated redundancy data in the semiconductor memory array; and a first redundancy data generation/non-generation information updating unit configured to update the redundancy data generation/non-generation information of the data whose redundancy data held by the storage unit is generated.
摘要翻译：半导体存储器包括被配置为从主机设备接收写请求的接收器; 存储单元，被配置为保存冗余数据生成/非生成信息; 写入单元，被配置为在半导体存储器阵列中写入数据，并将写入的数据的冗余数据生成/非生成信息写入存储单元中; 第一数据提取单元，被配置为从半导体存储器阵列保存的数据中提取不产生冗余数据的数据; 第一冗余数据生成单元，被配置为生成冗余数据; 第一冗余数据写入单元，被配置为将所生成的冗余数据写入所述半导体存储器阵列中; 以及第一冗余数据生成/非生成信息更新单元，被配置为更新由所述存储单元保持的冗余数据生成的数据的冗余数据生成/非生成信息。

53. 发明授权

US08219861B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08219861B2
公开(公告)日：2012-07-10
申请号：US13270788
申请日：2011-10-11
申请人： Toshikatsu Hida , Shinichi Kanno , Hirokuni Yano , Kazuya Kitsunai , Shigehiro Asano , Junji Yano
发明人： Toshikatsu Hida , Shinichi Kanno , Hirokuni Yano , Kazuya Kitsunai , Shigehiro Asano , Junji Yano
IPC分类号： G11C29/00
CPC分类号： G06F11/1412 , G06F11/1068 , G06F11/1402 , G06F12/02 , G11C16/0483 , G11C16/3418 , G11C16/3431
摘要： As a semiconductor storage device that can efficiently perform a refresh operation, provided is a semiconductor storage device comprising a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing, and a controlling unit monitoring an error count of data stored in a monitored block selected from the blocks and refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.
摘要翻译：作为可以有效地执行刷新操作的半导体存储装置，提供了一种半导体存储装置，其包括以块为单位存储数据的非易失性半导体存储器，该块是数据擦除单元，以及监视数据的错误计数的控制单元存储在从所述块中选择的监视块和所述监视块中的刷新数据中，其中所述错误计数等于或大于阈值。

54. 发明授权

US08060797B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08060797B2
公开(公告)日：2011-11-15
申请号：US12529282
申请日：2008-09-22
申请人： Toshikatsu Hida , Shinichi Kanno , Hirokuni Yano , Kazuya Kitsunai , Shigehiro Asano , Junji Yano
发明人： Toshikatsu Hida , Shinichi Kanno , Hirokuni Yano , Kazuya Kitsunai , Shigehiro Asano , Junji Yano
IPC分类号： G06F11/00
CPC分类号： G06F11/1412 , G06F11/1068 , G06F11/1402 , G06F12/02 , G11C16/0483 , G11C16/3418 , G11C16/3431
摘要： A semiconductor storage device can efficiently perform a refresh operation. A semiconductor storage device is provided which includes a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing. A controlling unit is further included monitoring an error count of data stored in a monitored block selected from the blocks and for refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.
摘要翻译：半导体存储装置可以有效地执行刷新操作。提供一种半导体存储装置，其包括以块为单位存储数据的非易失性半导体存储器，该块是数据擦除的单位。还包括控制单元，用于监视存储在从块中选择的监视块中的数据的错误计数，以及用于刷新其中错误计数等于或大于阈值的监视块中的数据。

55. 发明授权

US08015347B2 Memory system and control method thereof 有权
标题翻译：存储系统及其控制方法
公开(公告)号：US08015347B2
公开(公告)日：2011-09-06
申请号：US12552422
申请日：2009-09-02
申请人： Kazuya Kitsunai , Shinichi Kanno , Hirokuni Yano , Toshikatsu Hida , Junji Yano
发明人： Kazuya Kitsunai , Shinichi Kanno , Hirokuni Yano , Toshikatsu Hida , Junji Yano
IPC分类号： G06F13/00
CPC分类号： G06F3/0604 , G06F3/0616 , G06F3/0619 , G06F3/064 , G06F3/0647 , G06F3/0652 , G06F3/0659 , G06F3/0679 , G06F3/0685 , G06F12/0246 , G06F2212/1036 , G06F2212/7202 , G06F2212/7205 , G06F2212/7211
摘要： A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
摘要翻译：存储器系统包括包括作为数据擦除单元的多个块的非易失性存储器，测量擦除每个块的数据的擦除时间的测量单元，以及写入从至少外部提供的数据到第一块设置为空闲状态，擦除时间最长。

56. 发明申请

US20110202812A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110202812A1
公开(公告)日：2011-08-18
申请号：US12888822
申请日：2010-09-23
申请人： Shigehiro ASANO , Kenichiro Yoshii , Kazuhiro Fukutomi , Shinichi Kanno
发明人： Shigehiro ASANO , Kenichiro Yoshii , Kazuhiro Fukutomi , Shinichi Kanno
IPC分类号： G06F11/14
CPC分类号： G11C29/52 , G06F11/1008 , G06F11/1068
摘要： According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.
摘要翻译：根据一个实施例，半导体存储器件包括要求写入数据的半导体存储器芯片。数据具有预定单元中的一个或多个第一数据。该装置包括写入控制器，其写入通过使用预定数量的第一数据计算出的第一数据和冗余信息，并将其用于将预定数量的第一数据中的错误校正到不同的半导体存储器芯片中; 以及存储单元，其存储相互关联的识别信息和区域指定信息。所述识别信息将所述第一数据和所述冗余信息相关联，并且所述区域指定信息指定所述第一数据和所述冗余信息相互写入的所述半导体存储器芯片中的多个存储区域。

57. 发明申请

US20110202578A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110202578A1
公开(公告)日：2011-08-18
申请号：US12885941
申请日：2010-09-20
申请人： Shigehiro ASANO , Kenichiro Yoshii , Kazuhiro Fukutomi , Shinichi Kanno
发明人： Shigehiro ASANO , Kenichiro Yoshii , Kazuhiro Fukutomi , Shinichi Kanno
IPC分类号： G06F17/30
CPC分类号： G06F12/0246 , G06F2212/7205
摘要： According to one embodiment, a semiconductor memory device performs writing of data to a semiconductor memory element in response to a request to write the data with a specified logical block address from a host and performs writing of valid data to the semiconductor memory element for compaction according to a log-structured method. The semiconductor memory device adjusts a frequency of the writing response to a request from the host and a frequency of the writing for compaction according to a predetermined ratio.
摘要翻译：根据一个实施例，半导体存储器件响应于从主机以指定的逻辑块地址写入数据的请求，执行将数据写入到半导体存储器元件，并且执行将有效数据写入半导体存储元件以进行压缩以日志结构的方式。半导体存储器装置根据预定的比例调整来自主机的请求的写入响应的频率和用于压缩的写入频率。

58. 发明授权

US07900117B2 Semiconductor memory device and its control method 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US07900117B2
公开(公告)日：2011-03-01
申请号：US12400863
申请日：2009-03-10
申请人： Shinichi Kanno
发明人： Shinichi Kanno
IPC分类号： H03M13/00
CPC分类号： G06F11/1068
摘要： A semiconductor memory device includes a temporary storage circuit configured to receive data items and store the data items in rows and columns, a detecting code generator configured to generate first detecting codes used to detect errors in the data items, respectively, a first correcting code generator configured to generate first correcting codes used to correct errors in first data blocks corresponding to the columns, respectively, each of the first data blocks containing data items that are arranged in a corresponding one of the columns, and a second correcting code generator configured to generate second correcting codes used to correct errors in second data blocks corresponding to the rows, respectively, each of the second data blocks containing data items that are arranged in a corresponding one of the rows.
摘要翻译：一种半导体存储器件，包括临时存储电路，被配置为接收数据项并将数据项存储在行和列中;检测码发生器，被配置为分别生成用于检测数据项中的错误的第一检测码;第一校正码发生器被配置为分别产生用于校正与所述列相对应的第一数据块中的错误的第一校正码，每个第一数据块包含布置在对应的一列中的数据项，以及第二校正码生成器，被配置为生成用于分别对应于行的第二数据块中的错误的第二校正码，每个第二数据块包含布置在相应行中的数据项。

59. 发明申请

US20100169553A1 MEMORY SYSTEM, CONTROLLER, AND METHOD OF CONTROLLING MEMORY SYSTEM 有权
标题翻译：存储器系统，控制器和控制存储器系统的方法
公开(公告)号：US20100169553A1
公开(公告)日：2010-07-01
申请号：US12566236
申请日：2009-09-24
申请人： Hirokuni YANO , Shinichi Kanno
发明人： Hirokuni YANO , Shinichi Kanno
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F12/0866 , G06F2212/7202
摘要： A memory system according to an embodiment of the present invention includes a volatile first storing unit, a nonvolatile second storing unit, a controller that transfers data between a host apparatus and the second storing unit via the first storing unit. The memory system monitors whether data written from the host apparatus in the first storing unit has a specific pattern in management units. When data to be flushed to the second storing unit has the specific pattern, the memory system set an invalid address value that is not in use in the second storing unit to the data.
摘要翻译：根据本发明的实施例的存储器系统包括易失性第一存储单元，非易失性第二存储单元，经由第一存储单元在主机设备和第二存储单元之间传送数据的控制器。存储系统监视从第一存储单元中的主机设备写入的数据是否具有管理单元中的特定模式。当要刷新到第二存储单元的数据具有特定模式时，存储器系统将不在第二存储单元中使用的无效地址值设置为数据。

60. 发明申请

US20100122147A1 MEMORY CONTROLLER CONTROLLING SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR DEVICE 失效
标题翻译：存储器控制器控制半导体存储器件和半导体器件
公开(公告)号：US20100122147A1
公开(公告)日：2010-05-13
申请号：US12687915
申请日：2010-01-15
申请人： Shinichi Kanno , Yosuke Kuroda , Toshio Shirakihara
发明人： Shinichi Kanno , Yosuke Kuroda , Toshio Shirakihara
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G11C16/3418
摘要： A memory controller controls a semiconductor storage device including nonvolatile memory cells. The controller includes a generating circuit, and a selection circuit. The generating circuit generates first data based on a second data. The selection circuit retains a cumulative value whose each digit is a cumulative result in each bit of data which is already written in the memory cells. The selection circuit selects one of the first data. A selected first data has a better average of digits in a sum of each bit of the selected first data and each digit of the cumulative value than an unselected first data. The selection circuit retains the sum concerning the selected first data as the new cumulative value.
摘要翻译：存储器控制器控制包括非易失性存储单元的半导体存储器件。控制器包括发生电路和选择电路。生成电路基于第二数据生成第一数据。选择电路保留累积值，其每个数字是已经写入存储器单元的每个数据位的累积结果。选择电路选择第一数据之一。所选择的第一数据在所选择的第一数据的每一比特和累积值的每个数字之和与未选择的第一数据的和中具有更好的数字平均。选择电路将与所选择的第一数据相关的和保持为新的累积值。

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