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51. 发明授权

US4392267A Apparatus for continuously pickling the outer surfaces of tubular materials 失效
标题翻译：用于连续酸洗管状材料外表面的装置
公开(公告)号：US4392267A
公开(公告)日：1983-07-12
申请号：US307676
申请日：1981-10-01
申请人： Yoshiro Tanaka , Hayato Moroi , Yukihiko Komatsu , Kazuo Akagi , Ryujiro Shitamatsu , Tadashi Nishimura
发明人： Yoshiro Tanaka , Hayato Moroi , Yukihiko Komatsu , Kazuo Akagi , Ryujiro Shitamatsu , Tadashi Nishimura
IPC分类号： B65G13/00 , C23G3/04 , B08B9/02
CPC分类号： C23G3/04
摘要： An apparatus for continuously pickling the outer surfaces of hermetically plugged tubular members is described. The apparatus includes a plurality of liquid tanks which separately contain different pickling liquids and define through-holes in their respective front and rear walls on at least one common longitudinal line to permit the successive passage of the tubular members therethrough while rotating them around their respective longitudinal axes. The apparatus includes a cleaning tank and cleaning brush unit provided sequentially before the liquid tanks. The cleaning tank includes at least one ultrasonic cleaning oscillator and defines through-holes in the front and rear walls thereof for allowing said tubular members to pass through the cleaning tank and the brush unit. Since any oil, grease or dust can be completely removed by the cleaning tank and brush unit prior to pickling, it is possible to obtain tubular members having excellent outer surface quality.
摘要翻译：描述了用于连续酸洗密封管状构件的外表面的装置。该装置包括多个液体罐，其分开地容纳不同的酸洗液体，并且在至少一个共同的纵向线上的相应的前壁和后壁中形成通孔，以允许管状构件连续通过，同时使它们围绕它们各自的纵向旋转轴。该装置包括在液罐之前依次提供的清洗槽和清洁刷单元。清洗槽包括至少一个超声波清洗振荡器，并在其前壁和后壁上形成通孔，以允许所述管状构件通过清洁槽和刷子单元。由于在酸洗之前可以通过清洗槽和刷子单元完全除去任何油，油脂或灰尘，所以可以获得具有优异的外表面质量的管状构件。

52. 发明授权

US06727552B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06727552B2
公开(公告)日：2004-04-27
申请号：US10062462
申请日：2002-02-05
申请人： Yasuo Inoue , Tadashi Nishimura , Yasuo Yamaguchi , Toshiaki Iwamatsu
发明人： Yasuo Inoue , Tadashi Nishimura , Yasuo Yamaguchi , Toshiaki Iwamatsu
IPC分类号： H01L2701
CPC分类号： H01L21/8238 , H01L21/84 , H01L23/4825 , H01L27/0921 , H01L27/1203 , H01L29/78609 , H01L29/78612 , H01L29/78615 , H01L29/78621 , H01L29/78645 , H01L29/78654 , H01L2924/0002 , H01L2924/00
摘要： According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.
摘要翻译：根据本发明的半导体器件，形成场致氧化膜以覆盖SOI层的主表面并到达掩埋氧化膜的主表面。结果，可以完全电隔离SOI的pMOS有源区和SOI的nMOS有源区。因此，可以完全防止闭锁。结果，可以提供使用SOI衬底的半导体器件，该SOI衬底可以通过消除源极和漏极之间的击穿电压的降低来实现高集成度，这是常规SOI场效应晶体管的问题，以及有效地设置妨碍高集成度的身体接触区域及其制造方法。

53. 发明授权

US06649976B2 Semiconductor device having metal silicide film and manufacturing method thereof 失效
公开(公告)号：US06649976B2
公开(公告)日：2003-11-18
申请号：US09982777
申请日：2001-10-22
申请人： Toshiaki Iwamatsu , Yasuo Inoue , Yasuo Yamaguchi , Tadashi Nishimura
发明人： Toshiaki Iwamatsu , Yasuo Inoue , Yasuo Yamaguchi , Tadashi Nishimura
IPC分类号： H01L2976
CPC分类号： H01L21/26506 , H01L21/26586 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/458 , H01L29/66507 , H01L29/66659 , H01L29/66772 , H01L29/78621
摘要： A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.

54. 发明授权

US06358783B1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06358783B1
公开(公告)日：2002-03-19
申请号：US09233212
申请日：1999-01-20
申请人： Yasuo Yamaguchi , Tadashi Nishimura
发明人： Yasuo Yamaguchi , Tadashi Nishimura
IPC分类号： H01L2100
CPC分类号： H01L29/66772 , H01L21/26586 , H01L29/78609 , H01L29/78621 , H01L29/78627
摘要： A semiconductor device includes a MOS-type field effect transistor (SOI-MOSFET) formed on a thin silicon layer on an insulator layer. The SOI-MOSFET has a gate overlap-type LDD structure in which additional source/drain regions having an impurity concentration of 3×1017 to 3×1018/cm3 overlapping with a gate electrode are provided in the silicon layer. According to this structure, when the SOI-MOSFET is on operation, only the additional source/drain regions are depleted, so that it is possible to obtain satisfactory transistor characteristics. Additional source/drain regions in this structure are formed by combination of vertical ion implantation using the gate electrode as a mask and thermal diffusion or oblique ion implantation using the gate electrode as a mask.
摘要翻译：半导体器件包括形成在绝缘体层上的薄硅层上的MOS型场效应晶体管（SOI-MOSFET）。 SOI-MOSFET具有栅极重叠型LDD结构，其中在硅层中提供了与栅电极重叠的杂质浓度为3×10 17至3×10 18 / cm 3的附加源/漏区。根据该结构，当SOI-MOSFET工作时，只有附加的源极/漏极区域被耗尽，从而可以获得令人满意的晶体管特性。该结构中的额外的源极/漏极区域通过使用栅电极作为掩模的垂直离子注入和使用栅极电极作为掩模的热扩散或倾斜离子注入的组合形成。

55. 发明授权

US06214664B1 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06214664B1
公开(公告)日：2001-04-10
申请号：US09443016
申请日：1999-11-18
申请人： Hiroshi Kimura , Tadashi Nishimura , Takahiro Tsuruda , Kazutami Arimoto , Tadato Yamagata , Kazuyasu Fujishima
发明人： Hiroshi Kimura , Tadashi Nishimura , Takahiro Tsuruda , Kazutami Arimoto , Tadato Yamagata , Kazuyasu Fujishima
IPC分类号： H01L218242
CPC分类号： H01L27/10852
摘要： In a semiconductor device and a method of manufacturing the same, an isolating and insulating film is provided at an end neighboring to a second impurity region with a groove extended to a semiconductor substrate. This removes a crystal defect existed at the end of the isolating and insulating film, and thus prevents leak of a current at this portion from a storage node. Consequently, provision of the groove at the edge portion of the isolating oxide film neighboring to the impurity region removes a crystal defect at this region, and thus eliminates a possibility of leak of a current.
摘要翻译：在半导体器件及其制造方法中，隔离绝缘膜设置在与第二杂质区相邻的端部处，并且沟槽延伸到半导体衬底。这消除了隔离和绝缘膜末端存在的晶体缺陷，从而防止在该部分处的电流从存储节点泄漏。因此，在与杂质区相邻的隔离氧化膜的边缘部分处设置沟槽消除了该区域的晶体缺陷，从而消除了电流泄漏的可能性。

56. 发明授权

US6051494A Semiconductor device having metal silicide film 失效
标题翻译：具有金属硅化物膜的半导体器件
公开(公告)号：US6051494A
公开(公告)日：2000-04-18
申请号：US855259
申请日：1997-05-13
申请人： Toshiaki Iwamatsu , Yasuo Inoue , Yasuo Yamaguchi , Tadashi Nishimura
发明人： Toshiaki Iwamatsu , Yasuo Inoue , Yasuo Yamaguchi , Tadashi Nishimura
IPC分类号： H01L21/28 , H01L21/265 , H01L21/336 , H01L21/76 , H01L21/84 , H01L27/12 , H01L29/45 , H01L29/78 , H01L29/786 , H01L21/44
CPC分类号： H01L21/26506 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/458 , H01L29/66507 , H01L29/66659 , H01L29/66772 , H01L21/26586 , H01L29/78621
摘要： A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.
摘要翻译：可以获得其中源极/漏极区域的寄生电阻可以比漏极区域的寄生电阻降低的半导体器件及其制造方法。在半导体装置中，仅将钝化离子注入到半导体层的源极区域，以损坏半导体层的表面附近的晶体，从而促进了硅化反应。因此，在源极区域中，可以形成更厚的硅化钛膜。

57. 发明授权

US5721444A Thin-film transistor having a buried impurity region and method of fabricating the same 失效
标题翻译：具有埋入杂质区的薄膜晶体管及其制造方法
公开(公告)号：US5721444A
公开(公告)日：1998-02-24
申请号：US824550
申请日：1997-03-25
申请人： Toshiyuki Oashi , Jiro Matsufusa , Takahisa Eimori , Tadashi Nishimura
发明人： Toshiyuki Oashi , Jiro Matsufusa , Takahisa Eimori , Tadashi Nishimura
IPC分类号： H01L21/316 , H01L21/02 , H01L21/205 , H01L21/265 , H01L21/76 , H01L21/84 , H01L27/12 , H01L29/786 , H01L27/01
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/78606 , H01L29/78609
摘要： A buried insulating layer is provided in a semiconductor substrate, in a position separated from its major surface. A LOCOS isolation film is provided in the major surface of the semiconductor substrate for isolating an active region from other active regions. A thin-film transistor is provided in the active region. The thin-film transistor comprises a gate electrode which is provided on the active region with interposition of a gate insulating layer. A pair of source/drain layers are provided in the major surface of the semiconductor substrate on both sides of the gate electrode. A high-concentration impurity layer is provided in the semiconductor substrate immediately under the buried insulating layer.
摘要翻译：掩埋绝缘层设置在半导体衬底中的与其主表面分离的位置。在半导体衬底的主表面上提供了一个LOCOS隔离膜，用于将活性区域与其它活性区域隔离。在有源区域中设置薄膜晶体管。薄膜晶体管包括设置在有源区上的栅极，插入栅极绝缘层。在栅电极的两侧的半导体衬底的主表面上设置一对源极/漏极层。在掩埋绝缘层正下方的半导体衬底中设置高浓度杂质层。

58. 发明授权

US5471086A Semiconductor device having piezo resistance 失效
标题翻译：具有压电电阻的半导体器件
公开(公告)号：US5471086A
公开(公告)日：1995-11-28
申请号：US332623
申请日：1992-10-31
申请人： Takashi Ipposhi , Tadashi Nishimura
发明人： Takashi Ipposhi , Tadashi Nishimura
IPC分类号： H01L21/20 , G01L9/00 , H01L21/822 , H01L27/04 , H01L29/84 , H01L41/04 , H01L41/08
CPC分类号： G01L9/0055 , H01L29/84
摘要： Disclosed herein a semiconductor pressure sensor, which is capable of carrying out temperature compensation in high accuracy, having a piezo resistance layer consisting of a single crystal layer formed by lateral seeding. In this semiconductor pressure sensor, a piezo resistance is so formed as to contain no crystal sub-grain boundary. Thus prevented is inconvenience of reduction in resistance temperature coefficient, which is caused when the piezo resistance contains the crystal sub-grain boundary. Thus, the piezo resistance can be set at a high resistance temperature coefficient, whereby a semiconductor pressure sensor capable of carrying out temperature compensation in high accuracy is obtained.
摘要翻译：这里公开了能够以高精度进行温度补偿的半导体压力传感器，其具有由横向接种形成的单晶层构成的压电电阻层。在该半导体压力传感器中，压电电阻形成为不含晶粒子晶界。因此防止了当压电电阻含有晶体亚晶界时引起的电阻温度系数降低的不便。因此，可以将压电电阻设定在高电阻温度系数，从而获得能够以高精度进行温度补偿的半导体压力传感器。

59. 发明授权

US5343051A Thin-film SOI MOSFET 失效
标题翻译：薄膜SOI MOSFET
公开(公告)号：US5343051A
公开(公告)日：1994-08-30
申请号：US58814
申请日：1993-05-10
申请人： Yasuo Yamaguchi , Tadashi Nishimura
发明人： Yasuo Yamaguchi , Tadashi Nishimura
IPC分类号： H01L21/84 , H01L21/336 , H01L29/78 , H01L29/786 , H01L29/04 , H01L27/01 , H01L27/108
CPC分类号： H01L29/66772 , H01L29/786 , H01L29/78612 , H01L29/78615 , H01L2924/0002
摘要： An MOS field effect transistor comprises a channel region (6) of a first conductivity type formed in a semiconductor layer (3) on an insulator substrate (2), a source region (8) and a drain region (9) of a second conductivity type formed in contact with one and the other sides of the channel region (6) in the semiconductor layer (3), respectively, a body region (7) formed in contact with at least a part of the channel region (6) and a part of a periphery of the source region (8) in the semiconductor layer (3) and having a higher impurity concentration than that of the channel region (6), a gate electric thin film (4) and a gate electrode (5) formed on the channel region (6), and a conductor (14a) connected in common to the source region (8) and the body region (7).
摘要翻译： MOS场效应晶体管包括形成在绝缘体基板（2）上的半导体层（3）中的第一导电类型的沟道区（6），具有第二导电性的源区（8）和漏区（9）分别与半导体层（3）中的沟道区（6）的一侧和另一侧接触形成与沟道区（6）的至少一部分形成的主体区（7）和半导体层（3）中的源极区（8）的周边的一部分，并且具有比沟道区（6）的杂质浓度高的杂质浓度，形成栅极电薄膜（4）和栅电极（5）在沟道区域（6）上，以及与源区（8）和体区（7）共同连接的导体（14a）。

60. 发明授权

US5336918A Semiconductor pressure sensor and method of fabricating the same 失效
标题翻译：半导体压力传感器及其制造方法
公开(公告)号：US5336918A
公开(公告)日：1994-08-09
申请号：US51914
申请日：1993-04-26
申请人： Takashi Ipposhi , Tadashi Nishimura
发明人： Takashi Ipposhi , Tadashi Nishimura
IPC分类号： G01L9/04 , G01L9/00 , H01L21/20 , H01L21/84 , H01L29/84 , H01L29/06
CPC分类号： G01L9/0055 , G01L9/0042
摘要： Disclosed herein is a semiconductor pressure sensor which can improve a withstand voltage across piezoresistance and interconnection layers and a semiconductor substrate. In this semiconductor pressure sensor, a plurality of dot seeds, which are regions for serving as seed crystals for growing monocrystals, are arranged to enclose the piezoresistance, and the interconnection layer is formed to pass through a clearance between adjacent ones of the dot seeds.
摘要翻译：这里公开了一种半导体压力传感器，其能够改善压电阻和互连层和半导体衬底之间的耐受电压。在该半导体压力传感器中，布置作为用于生长单晶的籽晶的区域的多个点状籽粒，以包围压阻，并且互连层形成为通过相邻点状种子之间的间隙。

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