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51. 发明授权

US5828258A Semiconductor device and testing apparatus thereof 失效
公开(公告)号：US5828258A
公开(公告)日：1998-10-27
申请号：US639326
申请日：1996-04-25
申请人： Tsukasa Ooishi , Tomoya Kawagoe , Hideto Hidaka , Mikio Asakura
发明人： Tsukasa Ooishi , Tomoya Kawagoe , Hideto Hidaka , Mikio Asakura
IPC分类号： G11C11/403 , G06F1/04 , G06F1/08 , G11C11/401 , G11C11/406 , G11C11/4076 , G11C29/00 , G11C29/02 , G11C29/12 , G11C29/50
CPC分类号： G11C29/028 , G11C11/4076 , G11C29/02 , G11C29/50 , G11C29/50012 , G11C11/401
摘要： A tester is connected to a signal output terminal provided in a DRAM chip, and a frequency of a clock signal output from an internal timer is monitored. The frequency of the clock signal is varied by changing the combination of 3 bit signals, so as to obtain signals by which the frequency closest to the set value is obtained. A fuse in the internal timer is disconnected to set the frequency of the clock signal so as to obtain the same state as in the case where that signal is applied.

52. 发明授权

US5726940A Semiconductor memory device of which prescribed state of operation is terminated under a prescribed condition and method of operating a semiconductor memory device for terminating prescribed state of operation 失效
标题翻译：在规定条件下终止规定的操作状态的半导体存储器件以及操作半导体存储器件以终止规定操作状态的方法
公开(公告)号：US5726940A
公开(公告)日：1998-03-10
申请号：US833207
申请日：1997-04-14
申请人： Mikio Asakura , Hideto Hidaka , Kiyohiro Furutani
发明人： Mikio Asakura , Hideto Hidaka , Kiyohiro Furutani
IPC分类号： G11C11/401 , G11C29/00 , G11C29/14 , G11C29/34 , G11C29/46 , G11C29/50
CPC分类号： G11C29/46 , G11C29/34 , G11C29/50
摘要： In the semiconductor memory device in accordance with the present invention, when test mode is entered at WCbR+super V.sub.IH +address key timing, the test mode is terminated only at the WCbR+super V.sub.IH +address key timing. Therefore, when refresh is to be started in the test mode, erroneous entrance to another test mode can be prevented, ensuring highly reliable testing. Further, since it is not necessary to take into account the special condition to enter the refreshing operation in the test mode, formation of a test pattern is facilitated.
摘要翻译：在根据本发明的半导体存储器件中，当以WCbR +超VIH +地址键定时输入测试模式时，测试模式仅在WCbR +超级VIH +地址键定时终止。因此，当在测试模式下开始刷新时，可以防止对另一测试模式的错误进入，确保高度可靠的测试。此外，由于不需要考虑在测试模式中进入刷新操作的特殊条件，因此便于形成测试图案。

53. 发明授权

US5708610A Semiconductor memory device and semiconductor device 失效
标题翻译：半导体存储器件和半导体器件
公开(公告)号：US5708610A
公开(公告)日：1998-01-13
申请号：US602643
申请日：1996-02-16
申请人： Yasuhiko Okasaka , Mikio Asakura , Hideto Hidaka , Masaaki Ura , Fukashi Morishita
发明人： Yasuhiko Okasaka , Mikio Asakura , Hideto Hidaka , Masaaki Ura , Fukashi Morishita
IPC分类号： H01L21/8242 , G11C5/14 , G11C11/4074 , G11C11/4076 , H01L27/02 , H01L27/108
CPC分类号： H01L27/0288 , G11C11/4074 , G11C11/4076 , G11C5/14
摘要： For each of pads for control clock signals and address signals included in a DRAM, an n type well region is provided, and each n type well region is connected to an upper power supply means only by means of a first lower power supply line. Therefore, compared with the conventional device in which n type wells are connected to each other by a second lower power supply line, current flowing from the resistance element in a p type well to the upper power supply line is reduced. Therefore, damage to the resistance element 8 can be prevented, and surge immunity of the DRAM is increased.
摘要翻译：对于包括在DRAM中的控制时钟信号和地址信号的每个焊盘，提供n型阱区，并且每个n型阱区仅通过第一较低电源线连接到上电源装置。因此，与通过第二低电源线连接n个型阱的常规装置相比，减小了从p型阱中的电阻元件流向上部电源线的电流。因此，可以防止对电阻元件8的损坏，并且DRAM的浪涌抗扰度增加。

54. 发明授权

US06690241B2 Ring oscillator having variable capacitance circuits for frequency adjustment 有权
标题翻译：环形振荡器具有用于频率调节的可变电容电路
公开(公告)号：US06690241B2
公开(公告)日：2004-02-10
申请号：US09539892
申请日：2000-03-31
申请人： Tsukasa Ooishi , Tomoya Kawagoe , Hideto Hidaka , Mikio Asakura
发明人： Tsukasa Ooishi , Tomoya Kawagoe , Hideto Hidaka , Mikio Asakura
IPC分类号： H03B502
CPC分类号： G11C29/028 , G11C11/401 , G11C11/4076 , G11C29/02 , G11C29/50 , G11C29/50012
摘要： A tester is connected to a signal output terminal provided in a DRAM chip, and a frequency of a clock signal output from an internal timer is monitored. The frequency of the clock signal is varied by changing the combination of 3 bit signals, so as to obtain signals by which the frequency closest to the set value is obtained. A fuse in the internal timer is disconnected to set the frequency of the clock signal so as to obtain the same state as in the case where that signal is applied. The internal timer includes an oscillator formed of a plurality of inverters connected in ring shape and a variable capacitance circuit for each inverter. Each variable capacitance circuit includes a plurality of sets of transfer gates, fuses and capacitors connected between the output node of the corresponding inverter and a prescribed potential line.
摘要翻译：测试器连接到设置在DRAM芯片中的信号输出端子，并且监视从内部定时器输出的时钟信号的频率。通过改变3位信号的组合来改变时钟信号的频率，以获得最接近设定值的频率的信号。内部定时器中的保险丝断开以设置时钟信号的频率，以获得与施加该信号的情况相同的状态。内部定时器包括由环形连接的多个逆变器和每个逆变器的可变电容电路构成的振荡器。每个可变电容电路包括连接在相应逆变器的输出节点和规定电位线之间的多组传输门，熔丝和电容器。

55. 发明授权

US6091268A Potential detecting circuit and semiconductor integrated circuit 失效
标题翻译：电位检测电路和半导体集成电路
公开(公告)号：US6091268A
公开(公告)日：2000-07-18
申请号：US055314
申请日：1998-04-06
申请人： Tsukasa Ooishi , Hideto Hidaka , Mikio Asakura
发明人： Tsukasa Ooishi , Hideto Hidaka , Mikio Asakura
IPC分类号： G01R31/28 , G01R19/165 , G01R31/3185 , G05F1/10 , H03K5/08 , H03K5/153
CPC分类号： H03K5/08
摘要： A constant current source (1) is provided between a power supply (.sup.V CC) and an intermediate node (N1) and supplies a reference current (IR) which is a constant current between the power supply (.sup.V CC) and the intermediate node (N1). A variable resistor (2) is provided between the intermediate node (N1) and a comparison potential (VL) and its resistance value can be set to a desired value. A current flowing in the variable resistor (2) is a comparison current (IC). An amplifier (3) has an input connected to the intermediate node (N1) and amplifies a potential from the intermediate node (N1) to output a level detection signal (GE). Having this configuration, a potential detecting circuit which ensures a stable and controllable detection level is provided.
摘要翻译：在电源（VCC）和中间节点（N1）之间提供恒流源（1），并且在电源（VCC）和中间节点（N1）之间提供作为恒定电流的参考电流（IR）。在中间节点（N1）和比较电位（VL）之间设置可变电阻器（2），其电阻值可以设定为期望值。在可变电阻器（2）中流动的电流是比较电流（IC）。放大器（3）具有连接到中间节点（N1）的输入并放大来自中间节点（N1）的电位以输出电平检测信号（GE）。具有这种配置，提供了确保稳定和可控的检测水平的电位检测电路。

56. 发明授权

US5509132A Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and operating method thereof 失效
标题翻译：具有集成在同一芯片上的作为高速缓存存储器的SRAM的半导体存储器件及其操作方法
公开(公告)号：US5509132A
公开(公告)日：1996-04-16
申请号：US283487
申请日：1994-08-01
申请人： Yoshio Matsuda , Kazuyasu Fujishima , Hideto Hidaka , Mikio Asakura
发明人： Yoshio Matsuda , Kazuyasu Fujishima , Hideto Hidaka , Mikio Asakura
IPC分类号： G06F12/08 , G11C7/10 , G11C8/00 , G11C11/401 , G11C11/41
CPC分类号： G06F12/0893 , G11C7/1051
摘要： A cache DRAM (100) includes a DRAM memory array (11) accessed by a row address signal and a column address signal, an SRAM memory array (21) accessed by the column address signal, and an ECC circuit (30). The DRAM memory array (11) is divided into a plurality of blocks (B1 to B64), each including a plurality of columns. The SRAM memory array (21) includes 4 ways (W1 to W4). In determining a cache hit/cache miss, a column address signal is inputted. Consequently, the SRAM memory array (21) is accessed and data are read from each of the ways. When a cache hit occurs, one way is selected in response to an externally applied way address signal, and data from that way are outputted. When a cache miss occurs, the column address signal is latched and the row address signal is applied. The DRAM array (11) is accessed in accordance with the row address signal and the latched column address signal.
摘要翻译：缓存DRAM（100）包括通过行地址信号和列地址信号访问的DRAM存储器阵列（11），由列地址信号访问的SRAM存储器阵列（21）和ECC电路（30）。 DRAM存储器阵列（11）被分成多个块（B1至B64），每个块包括多个列。 SRAM存储器阵列（21）包括4路（W1至W4）。在确定高速缓存命中/高速缓存未命中时，输入列地址信号。因此，访问SRAM存储器阵列（21）并且从每种方式读取数据。当发生高速缓存命中时，响应于外部施加的方式地址信号选择一种方式，并且从该方式输出数据。当发生高速缓存未命中时，锁存列地址信号并应用行地址信号。根据行地址信号和锁存列地址信号来访问DRAM阵列（11）。

57. 发明授权

US5226139A Semiconductor memory device with a built-in cache memory and operating method thereof 失效
标题翻译：具有内置缓存存储器的半导体存储器件及其操作方法
公开(公告)号：US5226139A
公开(公告)日：1993-07-06
申请号：US637872
申请日：1991-01-08
申请人： Kazuyasu Fujishima , Yoshio Matsuda , Hideto Hidaka , Mikio Asakura
发明人： Kazuyasu Fujishima , Yoshio Matsuda , Hideto Hidaka , Mikio Asakura
IPC分类号： G06F9/38 , G06F12/08 , G11C11/401 , G11C11/408 , G11C11/4096 , G11C11/41
CPC分类号： G06F9/3824 , G06F12/0893 , G11C11/408 , G11C11/4096
摘要： A semiconductor memory device with a built-in cache memory comprises a memory cell array (1). The memory cell array (1) is divided into a plurality of blocks (B1 to B16). Each block is divided into a plurality of sub blocks each having a plurality of columns. At the time of a cache hit, block address signals (B0, B1) and a column address signal (CA) are simultaneously applied. Any of the plurality of blocks (B1 to B16) is selected in response to the block address signals (B0, B1). At the same time, any of the plurality of registers (16a) corresponding to the selected block is selected in response to the column address signal (CA). The data stored in the register (16a) is thereby read out at a high speed
摘要翻译：具有内置高速缓冲存储器的半导体存储器件包括存储单元阵列（1）。存储单元阵列（1）被分成多个块（B1〜B16）。每个块被分成多个子块，每个子块具有多个列。在缓存命中时，同时施加块地址信号（B0，B1）和列地址信号（CA）。响应于块地址信号（B0，B1）选择多个块（B1至B16）中的任一个。同时，响应于列地址信号（CA）选择对应于所选块的多个寄存器（16a）中的任何一个。因此，存储在寄存器（16a）中的数据被高速读出

58. 发明授权

US5179687A Semiconductor memory device containing a cache and an operation method thereof 失效
标题翻译：包含高速缓存的半导体存储器件及其操作方法
公开(公告)号：US5179687A
公开(公告)日：1993-01-12
申请号：US542682
申请日：1990-06-25
申请人： Hideto Hidaka , Kazuyasu Fujishima , Yoshio Matsuda , Mikio Asakura
发明人： Hideto Hidaka , Kazuyasu Fujishima , Yoshio Matsuda , Mikio Asakura
IPC分类号： G06F12/08 , G11C11/4096
CPC分类号： G06F12/0893 , G11C11/4096
摘要： A DRAM for use in a simple cache memory system comprises a memory cell array divided into a plurality of blocks, a plurality of data registers provided corresponding to the respective blocks of the array for latching memory cell data of the corresponding blocks, and a selector responsive to a row address strobe signal for selecting access to either the data registers or the memory cell array. Upon cache hit, the row address strobe signal is inactivated to cause the selector to select the access to the data registers. Upon cache miss, the row address strobe signal is activated to cause the selector to select the access to the memory cell array.
摘要翻译：用于简单高速缓冲存储器系统的DRAM包括被划分成多个块的存储单元阵列，与阵列的各个块对应地提供的多个数据寄存器，用于锁存相应块的存储单元数据，以及响应于选择器用于选择对数据寄存器或存储单元阵列的访问的行地址选通信号。缓存命中后，行地址选通信号被取消激活，使选择器选择对数据寄存器的访问。在缓存未命中时，行地址选通信号被激活以使选择器选择对存储单元阵列的访问。

59. 发明授权

US08000133B2 Thin film magnetic memory device capable of conducting stable data read and write operations 有权
标题翻译：能够进行稳定数据读写操作的薄膜磁存储器件
公开(公告)号：US08000133B2
公开(公告)日：2011-08-16
申请号：US12755018
申请日：2010-04-06
申请人： Hideto Hidaka
发明人： Hideto Hidaka
IPC分类号： G11C11/14 , G11C11/15 , G11C7/02
CPC分类号： H01L27/228 , G11C7/14 , G11C11/16 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , H01L27/224
摘要： A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provided between the fixed and free magnetic layers in a tunnel junction region. In the free magnetic layer, a region corresponding to an easy axis region having characteristics desirable as a memory cell is used as the tunnel junction region. A hard axis region having characteristics undesirable as a memory cell is not used as a portion of the tunnel magnetic resistive element.
摘要翻译：形成磁存储单元的隧道磁阻元件包括具有固定方向的固定磁场的固定磁性层，由施加的磁场磁化的自由磁性层和作为绝缘膜的隧道势垒，所述绝缘膜设置在固定和隧道结区域中的自由磁性层。在自由磁性层中，使用对应于具有作为存储单元的特性的容易轴区域的区域作为隧道结区域。具有作为存储单元的不期望的特性的硬轴区域不被用作隧道磁阻元件的一部分。

60. 发明授权

US07911871B2 Semiconductor memory device operational processing device and storage system 有权
标题翻译：半导体存储器件操作处理装置和存储系统
公开(公告)号：US07911871B2
公开(公告)日：2011-03-22
申请号：US12461743
申请日：2009-08-24
申请人： Hideto Hidaka
发明人： Hideto Hidaka
IPC分类号： G11C8/00
CPC分类号： G11C11/005
摘要： A thin film magnetic memory includes a size-variable Read Only Memory (ROM) region and a size-variable Random Access Memory (RAM) coupled to different ports for parallel access to the ports, respectively. A memory system allowing fast and efficient data transfer can be achieved.
摘要翻译：薄膜磁存储器包括大小可变只读存储器（ROM）区域和耦合到不同端口的大小可变随机存取存储器（RAM），用于并行地访问端口。可以实现快速高效的数据传输的存储器系统。

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