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51. 发明申请

US20090294633A1 Image sensor using photo-detecting molecule and method of operating the same 有权
标题翻译：使用光检测分子的图像传感器及其操作方法
公开(公告)号：US20090294633A1
公开(公告)日：2009-12-03
申请号：US12385122
申请日：2009-03-31
申请人： Kwang-soo Seol , Yoon-dong Park
发明人： Kwang-soo Seol , Yoon-dong Park
IPC分类号： H01L27/146 , H01L31/0256 , H01L51/46
CPC分类号： H01L27/14603 , H01L27/14627 , H01L27/307 , H01L51/0043 , H01L51/0073 , H01L51/424 , H01L51/4246 , Y02E10/549
摘要： Provided is an image sensor using a photo-detecting molecule and a method of operating the image sensor. The image sensor may include a plurality of first electrodes disposed parallel to each other and a plurality of second electrodes disposed parallel to each other in a direction perpendicular to the first electrodes and above the first electrodes, and a plurality of subpixels formed in regions where the first electrodes cross the second electrodes. Each of the subpixels may comprise a photo-detecting molecule layer that may generate charges by absorbing light having a certain wavelength, a charge generation layer that may form a plurality of secondary electrons by receiving the charges from the photo-detecting molecule layer when a known voltage is applied between the first electrodes and the second electrodes, and a variable resistance layer, an electrical state of which is changed by receiving the secondary electrons generated from the charge generation layer.
摘要翻译：提供了使用光检测分子的图像传感器和操作图像传感器的方法。图像传感器可以包括彼此平行设置的多个第一电极和在垂直于第一电极并且在第一电极上方彼此平行设置的多个第二电极，以及多个子像素，其形成在第一电极与第二电极交叉。每个子像素可以包括可以通过吸收具有一定波长的光而产生电荷的光检测分子层，电荷产生层可以通过从已知的光检测分子层接收电荷而形成多个二次电子在第一电极和第二电极之间施加电压，并且通过接收从电荷产生层产生的二次电子而改变其电状态的可变电阻层。

52. 发明申请

US20090256941A1 Image sensor with sensing transistor having two gates and method of operating the same 有权
标题翻译：具有两个门的感测晶体管的图像传感器及其操作方法
公开(公告)号：US20090256941A1
公开(公告)日：2009-10-15
申请号：US12222506
申请日：2008-08-11
申请人： Kwang-soo Seol , Sung-il Park
发明人： Kwang-soo Seol , Sung-il Park
IPC分类号： H01L33/00 , H04N3/14
CPC分类号： H01L27/14609 , H01L27/14612 , H04N5/355 , H04N5/35509 , H04N5/3745
摘要： Provided is an image sensor including a sensing transistor having two gates and a method of operating the image sensor. The image sensor may include a photoelectric conversion device, a sensing transistor which may have a first gate connected to a floating diffusion region in which charges generated from the photoelectric conversion region are stored and a second gate separated from the first gate, a reset transistor that may be connected to the floating diffusion region and may reset a potential of the floating diffusion region, a control voltage source that may supply a control applied to the second gate, and a column output line which may be connected to a source of the sensing transistor.
摘要翻译：提供了一种图像传感器，其包括具有两个门的感测晶体管和操作图像传感器的方法。图像传感器可以包括光电转换装置，感测晶体管，其可以具有连接到浮动扩散区域的第一栅极，其中存储从光电转换区域产生的电荷和从第一栅极分离的第二栅极;复位晶体管，可以连接到浮动扩散区域并且可以复位浮动扩散区域的电位，可以提供施加到第二栅极的控制的控制电压源和可以连接到感测晶体管的源极的列输出线。

53. 发明申请

US20070257297A1 Memory device having nanocrystals and methods of manufacturing the same 有权
标题翻译：具有纳米晶体的记忆装置及其制造方法
公开(公告)号：US20070257297A1
公开(公告)日：2007-11-08
申请号：US11711714
申请日：2007-02-28
申请人： Kwang-soo Seol , Seong-jae Choi , Jae-young Choi , Yo-sep Min , Eun-joo Jang , Dong-kee Yi
发明人： Kwang-soo Seol , Seong-jae Choi , Jae-young Choi , Yo-sep Min , Eun-joo Jang , Dong-kee Yi
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/51 , H01L29/513 , H01L29/7881 , Y10S977/721 , Y10S977/785 , Y10S977/943
摘要： The memory device includes a source region and a drain region in a substrate and spaced apart from each other; a memory cell formed on a surface of the substrate, wherein the memory cell connects the source region and the drain region and includes a plurality of nanocrystals; a control gate formed on the memory cell. The memory cell includes a first tunneling oxide layer formed on the substrate; a second tunneling oxide layer formed on the first tunneling oxide layer; and a control oxide layer formed on the second tunneling oxide layer. The control oxide layer includes the nanocrystals. The second tunneling oxide layer, having an aminosilane group the increases electrostatic attraction, may be hydrophilic, enabling the formation of a monolayer of the nanocrystals.
摘要翻译：该存储装置包括一基板中的一源极区和一漏极区，彼此间隔开; 形成在所述基板的表面上的存储单元，其中所述存储单元连接所述源极区域和所述漏极区域并且包括多个纳米晶体; 形成在存储单元上的控制栅极。存储单元包括形成在基板上的第一隧穿氧化层; 形成在第一隧道氧化物层上的第二隧穿氧化物层; 以及形成在第二隧道氧化物层上的控制氧化物层。控制氧化物层包括纳米晶体。具有增加静电吸引力的氨基硅烷基团的第二隧道氧化物层可以是亲水性的，能够形成纳米晶体的单层。

54. 发明授权

US08441062B2 Nonvolatile memory devices having memory cell transistors therein with lower bandgap source/drain regions 有权
标题翻译：具有其中具有较低带隙源极/漏极区域的存储单元晶体管的非易失性存储器件
公开(公告)号：US08441062B2
公开(公告)日：2013-05-14
申请号：US12974542
申请日：2010-12-21
申请人： Byung-kyu Cho , Kwang-soo Seol , Sung-hoi Hur , Jung-dal Choi
发明人： Byung-kyu Cho , Kwang-soo Seol , Sung-hoi Hur , Jung-dal Choi
IPC分类号： H01L29/772
CPC分类号： H01L27/11521 , H01L27/11524
摘要： Nonvolatile memory devices include a plurality of nonvolatile memory cell transistors having respective channel regions within a semiconductor layer formed of a first semiconductor material and respective source/drain regions formed of a second semiconductor material, which has a smaller bandgap relative to the first semiconductor material. The source/drain regions can form non-rectifying junctions with the channel regions. The source/drain regions may include germanium (e.g., Ge or SiGe regions), the semiconductor layer may be a P-type silicon layer and the source/drain regions of the plurality of nonvolatile memory cell transistors may be P-type germanium or P-type silicon germanium.
摘要翻译：非易失性存储器件包括多个非易失性存储单元晶体管，其在由第一半导体材料形成的半导体层内的相应沟道区和由第二半导体材料形成的相应的源极/漏极区相互相对于第一半导体材料具有较小的带隙。源极/漏极区域可以与沟道区域形成非整流结。源极/漏极区域可以包括锗（例如Ge或SiGe区域），半导体层可以是P型硅层，并且多个非易失性存储单元晶体管的源极/漏极区域可以是P型锗或P 型硅锗。

55. 发明授权

US08053302B2 Non-volatile memory device and method of manufacturing same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US08053302B2
公开(公告)日：2011-11-08
申请号：US12461416
申请日：2009-08-11
申请人： Kwang-soo Seol , Yoon-dong Park
发明人： Kwang-soo Seol , Yoon-dong Park
IPC分类号： H01L21/8239
CPC分类号： H01L27/11578 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11551 , H01L27/11556 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： A non-volatile memory device and a method of manufacturing the non-volatile memory device are provided. At least one first semiconductor layer and at least one second semiconductor layer are disposed. At least one control gate electrode is disposed between the at least one first semiconductor layer and the at least one second semiconductor layer. At least one first layer selection line is capacitively coupled to the at least one first semiconductor layer. At least one second layer selection line is capacitively coupled to the at least one second semiconductor layer.
摘要翻译：提供了一种非易失性存储器件和制造该非易失性存储器件的方法。设置至少一个第一半导体层和至少一个第二半导体层。至少一个控制栅电极设置在至少一个第一半导体层和至少一个第二半导体层之间。至少一个第一层选择线电容耦合到至少一个第一半导体层。至少一个第二层选择线电容耦合到至少一个第二半导体层。

56. 发明申请

US20100237312A1 Nonvolatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US20100237312A1
公开(公告)日：2010-09-23
申请号：US12659175
申请日：2010-02-26
申请人： Kwang-soo Seol , Yoon-dong Park , Deok-kee Kim , Sang-jun Choi
发明人： Kwang-soo Seol , Yoon-dong Park , Deok-kee Kim , Sang-jun Choi
IPC分类号： H01L45/00
CPC分类号： H01L27/2445 , H01L27/2436 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/146 , H01L45/147
摘要： The nonvolatile memory device includes at least one pair of first electrode lines, at least one device structure disposed between the at least one pair of first electrode lines and a dielectric layer disposed between the at least one device structure and the at least one pair of first electrode lines. The at least one device structure includes a second electrode line including a first conductive type semiconductor, a resistance changing material layer adjacent to the second electrode line, a channel adjacent to the resistance changing material layer and including a second conductive type semiconductor different from the first conductive type semiconductor and a third electrode line adjacent to the channel and including the first conductive type semiconductor.
摘要翻译：非易失性存储器件包括至少一对第一电极线，设置在至少一对第一电极线之间的至少一个器件结构和设置在该至少一个器件结构与至少一对第一电极线之间的电介质层电极线。所述至少一个器件结构包括第二电极线，所述第二电极线包括第一导电类型半导体，与所述第二电极线相邻的电阻改变材料层，与所述电阻变化材料层相邻的通道，并且包括不同于所述第一导电类型的第一导电型半导体导电型半导体和与沟道相邻的第三电极线，并且包括第一导电型半导体。

57. 发明申请

US20090244980A1 Method for reducing lateral movement of charges and memory device thereof 有权
标题翻译：减少电荷横向运动的方法及其记忆装置
公开(公告)号：US20090244980A1
公开(公告)日：2009-10-01
申请号：US12382790
申请日：2009-03-24
申请人： Kwang-soo Seol , Young-gu Jin , Yoon-dong Park
发明人： Kwang-soo Seol , Young-gu Jin , Yoon-dong Park
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C16/3409 , G11C16/344 , G11C16/3454
摘要： Provided is a method and device for reducing lateral movement of charges. The method may include pre-programming at least one memory cell that is in an erased state by applying a pre-programming voltage to the at least one memory cell to have a narrower distribution of threshold voltages than the at least one erased state memory cell and verifying that the pre-programmed memory cell is in the pre-programmed state using a negative effective verifying voltage.
摘要翻译：提供一种用于减少电荷的横向移动的方法和装置。该方法可以包括通过对至少一个存储器单元施加预编程电压以使得具有比所述至少一个擦除状态存储器单元更窄的阈值电压分布来对处于擦除状态的至少一个存储器单元进行预编程，以及使用负的有效验证电压来验证预编程存储器单元是否处于预编程状态。

58. 发明授权

US07501680B2 Memory device having nanocrystals in memory cell 有权
标题翻译：在存储器单元中具有纳米晶体的存储器件
公开(公告)号：US07501680B2
公开(公告)日：2009-03-10
申请号：US11711714
申请日：2007-02-28
申请人： Kwang-soo Seol , Seong-jae Choi , Jae-young Choi , Yo-sep Min , Eun-joo Jang , Dong-kee Yi
发明人： Kwang-soo Seol , Seong-jae Choi , Jae-young Choi , Yo-sep Min , Eun-joo Jang , Dong-kee Yi
IPC分类号： H01L21/336
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/51 , H01L29/513 , H01L29/7881 , Y10S977/721 , Y10S977/785 , Y10S977/943
摘要： The memory device includes a source region and a drain region in a substrate and spaced apart from each other; a memory cell formed on a surface of the substrate, wherein the memory cell connects the source region and the drain region and includes a plurality of nanocrystals; a control gate formed on the memory cell. The memory cell includes a first tunneling oxide layer formed on the substrate; a second tunneling oxide layer formed on the first tunneling oxide layer; and a control oxide layer formed on the second tunneling oxide layer. The control oxide layer includes the nanocrystals. The second tunneling oxide layer, having an aminosilane group the increases electrostatic attraction, may be hydrophilic, enabling the formation of a monolayer of the nanocrystals.
摘要翻译：该存储装置包括一基板中的一源极区和一漏极区，彼此间隔开; 形成在所述基板的表面上的存储单元，其中所述存储单元连接所述源极区域和所述漏极区域并且包括多个纳米晶体; 形成在存储单元上的控制栅极。存储单元包括形成在基板上的第一隧穿氧化层; 形成在第一隧道氧化物层上的第二隧穿氧化物层; 以及形成在第二隧道氧化物层上的控制氧化物层。控制氧化物层包括纳米晶体。具有增加静电吸引力的氨基硅烷基团的第二隧道氧化物层可以是亲水性的，能够形成纳米晶体的单层。

59. 发明申请

US20080131710A1 Charge trap layer for a charge trap semiconductor memory device and method of manufacturing the same 有权
标题翻译：用于电荷陷阱半导体存储器件的电荷陷阱层及其制造方法
公开(公告)号：US20080131710A1
公开(公告)日：2008-06-05
申请号：US11987425
申请日：2007-11-30
申请人： Kwang-soo Seol , Yo-sep Min , Sang-min Shin
发明人： Kwang-soo Seol , Yo-sep Min , Sang-min Shin
IPC分类号： B32B15/04 , H01L21/31 , H01L29/792
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L29/42324 , H01L29/4234 , H01L29/7883 , Y10T428/31678
摘要： Provided are a charge trap semiconductor memory device including a charge trap layer on a semiconductor substrate, and a method of manufacturing the charge trap semiconductor memory device. The method includes: (a) coating a first precursor material on a surface of a semiconductor substrate to be deposited and oxidizing the first precursor material to form a first layer formed of an insulating material; (b) coating a second precursor material formed of metallicity on the first layer; (c) supplying the first precursor material on the surface coated with the second precursor material to substitute the second precursor material with the first precursor material; and (d) oxidizing the first and second precursor materials obtained in (c) to form a second layer formed of an insulating material and a metal impurity, and (a) through (d) are performed at least one time to form a charge trap layer having a structure in which the metal impurity is isolated in the insulating material.
摘要翻译：提供了一种在半导体衬底上包括电荷陷阱层的电荷陷阱半导体存储器件，以及制造电荷阱半导体存储器件的方法。该方法包括：（a）在要沉积的半导体衬底的表面上涂覆第一前体材料并氧化第一前体材料以形成由绝缘材料形成的第一层; （b）在第一层上涂覆由金属性形成的第二前体材料; （c）在涂覆有第二前体材料的表面上提供第一前体材料以用第一前体材料代替第二前体材料; 和（d）氧化由（c）中得到的第一和第二前体材料以形成由绝缘材料和金属杂质形成的第二层，并且（a）至（d）至少进行一次以形成电荷阱具有金属杂质在绝缘材料中隔离的结构的层。

60. 发明申请

US20080023744A1 Nonvolatile semiconductor memory device and method of manufacturing the same 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20080023744A1
公开(公告)日：2008-01-31
申请号：US11723081
申请日：2007-03-16
申请人： Sang-min Shin , Kwang-soo Seol , Young-gu Jin
发明人： Sang-min Shin , Kwang-soo Seol , Young-gu Jin
IPC分类号： H01L29/94
CPC分类号： H01L29/792 , H01L29/40117 , H01L29/42332 , H01L29/42348 , H01L29/513 , H01L29/7881
摘要： Provided are a nonvolatile semiconductor memory device and a method of manufacturing the same. The nonvolatile semiconductor memory device may include a tunnel insulating layer formed on a semiconductor substrate, a charge trap layer including a dielectric layer doped with a transition metal formed on the tunnel insulating layer, a blocking insulating layer formed on the charge trap layer, and a gate electrode formed on the blocking insulating layer. The dielectric layer may be a high-k dielectric layer, for example, a HfO2 layer. Thus, the data retention characteristics of the nonvolatile semiconductor memory device may be improved because a deeper charge trap may be formed by doping the high-k dielectric layer with a transition metal.
摘要翻译：提供一种非易失性半导体存储器件及其制造方法。非易失性半导体存储器件可以包括形成在半导体衬底上的隧道绝缘层，包含掺杂在隧道绝缘层上形成的过渡金属的电介质层的电荷陷阱层，形成在电荷陷阱层上的阻挡绝缘层，以及栅电极形成在阻挡绝缘层上。介电层可以是高k电介质层，例如HfO 2层。因此，可以通过用过渡金属掺杂高k电介质层来形成更深的电荷陷阱来提高非易失性半导体存储器件的数据保持特性。

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