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51. 发明授权

US07321958B2 System and method for sharing memory by heterogeneous processors 有权
标题翻译：异构处理器共享内存的系统和方法
公开(公告)号：US07321958B2
公开(公告)日：2008-01-22
申请号：US10697897
申请日：2003-10-30
申请人： Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle
发明人： Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle
IPC分类号： G06F12/08
CPC分类号： G06F12/0284 , G06F13/1652
摘要： A system for sharing memory by heterogeneous processors, each of which is adapted to process its own instruction set, is presented. A common bus is used to couple the common memory to the various processors. In one embodiment, a cache for more than one of the processors is stored in the shared memory. In another embodiment, some of the processors include a local memory area that is mapped to the shared memory pool. In yet another embodiment, local memory included on one or more of the processors is partially shared so that some of the local memory is mapped to the shared memory area, while remaining memory in the local memory is private to the particular processor.
摘要翻译：提出了一种用于通过异构处理器共享存储器的系统，每个处理器适于处理其自己的指令集。公共总线用于将公共存储器耦合到各种处理器。在一个实施例中，用于多于一个处理器的高速缓存存储在共享存储器中。在另一个实施例中，一些处理器包括映射到共享存储器池的本地存储器区域。在另一个实施例中，包括在一个或多个处理器中的本地存储器被部分地共享，使得一些本地存储器被映射到共享存储器区域，而本地存储器中的剩余存储器对于特定处理器是专用的。

52. 发明授权

US07299372B2 Hierarchical management for multiprocessor system with real-time attributes 失效
标题翻译：具有实时属性的多处理器系统的分层管理
公开(公告)号：US07299372B2
公开(公告)日：2007-11-20
申请号：US10912481
申请日：2004-08-05
申请人： Jeffrey Douglas Brown , Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , Michael Fan Wang
发明人： Jeffrey Douglas Brown , Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , Michael Fan Wang
IPC分类号： G06F1/28
CPC分类号： G06F1/3203
摘要： The present invention provides for controlling the power consumption of an element. A first power control command is issued by software for the element. It is determined if the power control command corresponds to an allowable power control state for that element as defined by the hardware. If the power control command is not an allowable power control state for that element, the hardware sets the power control at a higher level than the power control state issued by the software. The software is real time software, and the software also sets minimally acceptable activity control states. A hierarchy of power consumption is defined for different elements of a chip by software, which provides the minimum level of power consumption by any element or sub-element on a chip.
摘要翻译：本发明提供用于控制元件的功耗。第一个功率控制命令由该元件的软件发出。确定功率控制命令是否对应于由硬件定义的该元件的容许功率控制状态。如果功率控制命令不是该元件的允许功率控制状态，则硬件将功率控制设置在比由软件发出的功率控制状态更高的水平。该软件是实时软件，软件还设置了最低限度可接受的活动控制状态。通过软件为芯片的不同元件定义功耗层级，其通过芯片上的任何元件或子元件提供最低功耗水平。

53. 发明授权

US07299371B2 Hierarchical management for multiprocessor system 失效
标题翻译：多处理器系统的分层管理
公开(公告)号：US07299371B2
公开(公告)日：2007-11-20
申请号：US10912479
申请日：2004-08-05
申请人： Micahel Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle
发明人： Micahel Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle
IPC分类号： G06F1/28
CPC分类号： G06F1/3203
摘要： The present invention provides for controlling the power consumption of an element. A first power control command is issued by software for the element. It is determined if the power control command corresponds to an allowable power control state for that element as defined by the hardware. If the power control command is not an allowable power control state for that element, the hardware sets the power control at a higher level than the power control state issued by the software. A hierarchy of power consumption is defined for different elements of a chip by software, which provides the minimum level of power consumption by any element or sub-element on a chip.
摘要翻译：本发明提供用于控制元件的功耗。第一个功率控制命令由该元件的软件发出。确定功率控制命令是否对应于由硬件定义的该元件的容许功率控制状态。如果功率控制命令不是该元件的允许功率控制状态，则硬件将功率控制设置在比由软件发出的功率控制状态更高的水平。通过软件为芯片的不同元件定义功耗层级，其通过芯片上的任何元件或子元件提供最低功耗水平。

54. 发明授权

US07279996B2 Method of functionality testing for a ring oscillator 失效
公开(公告)号：US07279996B2
公开(公告)日：2007-10-09
申请号：US11204408
申请日：2005-08-16
申请人： David William Boerstler , Eskinder Hailu , Harm Peter Hofstee , John Samuel Liberty
发明人： David William Boerstler , Eskinder Hailu , Harm Peter Hofstee , John Samuel Liberty
IPC分类号： H03K3/03
CPC分类号： H03K3/0315 , H03K5/133
摘要： A method and apparatus is provided for testing the logic functionality and electrical continuity of a ring oscillator comprising an odd number of inverters connected to form a closed loop. In the method and apparatus, a known value is forced through the ring oscillator, to test the complete circuit path thereof. Thus, a low overhead deterministic test of the functionality of the ring oscillator is provided. In a useful embodiment of the invention, a method is provided for testing functionality and electrical continuity in a ring oscillator, wherein a first test device is inserted between the input of a first inverter and the output of an adjacent second inverter. The first test device is then operated to apply first and second test bits as input test signals to the first inverter input. The embodiment further comprises detecting the response to the applied first and second test bit signals at the output of the second inverter, and using the detected responses in providing an evaluation of functionality of the ring oscillator.

55. 发明授权

US07233212B2 Oscillator array with row and column control 有权
标题翻译：具有行和列控制的振荡器阵列
公开(公告)号：US07233212B2
公开(公告)日：2007-06-19
申请号：US11095895
申请日：2005-03-31
申请人： David William Boerstler , Eskinder Hailu , Harm Peter Hofstee , John Samuel Liberty
发明人： David William Boerstler , Eskinder Hailu , Harm Peter Hofstee , John Samuel Liberty
IPC分类号： H03B29/00 , H03K3/03
CPC分类号： G06F7/588 , H03K3/0315 , H03K3/84
摘要： A circuit topology which can be used to create an array of individually tuned oscillators operating at different frequencies determined by common control inputs and an easily managed variation in design dimensions of several components is provided. An array of oscillators are provided arranged in columns and rows. Each oscillator in a column is unique from the other oscillators in the column based on number of stages in the oscillator and fanout so that each oscillator will operate at a unique frequency. Oscillators of different columns within the array may differ by a common setting of the selects to these oscillators and the physical ordering of the oscillators in the column to further reduce the possibility of injection locking. A base delay cell provides selects to each column of oscillators such that each column may be programmed to operate at a different frequency from its neighbors.
摘要翻译：提供了一种电路拓扑结构，可用于创建由通用控制输入确定的不同频率运行的单独调谐的振荡器阵列，以及易于管理的多个组件的设计尺寸变化。提供了一列列和列排列的振荡器阵列。列中的每个振荡器都基于列中的其他振荡器是独特的，基于振荡器和扇出的级数，使得每个振荡器将以唯一的频率工作。阵列中不同列的振荡器可能会通过对这些振荡器的选择的共同设置以及列中的振荡器的物理顺序而不同，以进一步降低注入锁定的可能性。基本延迟单元为每列振荡器提供选择，使得每列可被编程为以与其邻居不同的频率工作。

56. 发明授权

US07103748B2 Memory management for real-time applications 失效
标题翻译：内存管理用于实时应用
公开(公告)号：US07103748B2
公开(公告)日：2006-09-05
申请号：US10318541
申请日：2002-12-12
申请人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong
IPC分类号： G06F12/12
CPC分类号： G06F12/1027 , G06F12/126
摘要： Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.
摘要翻译：计算机系统中的存储器管理通过防止地址转换信息的一部分被替换为高速缓冲存储器中的其他类型的地址转换信息而被改进，该高速缓冲存储器被保留用于存储用于CPU更快速访问的这种地址转换信息。这样，CPU可以识别存储在高速缓存中的地址转换信息的子集。

57. 发明授权

US06981072B2 Memory management in multiprocessor system 失效
标题翻译：多处理器系统中的内存管理
公开(公告)号：US06981072B2
公开(公告)日：2005-12-27
申请号：US10455169
申请日：2003-06-05
申请人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , James Allan Kahle , David Shippy , Thuong Quang Truong
IPC分类号： G06F12/10 , G06F13/00 , G06F13/28
CPC分类号： G06F13/28 , G06F12/1081
摘要： A system and a method are provided for improving memory management in a multiprocessor system. A direct memory access (DMA) operation is set up for a first processor. A DMA effective address is translated to a virtual address. The virtual address is translated to a physical address, which is used to access a memory hierarchy of the multiprocessor system.
摘要翻译：提供了一种用于改善多处理器系统中的存储器管理的系统和方法。为第一个处理器设置直接存储器访问（DMA）操作。 DMA有效地址转换为虚拟地址。虚拟地址被转换为物理地址，用于访问多处理器系统的存储器层次结构。

58. 发明授权

US06970982B2 Method and system for maintaining coherency in a multiprocessor system by broadcasting TLB invalidated entry instructions 失效
标题翻译：通过广播TLB无效输入指令来在多处理器系统中维持一致性的方法和系统
公开(公告)号：US06970982B2
公开(公告)日：2005-11-29
申请号：US10676540
申请日：2003-10-01
申请人： Erik R. Altman , Peter G. Capek , Michael Karl Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman
发明人： Erik R. Altman , Peter G. Capek , Michael Karl Gschwind , Harm Peter Hofstee , James Allan Kahle , Ravi Nair , Sumedh Wasudeo Sathaye , John-David Wellman
IPC分类号： G06F12/10 , G06F13/00
CPC分类号： G06F12/1027 , G06F2212/682
摘要： A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of processing elements coupled to the shared memory. Each of the plurality of processing elements comprises a processing unit, a direct memory access controller and a plurality of attached processing units. Each direct memory access controller comprises an address translation mechanism thereby enabling each associated attached processing unit to access the shared memory in a restricted manner without an address translation mechanism. Each attached processing unit is configured to issue a request to an associated direct memory access controller to access the shared memory specifying a range of addresses to be accessed as virtual addresses. The associated direct memory access controller is configured to translate the range of virtual addresses into an associated range of physical addresses.
摘要翻译：用于在SMP系统中访问共享存储器的附加处理单元的方法和系统。在一个实施例中，系统包括共享存储器。该系统还包括耦合到共享存储器的多个处理元件。多个处理单元中的每一个包括处理单元，直接存储器存取控制器和多个附加的处理单元。每个直接存储器访问控制器包括地址转换机制，从而使得每个相关联的附属处理单元能够以无限制的方式访问共享存储器，而无需地址转换机制。每个附加的处理单元被配置为向相关联的直接存储器访问控制器发出请求以访问指定要作为虚拟地址访问的地址范围的共享存储器。相关联的直接存储器访问控制器被配置为将虚拟地址的范围转换为相关的物理地址范围。

59. 发明授权

US08838950B2 Security architecture for system on chip 有权
标题翻译：片上系统的安全架构
公开(公告)号：US08838950B2
公开(公告)日：2014-09-16
申请号：US10601374
申请日：2003-06-23
申请人： David John Craft , Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , John Samuel Liberty
发明人： David John Craft , Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , John Samuel Liberty
IPC分类号： G06F21/00 , H04L9/32 , G06F21/53
CPC分类号： G06F21/53 , H04L9/3226 , H04L2209/56
摘要： The present invention provides for authenticating code and/or data and providing a protected environment for execution. The present invention provides for dynamically partitioning and un-partitioning a local store for the authentication of code or data. The local store is partitioned into an isolated and non-isolated section. Code or data is loaded into the isolated section. The code or data is authenticated in the isolated section of the local store. After authentication, the code is executed. After execution, the memory within the isolated region of the attached processor unit is erased, and the attached processor unit de-partitions the isolated section within the local store.
摘要翻译：本发明提供了验证代码和/或数据并提供受保护的环境以供执行。本发明提供了用于对代码或数据的认证的动态分区和分区本地存储。本地商店被划分成一个隔离和非隔离的部分。代码或数据被加载到隔离的部分。代码或数据在本地存储的隔离部分进行身份验证。认证后，执行代码。在执行之后，附着的处理器单元的隔离区域内的存储器被擦除，并且附加的处理器单元对本地存储器内的隔离部分进行分区。

60. 发明授权

US08677136B2 Authenticating messages using cryptographic algorithm constants supplied to a storage-constrained target 失效
标题翻译：使用提供给存储受限目标的加密算法常数验证消息
公开(公告)号：US08677136B2
公开(公告)日：2014-03-18
申请号：US13326489
申请日：2011-12-15
申请人： Daniel Alan Brokenshire , Harm Peter Hofstee , Mohammad Peyravian
发明人： Daniel Alan Brokenshire , Harm Peter Hofstee , Mohammad Peyravian
IPC分类号： H04L9/12
CPC分类号： H04L9/3242
摘要： The present invention provides for authenticating a message. A security function is performed upon the message. The message is sent to a target. The output of the security function is sent to the target. At least one publicly known constant is sent to the target. The received message is authenticated as a function of at least a shared key, the received publicly known constants, the security function, the received message, and the output of the security function. If the output of the security function received by the target is the same as the output generated as a function of at least the received message, the received publicly known constants, the security function, and the shared key, neither the message nor the constants have been altered.
摘要翻译：本发明提供用于认证消息。对消息执行安全功能。该消息被发送到目标。安全功能的输出被发送到目标。至少有一个公认的常数被发送到目标。接收到的消息被认证为至少共享密钥，接收的公知常数，安全功能，接收到的消息和安全功能的输出的功能。如果目标接收到的安全功能的输出与至少作为接收到的消息的函数产生的输出相同，则所接收的公知常数，安全功能和共享密钥，消息和常数都不具有被改变了

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