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51. 发明申请

US20110019495A1 DECODER CIRCUITRY PROVIDING FORWARD AND REVERSE MODES OF MEMORY ARRAY OPERATION AND METHOD FOR BIASING SAME 有权
标题翻译：提供存储器阵列操作的前向和反向模式的解码器电路及其偏移方法
公开(公告)号：US20110019495A1
公开(公告)日：2011-01-27
申请号：US12895523
申请日：2010-09-30
申请人： Roy E. Scheuerlein , Luca G. Fasoli
发明人： Roy E. Scheuerlein , Luca G. Fasoli
IPC分类号： G11C8/10 , G11C8/08
CPC分类号： G11C7/18 , G11C7/1048 , G11C8/08 , G11C8/12 , G11C8/14
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

52. 发明申请

US20100271885A1 Reduced complexity array line drivers for 3D matrix arrays 有权
标题翻译：降低3D矩阵阵列的复杂性阵列线驱动
公开(公告)号：US20100271885A1
公开(公告)日：2010-10-28
申请号：US12385964
申请日：2009-04-24
申请人： Roy E. Scheuerlein , Luca Fasoli
发明人： Roy E. Scheuerlein , Luca Fasoli
IPC分类号： G11C7/00 , G11C8/08
CPC分类号： G11C11/22 , G11C5/025 , G11C5/063 , G11C8/10 , G11C8/12 , G11C11/16 , G11C13/0002 , G11C13/0026 , G11C17/18 , G11C2213/71 , G11C2213/72
摘要： A method of biasing a nonvolatile memory array. The nonvolatile memory array includes a first and second plurality of Y lines, a plurality of X lines, a first and second plurality of two terminal memory cells. Each first and second memory cell is coupled to one of the first or second plurality of Y lines and one of the plurality of X lines, respectively. Substantially all of the first plurality and second plurality of Y lines are driven to a Y line unselect voltage. At least one selected Y line of the first plurality of Y lines is driven to a Y line select voltage while floating remaining Y lines of the first plurality of Y lines and while driving substantially all of the second plurality of Y lines to the Y line unselect voltage.
摘要翻译：一种偏置非易失性存储器阵列的方法。非易失性存储器阵列包括第一和第二多个Y线，多个X线，第一和第二多个两个终端存储器单元。每个第一和第二存储器单元分别耦合到第一或第二多个Y线中的一个和多个X线中的一个。基本上所有的第一和第二多个Y线被驱动到Y线取消选择电压。将第一多个Y线中的至少一个所选择的Y线驱动到Y线选择电压，同时浮置第一多条Y线的剩余Y线，同时将基本上所有的第二多条Y线驱动到Y线取消选择电压。

53. 发明授权

US07773443B2 Current sensing method and apparatus for a memory array 有权
标题翻译：用于存储器阵列的电流感测方法和装置
公开(公告)号：US07773443B2
公开(公告)日：2010-08-10
申请号：US12405160
申请日：2009-03-16
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C5/025 , G11C7/067 , G11C7/18 , G11C8/08 , G11C8/10 , G11C17/18 , G11C2207/063
摘要： A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.
摘要翻译：存储器阵列包括用于感测位线电流的感测电路，同时保持所选位线的电压基本上不变。字线和位线被偏置，使得基本上不会在半选择的存储器单元上施加偏置电压，这几乎消除了通过半选择的存储器单元的泄漏电流。感测的位线电流很大程度上仅来自所选存储单元的电流。存储器阵列中的噪声检测线减少了从未选择的字线耦合到所选位线的影响。在优选实施例中，具有在多于一个层上形成位线的多个轨道堆叠的三维存储器阵列包括与每个位线层相关联的至少一个噪声检测线。感测电路连接到选定的位线及其相关的噪声检测线。

54. 发明申请

US20100157652A1 Programming a memory cell with a diode in series by applying reverse bias 有权
标题翻译：通过施加反向偏置来对具有二极管串联的存储单元进行编程
公开(公告)号：US20100157652A1
公开(公告)日：2010-06-24
申请号：US12318021
申请日：2008-12-19
申请人： Yibo Nian , Tanmay Kumar , Roy E. Scheuerlein
发明人： Yibo Nian , Tanmay Kumar , Roy E. Scheuerlein
IPC分类号： G11C11/36
CPC分类号： G11C13/0007 , B82Y10/00 , G11C11/5614 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C11/5692 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/0016 , G11C13/0069 , G11C13/025 , G11C17/16 , G11C17/165 , G11C2013/009 , G11C2213/31 , G11C2213/32 , G11C2213/35 , G11C2213/72
摘要： A method of programming a memory cell comprises applying a reverse bias to the memory cell using a temporary resistor in series with the memory cell. The memory cell comprises a diode and a resistivity switching material element in series. The state of the resistivity switching material element changes from a first initial state to a second state different from the first state.
摘要翻译：一种对存储器单元进行编程的方法包括使用与存储单元串联的临时电阻器向存储单元施加反向偏置。存储单元包括串联的二极管和电阻率切换材料元件。电阻率切换材料元件的状态从第一初始状态变为与第一状态不同的第二状态。

55. 发明授权

US07696812B2 Cooperative charge pump circuit and method 有权
标题翻译：合作电荷泵电路及方法
公开(公告)号：US07696812B2
公开(公告)日：2010-04-13
申请号：US12352489
申请日：2009-01-12
申请人： Ali K. Al-Shamma , Roy E. Scheuerlein
发明人： Ali K. Al-Shamma , Roy E. Scheuerlein
IPC分类号： G05F1/10
CPC分类号： H02M3/073 , H02M2003/071 , H02M2003/077
摘要： A multiple polarity reversible charge pump circuit is disclosed which, in certain embodiments, may be configured to generate a positive voltage at times and may be reversed to generate a negative voltage at other times. Such a charge pump circuit is advantageous if both the positive and negative voltage are not simultaneously required. In certain other embodiments, a charge pump circuit generates a high output current for only a positive boosted voltage in one mode of operation, but lower current positive and negative boosted voltage outputs in another mode of operation. Use with certain erasable memory array technologies is disclosed, particularly certain resistive passive element memory cells, and more particularly in a three-dimensional memory array.
摘要翻译：公开了一种多极性可逆电荷泵电路，其在某些实施例中可被配置为有时产生正电压并且可以反向以在其它时间产生负电压。如果不同时需要正电压和负电压，则这种电荷泵电路是有利的。在某些其他实施例中，电荷泵电路仅在一种工作模式下产生仅仅正升压电压的高输出电流，而在另一种工作模式下产生较低电流正和负升压电压输出。公开了某些可擦除存储器阵列技术的使用，特别是某些电阻性无源元件存储单元，更具体地在三维存储器阵列中使用。

56. 发明申请

US20100059796A1 Shared masks for x-lines and shared masks for y-lines for fabrication of 3D memory arrays 有权
标题翻译：用于x线的共享掩码和用于制造3D存储器阵列的y线的共享掩码
公开(公告)号：US20100059796A1
公开(公告)日：2010-03-11
申请号：US12231000
申请日：2008-09-09
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： H01L21/283 , H01L27/06
CPC分类号： H01L21/283 , H01L21/8221 , H01L27/0207 , H01L27/0688 , H01L27/10
摘要： A structure and a method of manufacturing a three dimensional memory using a number of bit line masks that is less than the number of device layers. A first bit line mask is used to form a first bit line layer in a first device level. The first bit line layer comprises first bit lines. The first bit line mask is also used to form a second bit line layer in a second device level. The second bit line layer comprises second bit lines. The first bit lines and the second bit lines have different electrical connections to a bit line connection level despite employing the same mask pattern.
摘要翻译：使用小于设备层数的多个位线掩模来制造三维存储器的结构和方法。第一位线掩模用于在第一器件级中形成第一位线层。第一位线层包括第一位线。第一位线掩模还用于在第二器件级中形成第二位线层。第二位线层包括第二位线。即使使用相同的掩模图案，第一位线和第二位线具有与位线连接电平的不同电连接。

57. 发明申请

US20090323394A1 PULSE RESET FOR NON-VOLATILE STORAGE 有权
标题翻译：非易失性存储器的脉冲复位
公开(公告)号：US20090323394A1
公开(公告)日：2009-12-31
申请号：US12339363
申请日：2008-12-19
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0007 , G11C7/12 , G11C7/22 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2013/0092 , G11C2213/32 , G11C2213/34 , G11C2213/71
摘要： A non-volatile storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits to SET and RESET the resistance-switching elements. The circuits that RESET the resistance-switching elements provide a pulse to the memory cells that is large enough in magnitude to SET and RESET the memory cells, and long enough to potentially RESET the memory cell but not long enough to SET the memory cells.
摘要翻译：非易失性存储系统包括衬底，衬底上的控制电路，包括具有可逆电阻切换元件的多个存储单元的三维存储器阵列（衬底上方），以及用于设置和复位电阻切换的电路元素。复位电阻切换元件的电路向存储器单元提供足够大的脉冲以设置和复位存储器单元，并且足够长以潜在地重置存储器单元，但不足以设置存储器单元。

58. 发明授权

US07633828B2 Hierarchical bit line bias bus for block selectable memory array 有权
标题翻译：块可选存储阵列的分层位线偏置总线
公开(公告)号：US07633828B2
公开(公告)日：2009-12-15
申请号：US11461362
申请日：2006-07-31
申请人： Roy E. Scheuerlein , Luca G. Fasoli
发明人： Roy E. Scheuerlein , Luca G. Fasoli
IPC分类号： G11C8/00
CPC分类号： G11C16/08
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

59. 发明申请

US20090168480A1 Three dimensional hexagonal matrix memory array 有权
标题翻译：三维六边形矩阵记忆阵列
公开(公告)号：US20090168480A1
公开(公告)日：2009-07-02
申请号：US12005346
申请日：2007-12-27
申请人： Roy E. Scheuerlein , Christopher J. Petti
发明人： Roy E. Scheuerlein , Christopher J. Petti
IPC分类号： G11C5/02 , H01L21/308
CPC分类号： G03F7/2022 , B82Y10/00 , H01L27/0207 , H01L27/1021 , H01L27/112 , H01L27/224 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085
摘要： A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithography or by using a self-assembling layer.
摘要翻译：非易失性存储器件包括以基本上六边形图案布置的多个非易失性存储单元。非易失性存储单元可以是柱形非易失性存储单元，其可以使用三重或四重曝光光刻或通过使用自组装层进行图案化。

60. 发明授权

US07542337B2 Apparatus for reading a multi-level passive element memory cell array 有权
标题翻译：用于读取多级无源元件存储单元阵列的装置
公开(公告)号：US07542337B2
公开(公告)日：2009-06-02
申请号：US11461343
申请日：2006-07-31
申请人： Roy E. Scheuerlein , Tyler J. Thorp , Luca G. Fasoli
发明人： Roy E. Scheuerlein , Tyler J. Thorp , Luca G. Fasoli
IPC分类号： G11C16/04
CPC分类号： G11C11/56 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/77
摘要： A four level passive element cell has memory states corresponding to decreasing resistance levels, which are preferably mapped respectively to data states 11, 01, 00, and 10. The LSB and MSB are preferably mapped as part of different pages. To discriminate between memory cell states, the selected bit line current is sensed for at least two different combinations of reference current level and read bias voltage. A mid-level reference is used to read the LSB. When reading the MSB, a first reference between the 10 and 00 data states, and a second reference between 01 and 11 data states may be used, and the mid-level reference need not be used. In certain embodiments, the bit line current may be simultaneously compared against the first and second references, without requiring a delay to stabilize the bit line current to a different value, and the MSB generated accordingly.
摘要翻译：四级无源元件单元具有对应于降低电阻电平的存储器状态，其优选地分别映射到数据状态11,01,00和10. LSB和MSB优选地被映射为不同页面的一部分。为了区分存储单元状态，对于参考电流电平和读取偏置电压的至少两种不同的组合来检测所选择的位线电流。中间级参考用于读取LSB。当读取MSB时，可以使用10和00数据状态之间的第一个参考，并且可以使用01和11数据状态之间的第二个参考，并且不需要使用中间级参考。在某些实施例中，位线电流可以同时与第一和第二参考值进行比较，而不需要延迟来将位线电流稳定到不同的值，并且相应地生成MSB。

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