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    • 51. 发明授权
      US07395292B2 Method for displaying spectral trends in complex signals 有权
    • Method for displaying spectral trends in complex signals
    • 在复杂信号中显示光谱趋势的方法
    • US07395292B2
    • 2008-07-01
    • US10962336
    • 2004-10-08
    • Mark W. Johnson
    • Mark W. Johnson
    • G06F15/00 , G06F19/00
    • A61B5/048 , A61B5/7257
    • A method for displaying changes in spectral content of data signals over periods of time using a computer system. The method includes the steps of transforming time segments of digitized data signals into a frequency based spectral representation of the digitized data. The resulting spectral data are then grouped into appropriate frequency bins. Each frequency bin is normalized by the frequency range of the bin. The energy or power in each frequency bin is then multiplied by fn, where f represents an estimate of the frequency of the bin, and n is an exponent which is used to normalize the frequency content of the data. A logarithmic value is then calculated for each frequency bin. The logarithmic value of each frequency bin for each time period is then mapped to a color or gray-scale value. Finally, the mapped color or gray-scale value is displayed on a computer monitor in the computer system as an image, where the signal frequency is represented along one axis, time is represented along a second axis, and the value of the energy or power at that given time and frequency is displayed as the color or gray-scale value assigned to that point.
    • 一种使用计算机系统在一段时间内显示数据信号的频谱内容的变化的方法。 该方法包括将数字化数据信号的时间段转换为数字化数据的基于频率的频谱表示的步骤。 然后将所得到的光谱数据分组成适当的频率仓。 每个频率仓通过仓的频率范围进行归一化。 然后将每个频率仓中的能量或功率乘以f SUP n n，f f f f f f f f f f f f f f f and and and and and and and and and and and and and and and 。 然后对每个频率仓计算一个对数值。 然后将每个时间段的每个频率仓的对数值映射到一个颜色或灰度值。 最后，将映射的颜色或灰度值作为图像显示在计算机系统中的计算机监视器上，其中信号频率沿着一个轴表示，时间沿第二轴表示，能量或功率的值 在给定的时间和频率显示为分配给该点的颜色或灰度值。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 53. 发明授权
      US06629206B1 Set-associative cache-management using parallel reads and serial reads initiated during a wait state 有权
    • Set-associative cache-management using parallel reads and serial reads initiated during a wait state
    • 在等待状态期间启动并行读取和串行读取的集相关高速缓存管理
    • US06629206B1
    • 2003-09-30
    • US09476031
    • 1999-12-31
    • Mark W. Johnson
    • Mark W. Johnson
    • G06F1208
    • G06F12/0864 , G06F2212/1028 , Y02D10/13
    • A Harvard-architecture computer system includes a processor, an instruction cache, a data cache, and a write buffer. The caches are both set-associative in that they each have plural memories; both caches perform parallel reads by default. In a parallel read, all cache-memory locations of the selected cache corresponding to the set ID and word position bits of a requested read address are accessed in parallel while it is determined whether or not one of these locations has a tag matching the tag portion of the requested read address. If there is a “hit” (match), then an output multiplexer selects the appropriate cache memory for providing its data to the processor. The parallel read thus achieves faster reads, but expends extra power in accessing non-matching sets. A cache receiving a read request while the processor is waited performs a serial read instead of a parallel read. In a serial read, the tag match is performed before the data is accessed. Accordingly, a cache memory is accessed only if a match is found, achieving a power savings relative to a parallel read. There is no latency penalty since the parallel read cannot be completed during the wait. Thus, the power savings is achieved without impairing performance.
    • 哈佛架构计算机系统包括处理器，指令高速缓存，数据高速缓存和写入缓冲器。 高速缓存是集合关联的，因为它们各自具有多个记忆; 两个缓存默认执行并行读取。 在并行读取中，与所请求的读取地址的集合ID和字位置比特相对应的所选高速缓冲存储单元的所有高速缓冲存储器位置被并行访问，同时确定这些位置中的一个是否具有与标签部分匹配的标签 的请求读取地址。 如果存在“匹配”（匹配），则输出多路复用器选择适当的高速缓冲存储器以将其数据提供给处理器。 因此，并行读取实现更快的读取，但是在访问非匹配集合时花费额外的功率。 处理器等待时接收读取请求的缓存执行串行读取而不是并行读取。 在串行读取中，在访问数据之前执行标签匹配。 因此，仅当找到匹配时才访问高速缓冲存储器，实现相对于并行读取的功率节省。 由于并行读取在等待期间无法完成，因此没有延迟处罚。 因此，在不损害性能的情况下实现功率节省。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 54. 发明授权
      US06483339B1 Single flux quantum series biasing technique using superconducting DC transformer 有权
    • Single flux quantum series biasing technique using superconducting DC transformer
    • 使用超导直流变压器的单通量子量子偏置技术
    • US06483339B1
    • 2002-11-19
    • US09935310
    • 2001-08-22
    • Dale J. Durand , Quentin P. Herr , Mark W. Johnson
    • Dale J. Durand , Quentin P. Herr , Mark W. Johnson
    • H03K19195
    • H03K19/1952
    • The level of bias current (12) required by a superconductor integrated circuit (2 & 4) is lowered by separating the circuit into portions having separate ground planes and supplying the bias current to the circuit portion (2) in one ground plane in series (10) with that for the circuit portion (4) in another ground plane. To maintain DC isolation between those circuit portions, SFQ pulses inputted (SFQ IN) move across the separate ground planes through a pair of inductively coupled SQUIDS (3 & 5) that define a DC transformer; and a combiner (7) reconstitutes and outputs the SFQ pulses. To provide inductive coupling the DC transformer includes a primary (25) and isolated secondary (5) winding.
    • 通过将电路分离成具有分离的接地平面的部分并将偏置电流提供给串联的一个接地平面中的电路部分（2）来降低超导体集成电路（2和4）所需的偏置电流（12）的电平（ 10）与电路部分（4）在另一个接地平面中的电路部分。 为了保持这些电路部分之间的直流隔离，输入的SFQ脉冲（SFQ IN）通过一对感应耦合的SQUIDS（3和5）在独立的接地层上移动，定义了一个直流变压器; 并且组合器（7）重构并输出SFQ脉冲。 为了提供电感耦合，DC变压器包括初级（25）和隔离次级（5）绕组。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 55. 发明授权
      US06388600B1 Asynchronous superconductor serial multiply-accumulator 失效
    • Asynchronous superconductor serial multiply-accumulator
    • 异步超导体串联倍增器
    • US06388600B1
    • 2002-05-14
    • US09711322
    • 2000-11-13
    • Mark W. Johnson , Dale J. Durand
    • Mark W. Johnson , Dale J. Durand
    • H03M112
    • H03M1/60
    • An oscillator/multiply-accumulator AID converter (100) which simultaneously provides frequency downconversion, band pass filtering and analog-to-digital conversion of an analog signal, where the analog signal includes a carrier wave modulated with information by any known modulation technique. The converter (100) uses a superconducting, Josephson single flux quantum circuit operating as a voltage controlled oscillator (102). The voltage controlled oscillator (102) receives the analog signal to be converted, and generates a series of sharp, high frequency pulses based on the characteristics of the carrier signal. The series of pulses are applied to a gate circuit (104) that either passes or blocks the pulses depending on a gate control signal (103). When the pulses are passed by the gate circuit (104), a multiply-accumulator (106) multiplies the pulse by a binary coefficient (109) and accumulates the products (111) resulting from the multiplication during a predetermined time period. The predetermined time period includes at least one sampling period. Each sample is multiplied by a different weight and their products (111) are accumulated. This operation eliminates the DC response, and leads to an improved frequency response.
    • 同时提供模拟信号的频率下变频，带通滤波和模数转换的振荡器/乘法器AID转换器（100），其中模拟信号包括通过任何已知调制技术用信息调制的载波。 转换器（100）使用作为压控振荡器（102）工作的超导约瑟夫森单通量量子电路。 压控振荡器（102）接收要转换的模拟信号，并且基于载波信号的特性产生一系列尖锐的高频脉冲。 脉冲序列被施加到门电路（104），门电路（104）根据门控信号（103）通过或阻塞脉冲。 当脉冲被门电路（104）通过时，乘法累加器（106）将脉冲乘以二进制系数（109），并且在预定时间段内积累乘积产生的乘积（111）。 预定时间段包括至少一个采样周期。 每个样品乘以不同的重量，并且其产物（111）被累积。 该操作消除了直流响应，并且导致了改进的频率响应。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 56. 发明授权
      US06338118B2 Set-associative cache-management method with parallel and single-set sequential reads 有权
    • Set-associative cache-management method with parallel and single-set sequential reads
    • 具有并行和单组顺序读取的集相关缓存管理方法
    • US06338118B2
    • 2002-01-08
    • US09797644
    • 2001-03-01
    • Mark W. Johnson
    • Mark W. Johnson
    • G06F928
    • G06F12/0882 , G06F12/0864 , G06F2212/1028 , Y02D10/13
    • A set-associative cache-management method utilizes both parallel reads and single-cycle single-set reads. The parallel reads involve accessing data from all cache sets in parallel before a tag match is determined. Once a tag match is determined, it is used to select the one of the accessed cache memory locations to be coupled to the processor for the read operation. Single-cycle single-set reads occur when the line address of one read operation matches the line address of an immediately preceding read operation satisfied from the cache. In such a case, only the set from which the previous read request was satisfied is accessed in the present read operation. The single-set reads save power relative to the parallel reads, while maintaining the speed advantages of the parallel reads over serial “tag-then-data” reads.
    • 集相关缓存管理方法利用并行读取和单周期单集读取。 并行读取涉及在确定标签匹配之前并行访问所有高速缓存集中的数据。 一旦确定了标签匹配，则用于选择要与读取操作耦合到处理器的所访问的高速缓存存储单元中的一个。 当一个读取操作的行地址与从高速缓存满足的紧接在前的读取操作的行地址匹配时，发生单周期单集读取。 在这种情况下，在本读取操作中仅访问满足先前读取请求的集合。 单组读取相对于并行读取的保存功率，同时保持并行读取速度优于串行“标签 - 然后数据”读取的速度优势。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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