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51. 发明申请

US20050250258A1 Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode 审中-公开
标题翻译：制造具有高k栅极电介质层和金属栅电极的半导体器件的方法
公开(公告)号：US20050250258A1
公开(公告)日：2005-11-10
申请号：US10839077
申请日：2004-05-04
申请人： Matthew Metz , Suman Datta , Jack Kavalieros , Mark Doczy , Justin Brask , Robert Chau
发明人： Matthew Metz , Suman Datta , Jack Kavalieros , Mark Doczy , Justin Brask , Robert Chau
IPC分类号： H01L21/8238 , H01L21/335
CPC分类号： H01L21/823842
摘要： A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and forming a masking layer on a first part of the high-k gate dielectric layer. After forming a first metal layer on the masking layer and on an exposed second part of the high-k gate dielectric layer, the masking layer is removed. A second metal layer is then formed on the first metal layer and on the first part of the high-k gate dielectric layer.
摘要翻译：描述制造半导体器件的方法。该方法包括在衬底上形成高k栅极电介质层，并在高k栅极电介质层的第一部分上形成掩模层。在掩模层和高k栅极电介质层的暴露的第二部分上形成第一金属层之后，去除掩模层。然后在第一金属层和高k栅极电介质层的第一部分上形成第二金属层。

52. 发明申请

US20050156171A1 Nonplanar transistors with metal gate electrodes 有权
公开(公告)号：US20050156171A1
公开(公告)日：2005-07-21
申请号：US11023881
申请日：2004-12-27
申请人： Justin Brask , Brian Doyle , Mark Doczy , Robert Chau
发明人： Justin Brask , Brian Doyle , Mark Doczy , Robert Chau
IPC分类号： H01L21/336 , H01L21/77 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L29/49 , H01L29/786 , H01L29/94
CPC分类号： H01L29/785 , H01L21/823821 , H01L21/823828 , H01L21/845 , H01L27/092 , H01L27/0924 , H01L29/4908 , H01L29/66545 , H01L29/66795
摘要： A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are uniformed in the semiconductor body on opposite sides of the gate electrode.

53. 发明申请

US20050136677A1 Method for making a semiconductor device that includes a metal gate electrode 有权
标题翻译：制造包括金属栅电极的半导体器件的方法
公开(公告)号：US20050136677A1
公开(公告)日：2005-06-23
申请号：US10739173
申请日：2003-12-18
申请人： Justin Brask , Jack Kavalieros , Uday Shah , Mark Doczy , Matthew Metz , Robert Chau
发明人： Justin Brask , Jack Kavalieros , Uday Shah , Mark Doczy , Matthew Metz , Robert Chau
IPC分类号： H01L21/033 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L21/302 , H01L21/461
CPC分类号： H01L21/28185 , H01L21/0337 , H01L21/0338 , H01L21/28079 , H01L21/28088 , H01L21/28194 , H01L21/823842 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/511 , H01L29/517 , H01L29/66545 , H01L29/6659
摘要： A method for making a semiconductor device is described. That method comprises forming a dummy dielectric layer that is at least about 10 angstroms thick on a substrate, and forming a sacrificial layer on the dummy dielectric layer. After removing the sacrificial layer and the dummy dielectric layer to generate a trench that is positioned between first and second spacers, a gate dielectric layer is formed on the substrate at the bottom of the trench, and a metal layer is formed on the gate dielectric layer.
摘要翻译：描述制造半导体器件的方法。该方法包括在衬底上形成至少约10埃厚的虚拟电介质层，并在虚拟电介质层上形成牺牲层。在除去牺牲层和虚设电介质层以产生位于第一和第二间隔物之间的沟槽之后，在沟槽的底部的衬底上形成栅介质层，并且在栅介质层上形成金属层。

54. 发明申请

US20050048791A1 Selective etch process for making a semiconductor device having a high-k gate dielectric 失效
标题翻译：用于制造具有高k栅极电介质的半导体器件的选择性蚀刻工艺
公开(公告)号：US20050048791A1
公开(公告)日：2005-03-03
申请号：US10652546
申请日：2003-08-28
申请人： Justin Brask , Uday Shah , Mark Doczy , Jack Kavalieros , Robert Chau , Robert Turkot , Matthew Metz
发明人： Justin Brask , Uday Shah , Mark Doczy , Jack Kavalieros , Robert Chau , Robert Turkot , Matthew Metz
IPC分类号： H01L21/336 , H01L21/311 , H01L21/302 , H01L21/461
CPC分类号： H01L21/31111
摘要： A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and modifying a first portion of the high-k gate dielectric layer to ensure that it may be removed selectively to a second portion of the high-k gate dielectric layer.
摘要翻译：描述制造半导体器件的方法。该方法包括在衬底上形成高k栅极电介质层，以及修改高k栅极电介质层的第一部分，以确保其可被选择性地去除到高k栅极电介质层的第二部分。

55. 发明申请

US20050237850A1 Method and apparatus for improving stability of a 6T CMOS SRAM cell 有权
公开(公告)号：US20050237850A1
公开(公告)日：2005-10-27
申请号：US11165724
申请日：2005-06-24
申请人： Suman Datta , Brian Doyle , Robert Chau , Jack Kavalieros , Bo Zheng , Scott Hareland
发明人： Suman Datta , Brian Doyle , Robert Chau , Jack Kavalieros , Bo Zheng , Scott Hareland
IPC分类号： G11C11/412 , H01L21/336 , H01L21/8244 , H01L27/11 , H01L29/423 , H01L29/786 , G11C8/02
CPC分类号： G11C11/412 , H01L21/845 , H01L27/11 , H01L27/1104 , H01L27/1211 , H01L29/42384 , H01L29/66795 , H01L29/785 , H01L29/7854
摘要： The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin; and two pull-down devices, each pull-down device comprised of a tri-gate transistor having multiple fins. A method for manufacturing the CMOS SRAM cell, including the dual fin tri-gate transistor is also provided.

56. 发明申请

US20050221548A1 Semiconductor device having a laterally modulated gate workfunction and method of fabrication 失效
标题翻译：具有横向调制的栅极功能函数和制造方法的半导体器件
公开(公告)号：US20050221548A1
公开(公告)日：2005-10-06
申请号：US11099190
申请日：2005-04-04
申请人： Brian Doyle , Scott Hareland , Mark Doczy , Robert Chau
发明人： Brian Doyle , Scott Hareland , Mark Doczy , Robert Chau
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L31/112
CPC分类号： H01L29/4983 , H01L21/28079 , H01L21/28088 , H01L21/28105 , H01L21/28194 , H01L21/28202 , H01L21/32051 , H01L29/4958 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659
摘要： A transistor comprising a gate electrode formed on a gate dielectric layer formed on a substrate. A pair of source/drain regions are formed in the substrate on opposite sides of the laterally opposite sidewalls of the gate electrode. The gate electrode has a central portion formed on the gate dielectric layer and over the substrate region between the source and drain regions and a pair sidewall portions which overlap a portion of the source/drain regions wherein the central portion has a first work function and said pair of sidewall portions has a second work function, wherein the second work function is different than the first work function.
摘要翻译：一种晶体管，包括形成在形成于基板上的栅介质层上的栅电极。在栅电极的横向相对的侧壁的相对侧上的衬底中形成一对源极/漏极区域。栅极电极具有形成在栅极介电层上并且在源极和漏极区域之间的衬底区域上的中心部分和与源极/漏极区域的一部分重叠的一对侧壁部分，其中中心部分具有第一功函数和所述一对侧壁部分具有第二功函数，其中第二功函数不同于第一功函数。

57. 发明申请

US20050142766A1 Method of fabricating an ultra-narrow channel semiconductor device 有权
标题翻译：制造超窄通道半导体器件的方法
公开(公告)号：US20050142766A1
公开(公告)日：2005-06-30
申请号：US11064808
申请日：2005-02-23
申请人： Scott Hareland , Robert Chau
发明人： Scott Hareland , Robert Chau
IPC分类号： H01L21/335 , H01L29/76 , H01L29/775 , H01L21/336 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/0673 , H01L29/66439 , H01L29/66545 , H01L29/66818 , H01L29/7613 , H01L29/785 , Y10S977/762
摘要： A method of forming a nanowire is disclosed. A nanowire having a first dimension is deposited on a first dielectric layer that is formed on a substrate. A sacrificial gate stack having a sacrificial dielectric layer and a sacrificial gate electrode layer is deposited over a first region of the nanowire leaving exposed a second region and a third region of the nanowire. A first spacer is deposited on each side of the sacrificial gate stack. A second dielectric layer is deposited over the first dielectric layer to cover the second region and the third region. The sacrificial gate stack is removed. The first region of the nanowire is thinned by at least one thermal oxidation process and oxide removal process to thin said first region from said first dimension to a second dimension.
摘要翻译：公开了形成纳米线的方法。具有第一尺寸的纳米线沉积在形成在基底上的第一介电层上。具有牺牲电介质层和牺牲栅极电极层的牺牲栅极堆叠沉积在纳米线的第一区域上，从而暴露出纳米线的第二区域和第三区域。在牺牲栅极堆叠的每一侧上沉积第一间隔物。第二电介质层沉积在第一介电层上以覆盖第二区域和第三区域。去除牺牲栅极堆叠。通过至少一个热氧化工艺和氧化物去除工艺来稀薄纳米线的第一区域，以使所述第一区域从所述第一维度稀薄到第二维度。

58. 发明授权

US07531404B2 Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer 有权
标题翻译：具有在退火的高k栅介质层上形成的金属栅电极的半导体器件
公开(公告)号：US07531404B2
公开(公告)日：2009-05-12
申请号：US11216596
申请日：2005-08-30
申请人： Sangwoo Pae , Jose Maiz , Justin Brask , Gilbert Dewey , Jack Kavalieros , Robert Chau , Suman Datta
发明人： Sangwoo Pae , Jose Maiz , Justin Brask , Gilbert Dewey , Jack Kavalieros , Robert Chau , Suman Datta
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/8234 , H01L21/3205
CPC分类号： H01L21/28185 , H01L21/28088 , H01L29/495 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/66583
摘要： A method of forming a transistor gate stack having an annealed gate dielectric layer begins by providing a substrate that includes a first and second spacer separated by a trench. A conformal high-k gate dielectric layer is deposited on the substrate and within the trench with a thickness that ranges from 3 Å to 60 Å. Next, a capping layer is deposited on the high-k gate dielectric layer that substantially fills the trench and covers the high-k gate dielectric layer. The high-k gate dielectric layer is then annealed at a temperature that is greater than or equal to 600° C. The capping layer is removed to expose an annealed high-k gate dielectric layer. A metal layer is then deposited on the annealed high-k gate dielectric layer. A CMP process may be used to remove excess material and complete formation of the transistor gate stack.
摘要翻译：形成具有退火栅极电介质层的晶体管栅极堆叠的方法开始于提供包括由沟槽分隔开的第一和第二间隔物的衬底。保形高k栅极电介质层沉积在衬底上并且在沟槽内沉积，厚度范围为3埃至60埃。接下来，在高k栅极电介质层上沉积盖层，其基本上填充沟槽并覆盖高k栅极电介质层。然后将高k栅极电介质层在大于或等于600℃的温度下退火。去除覆盖层以暴露退火的高k栅极电介质层。然后在退火的高k栅极电介质层上沉积金属层。可以使用CMP工艺来去除多余的材料并完成晶体管栅叠层的形成。

59. 发明申请

US20070158702A1 Transistor including flatband voltage control through interface dipole engineering 审中-公开
标题翻译：晶体管包括通过接口偶极工程的平带电压控制
公开(公告)号：US20070158702A1
公开(公告)日：2007-07-12
申请号：US11322827
申请日：2005-12-30
申请人： Mark Doczy , Matthew Metz , Justin Brask , Robert Chau , Gilbert Dewey
发明人： Mark Doczy , Matthew Metz , Justin Brask , Robert Chau , Gilbert Dewey
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L29/785 , H01L29/4908
摘要： A transistor comprising a semiconductor including a source, a drain, and a channel interposed between the source and the drain; a first dielectric layer having a first thickness, the first dielectric layer being positioned on the channel; a second dielectric layer having a second thickness, the second dielectric layer being positioned on the first dielectric layer; and a gate electrode on the second dielectric layer, wherein the transistor gate is made of a mid-gap metal. A process comprising depositing a first dielectric layer on at least one surface of a semiconductor layer; depositing a second dielectric layer on the first dielectric layer; depositing a layer of mid-gap metal on the second dielectric layer; and patterning and etching the first dielectric layer, the second dielectric layer and the layer of mid-gap metal to create a gate electrode separated from the substrate by a first dielectric and a second dielectric. Other embodiments are disclosed and claimed.
摘要翻译：一种晶体管，包括：半导体，包括源极，漏极和介于源极和漏极之间的沟道; 具有第一厚度的第一介电层，所述第一介电层位于所述通道上; 具有第二厚度的第二介电层，所述第二介电层位于所述第一介电层上; 以及第二介质层上的栅电极，其中晶体管栅极由中间间隙金属制成。一种方法，包括在半导体层的至少一个表面上沉积第一介电层; 在所述第一电介质层上沉积第二电介质层; 在所述第二电介质层上沉积中间间隙金属层; 以及对第一电介质层，第二电介质层和中间间隙金属层进行图案化和蚀刻以产生通过第一电介质和第二电介质与衬底分离的栅电极。公开和要求保护其他实施例。

60. 发明申请

US20070145498A1 DEVICE WITH SCAVENGING SPACER LAYER 有权
标题翻译：装置与SCAVENGING间隔层
公开(公告)号：US20070145498A1
公开(公告)日：2007-06-28
申请号：US11320305
申请日：2005-12-27
申请人： Matthew Metz , Mark Doczy , Justin Brask , Robert Chau
发明人： Matthew Metz , Mark Doczy , Justin Brask , Robert Chau
IPC分类号： H01L29/94
CPC分类号： H01L29/0847 , H01L29/513 , H01L29/517 , H01L29/6656 , H01L29/66636
摘要： Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen-scavenging spacer layer on side walls of the high-k gate dielectric layer and metal gate may reduce such oxidation during high temperature processes.
摘要翻译：本发明的实施例提供一种具有金属栅极，高k栅极电介质层和在高k栅极电介质层下面的衬底的氧化减少的器件。在高k栅极电介质层和金属栅极的侧壁上的氧气清除间隔层可以在高温过程中减少这种氧化。

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