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51. 发明申请

US20050248995A1 Memory system and method for two step memory write operations 失效
标题翻译：用于两步存储器写操作的存储器系统和方法
公开(公告)号：US20050248995A1
公开(公告)日：2005-11-10
申请号：US11181412
申请日：2005-07-13
申请人： Paul Davis , Frederick Ware , Craig Hampel
发明人： Paul Davis , Frederick Ware , Craig Hampel
IPC分类号： G06F13/16 , G11C5/00 , G11C7/10 , G11C7/22
CPC分类号： G11C7/1039 , G06F13/1626 , G11C7/1006 , G11C7/22 , G11C11/4076 , G11C2207/2218 , G11C2207/229
摘要： A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation requires a resource needed for the completion of a read operation, the data being written is stored in a write data buffer in the memory device. The write data is stored in the buffer until a datapath is available to communicate the data to the memory device's memory core. Once the resource is free (or the memory device, or its controller force the write to complete) the data is written to the memory core of the memory device using the now-free datapath.
摘要翻译：描述了一种用于将数据存储在存储器件中的方法和装置。该装置被配置为执行以下步骤。该方法采用两步技术，允许无序完成读写操作。当写入操作需要完成读取操作所需的资源时，被写入的数据被存储在存储器件中的写入数据缓冲器中。写入数据被存储在缓冲器中，直到数据路径可用于将数据传送到存储器件的存储器核心。一旦资源空闲（或存储设备或其控制器强制写入完成），数据将使用现在免费的数据路径写入存储器设备的存储器内核。

52. 发明申请

US20050201164A1 Memory device having asynchronous/synchronous operating modes 有权
标题翻译：具有异步/同步操作模式的存储器件
公开(公告)号：US20050201164A1
公开(公告)日：2005-09-15
申请号：US11123931
申请日：2005-05-06
申请人： Richard Barth , Mark Horowitz , Craig Hampel , Frederick Ware
发明人： Richard Barth , Mark Horowitz , Craig Hampel , Frederick Ware
IPC分类号： G06F12/00 , G06F13/16 , G11C5/00 , G11C7/10 , G11C7/22 , G11C8/18
CPC分类号： G11C7/222 , G06F13/16 , G11C7/1045 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C8/18 , Y02D10/14
摘要： An integrated circuit memory device comprises a memory array to store data, a circuit to output the data at a pin, and a register to store a value that indicates a mode of operation of the integrated circuit memory device. The mode of operation is selected from at least one of a synchronous mode of operation and an asynchronous mode of operation. During the synchronous mode of operation, the circuit outputs the data in response to a transition of an external clock signal. During the asynchronous mode of operation, the circuit outputs the data after a period of time from when a transition of an external control signal is detected.
摘要翻译：集成电路存储器件包括用于存储数据的存储器阵列，用于在引脚处输出数据的电路以及用于存储指示集成电路存储器件的操作模式的值的寄存器。操作模式从同步操作模式和异步操作模式中的至少一个中选择。在同步操作模式期间，电路响应于外部时钟信号的转变而输出数据。在异步操作模式期间，电路在检测到外部控制信号的转变之后的一段时间后输出数据。

53. 发明申请

US20060004955A1 Dynamic memory supporting simultaneous refresh and data-access transactions 有权
公开(公告)号：US20060004955A1
公开(公告)日：2006-01-05
申请号：US11215339
申请日：2005-08-29
申请人： Frederick Ware , Richard Perego
发明人： Frederick Ware , Richard Perego
IPC分类号： G06F12/00
CPC分类号： G11C11/406 , G06F12/00 , G06F13/1605 , G11C11/40603
摘要： Described are dynamic memory systems that perform overlapping refresh and data-access (read or write) transactions that minimize the impact of the refresh transaction on memory performance. The memory systems support independent and simultaneous activate and precharge operations directed to different banks. Two sets of address registers enable the system to simultaneously specify different banks for refresh and data-access transactions.

54. 发明申请

US20060203532A1 Early read after write operation memory device, system and method 有权
公开(公告)号：US20060203532A1
公开(公告)日：2006-09-14
申请号：US11434695
申请日：2006-05-16
申请人： Richard Perego , Frederick Ware
发明人： Richard Perego , Frederick Ware
IPC分类号： G11C5/06
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C2207/2281 , G11C2207/229
摘要： A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path.

55. 发明申请

US20050157579A1 Memory device supporting a dynamically configurable core organization 审中-公开
标题翻译：内存设备支持动态配置的核心组织
公开(公告)号：US20050157579A1
公开(公告)日：2005-07-21
申请号：US11078872
申请日：2005-03-12
申请人： Richard Perego , Donald Stark , Frederick Ware
发明人： Richard Perego , Donald Stark , Frederick Ware
IPC分类号： G06F12/04 , G06F12/06 , G11C5/00 , G11C5/04 , G11C7/10 , G11C8/00 , G11C11/408 , G11C11/4097 , H05K1/11 , H05K1/14
CPC分类号： G06F13/1678 , G06F12/04 , G06F12/06 , G06F12/0646 , G06F13/1657 , G06F13/4022 , G11C5/02 , G11C5/025 , G11C5/04 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C7/1045 , G11C7/1048 , G11C7/106 , G11C7/1072 , G11C7/1087 , G11C8/06 , G11C11/4087 , G11C11/4097 , G11C2207/105 , G11C2207/108 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14 , Y02D10/151
摘要： Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.
摘要翻译：描述了存储器系统，其中存储器核心组织随设备宽度而变化。所访问的物理存储器组的数量随着器件宽度而减少，导致相对较窄的存储器配置的功率消耗减少。增加用于窄内存宽度的逻辑内存库的数量可以减少存储体冲突的可能性，从而提高速度性能。

56. 发明申请

US20090059642A1 Memory Controller With Multi-Modal Reference Pad 有权
标题翻译：具有多模态参考电压的存储控制器
公开(公告)号：US20090059642A1
公开(公告)日：2009-03-05
申请号：US12204728
申请日：2008-09-04
申请人： Frederick Ware , John Wilson , John C. Eble, III , Jade M. Kizer , Lei Luo , John W. Poulton , Ian Shaeffer
发明人： Frederick Ware , John Wilson , John C. Eble, III , Jade M. Kizer , Lei Luo , John W. Poulton , Ian Shaeffer
IPC分类号： G11C5/06 , G11C7/00 , G11C8/00
CPC分类号： G11C5/063 , G11C5/147
摘要： A memory controller operates in two modes to support different types of memory devices. In a first mode, the memory controller distributes a dedicated reference voltage with each of a plurality of signal bundles to a corresponding plurality of memory devices. The reference voltages are conveyed using pads that are alternatively used for e.g. timing-reference signals in a second mode, so the provision for bundle-specific reference voltages need not increase the number of pads on the memory controller.
摘要翻译：存储器控制器以两种模式操作以支持不同类型的存储器件。在第一模式中，存储器控制器将具有多个信号束中的每一个的专用参考电压分配给相应的多个存储器件。参考电压使用可替换地用于例如电极的焊盘传送。定时参考信号处于第二模式，因此针对束特定参考电压的提供不需要增加存储器控制器上的焊盘数量。

57. 发明申请

US20070300038A1 Memory Controller for Non-Homogeneous Memory System 有权
标题翻译：非均匀内存系统的内存控制器
公开(公告)号：US20070300038A1
公开(公告)日：2007-12-27
申请号：US11852996
申请日：2007-09-10
申请人： Frederick Ware
发明人： Frederick Ware
IPC分类号： G06F12/06
CPC分类号： G06F12/10 , G06F12/0292 , G06F12/08 , G06F12/0804 , G06F2212/2022 , G06F2212/205 , Y02D10/13
摘要： A memory controller includes at least one interface adapted to be coupled to one or more first memory devices of a first memory type having a first set of attributes, and to one or more second memory devices of a second memory type having a second set of attributes. The first and second sets of attributes have at least one differing attribute. The controller also includes interface logic configured to direct memory transactions having a predefined first characteristic to the first memory devices and to direct memory transactions having a predefined second characteristic to the second memory devices. Pages having a usage characteristic of large volumes of write operations may be mapped to the one or more first memory devices, while pages having a read-only or read-mostly usage characteristic may be mapped to the one or more second memory devices.
摘要翻译：存储器控制器包括适于耦合到具有第一组属性的第一存储器类型的一个或多个第一存储器件的至少一个接口以及具有第二组属性的第二存储器类型的一个或多个第二存储器件。第一和第二组属性具有至少一个不同的属性。控制器还包括接口逻辑，其被配置为将具有预定义的第一特性的存储器事务定向到第一存储器设备，并且将具有预定义的第二特性的存储器事务定向到第二存储器设备。具有大量写入操作的使用特性的页面可以被映射到一个或多个第一存储器设备，而具有只读或读取主要使用特性的页面可以映射到一个或多个第二存储器设备。

58. 发明申请

US20110016278A1 Independent Threading of Memory Devices Disposed on Memory Modules 审中-公开
标题翻译：内存模块中存储设备的独立线程
公开(公告)号：US20110016278A1
公开(公告)日：2011-01-20
申请号：US12920811
申请日：2009-03-05
申请人： Frederick Ware , Craig E. Hampel , Ian Shaeffer , Scott C. Best
发明人： Frederick Ware , Craig E. Hampel , Ian Shaeffer , Scott C. Best
IPC分类号： G06F12/00
CPC分类号： G11C7/1072 , G06F13/1684 , G06F13/4234 , G11C5/00
摘要： A memory module includes a substrate having signal lines thereon that form a control path and a plurality of data paths. A plurality of memory devices are mounted on the substrate. Each memory device is coupled to the control path and to a distinct data path. The memory module includes control circuitry to enable each memory device to process a distinct respective memory access command in a succession of memory access commands and to output data on the distinct data path in response to the processed memory access command.
摘要翻译：存储器模块包括其上具有信号线的衬底，其形成控制路径和多个数据路径。多个存储器件安装在基片上。每个存储器件耦合到控制路径和不同的数据路径。存储器模块包括控制电路，以使得每个存储器设备能够在一系列存储器访问命令中处理不同的相应存储器访问命令，并且响应于处理的存储器访问命令在不同的数据路径上输出数据。

59. 发明申请

US20100230807A1 Method and Apparatus to Repair Defects in Nonvolatile Semiconductor Memory Devices 有权
标题翻译：修复非易失性半导体存储器件缺陷的方法和装置
公开(公告)号：US20100230807A1
公开(公告)日：2010-09-16
申请号：US12676594
申请日：2008-09-04
申请人： Gary B. Bronner , Ming Li , Donald R. Mullen , Frederick Ware , Kevin S. Donnelly
发明人： Gary B. Bronner , Ming Li , Donald R. Mullen , Frederick Ware , Kevin S. Donnelly
IPC分类号： H01L23/34 , H01L21/26
CPC分类号： G11C16/349 , G11C16/3418 , H01L23/3128 , H01L23/345 , H01L24/73 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06562 , H01L2225/06589 , H01L2924/15311 , H01L2924/19107 , H01L2924/00012 , H01L2924/00
摘要： A method of repairing a nonvolatile semiconductor memory device to eliminate defects includes monitoring a memory endurance indicator for a nonvolatile semiconductor memory device contained in a semiconductor package. It is determined whether that the memory endurance indicator exceeds a predefined limit. Finally, in response to determining that the memory endurance indicator exceeds the predefined limit, the device is annealed.
摘要翻译：一种修复非易失性半导体存储器件以消除缺陷的方法包括监测包含在半导体封装中的非易失性半导体存储器件的存储器耐久性指示器。确定记忆耐力指示符是否超过预定义的限制。最后，响应于确定存储器耐力指示符超出预定义的限制，器件被退火。

60. 发明申请

US20070162825A1 Unidirectional error code transfer for a bidirectional data link 有权
标题翻译：双向数据链路的单向错误代码传输
公开(公告)号：US20070162825A1
公开(公告)日：2007-07-12
申请号：US11330524
申请日：2006-01-11
申请人： Yuanlong Wang , Frederick Ware
发明人： Yuanlong Wang , Frederick Ware
IPC分类号： G11C29/00
CPC分类号： G06F11/0727 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/073 , G06F11/0751 , G06F11/076 , G06F11/0793 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1044 , G06F11/1068 , G06F11/1402 , G06F13/4286 , H03M13/09 , H03M13/29 , H03M13/2906 , H03M13/611 , H04L1/0003 , H04L1/0008 , H04L1/0061 , H04L1/08 , H04L1/1867 , H04L2001/0093
摘要： A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
摘要翻译：控制器包括要耦合到第一链路以传送双向数据的链路接口和用于发送单向错误检测信息的第二链路。编码器将动态地将第一错误检测信息添加到写入数据的至少一部分。耦合到链路接口的发射机是发送写入数据。延迟元件耦合到编码器的输出。耦合到链路接口的接收机是接收对应于写数据的至少一部分的第二错误检测信息。错误检测逻辑耦合到来自延迟元件的输出和来自接收器的输出。错误检测逻辑是通过比较第一错误检测信息和第二错误检测信息来确定写入数据的至少一部分中的错误，并且如果检测到错误则是断言错误状况。

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