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51. 发明授权

US08169027B2 Substrate band gap engineered multi-gate pMOS devices 有权
标题翻译：基板带隙工程多栅极pMOS器件
公开(公告)号：US08169027B2
公开(公告)日：2012-05-01
申请号：US12757917
申请日：2010-04-09
申请人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta
发明人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta
IPC分类号： H01L29/66
CPC分类号： H01L29/78687 , H01L29/66545 , H01L29/785 , H01L29/78609
摘要： A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.
摘要翻译：多栅极晶体管和形成多栅极晶体管的方法，所述多栅极晶体管包括具有上部和下部的鳍。所述上部具有第一带隙，并且所述下部具有与所述第一带隙和所述第二带隙的第二带隙，所述第二带隙被设计成阻止电流从所述上部向下部流动。多栅极晶体管还包括具有与所述上部和所述下部电耦合的侧壁的栅极结构和位于鳍下方的衬底。

52. 发明申请

US20100193840A1 SUBSTRATE BAND GAP ENGINEERED MULTI-GATE PMOS DEVICES 有权
标题翻译：基板带隙工程多栅极PMOS器件
公开(公告)号：US20100193840A1
公开(公告)日：2010-08-05
申请号：US12757917
申请日：2010-04-09
申请人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta
发明人： Brian S. Doyle , Been-Yih Jin , Jack T. Kavalieros , Suman Datta
IPC分类号： H01L27/088
CPC分类号： H01L29/78687 , H01L29/66545 , H01L29/785 , H01L29/78609
摘要： A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion. The upper portion having a first band gap and the lower portion having a second band gap with the first band gap and the second band gap designed to inhibit current flow from the upper portion to the lower portion. The multi-gate transistor further including a gate structure having sidewalls electrically coupled with said upper portion and said lower portion and a substrate positioned below the fin.
摘要翻译：多栅极晶体管和形成多栅极晶体管的方法，所述多栅极晶体管包括具有上部和下部的鳍。所述上部具有第一带隙，并且所述下部具有与所述第一带隙和所述第二带隙的第二带隙，所述第二带隙被设计成阻止电流从所述上部向下部流动。多栅极晶体管还包括具有与所述上部和所述下部电耦合的侧壁的栅极结构和位于鳍下方的衬底。

53. 发明授权

US07521775B2 Protection of three dimensional transistor structures during gate stack etch 有权
标题翻译：在栅堆叠蚀刻期间保护三维晶体管结构
公开(公告)号：US07521775B2
公开(公告)日：2009-04-21
申请号：US11452883
申请日：2006-06-13
申请人： Brian S. Doyle , Uday Shah , Been-Yih Jin , Jack T. Kavalieros
发明人： Brian S. Doyle , Uday Shah , Been-Yih Jin , Jack T. Kavalieros
IPC分类号： H01L29/06
CPC分类号： H01L29/7851 , H01L29/66795
摘要： Embodiments of the invention include apparatuses and methods relating to three dimensional transistors having high-k dielectrics and metal gates with fins protected by a hard mask layer on their top surface. In one embodiment, the hard mask layer includes an oxide.
摘要翻译：本发明的实施例包括与具有高k电介质的三维晶体管和金属栅极相关的装置和方法，其翅片由其顶表面上的硬掩模层保护。在一个实施例中，硬掩模层包括氧化物。

54. 发明申请

US20090004868A1 Amorphous silicon oxidation patterning 审中-公开
标题翻译：非晶硅氧化图案化
公开(公告)号：US20090004868A1
公开(公告)日：2009-01-01
申请号：US11824489
申请日：2007-06-29
申请人： Brian S. Doyle , Uday Shah , Jack T. Kavalieros
发明人： Brian S. Doyle , Uday Shah , Jack T. Kavalieros
IPC分类号： H01L21/311
CPC分类号： H01L21/3086 , H01L27/10861 , H01L28/90
摘要： In one embodiment, a method comprises forming a sacrificial amorphous silicon layer on a semiconductor substrate, forming a hardmask on the amorphous silicon layer, etching one or more lines in the sacrificial amorphous silicon layer, growing oxide structures on the amorphous silicon layer, and forming a trench in the semiconductor substrate between the oxide structures.
摘要翻译：在一个实施例中，一种方法包括在半导体衬底上形成牺牲非晶硅层，在非晶硅层上形成硬掩模，蚀刻牺牲非晶硅层中的一条或多条线，在非晶硅层上生长氧化物结构，以及形成氧化物结构之间的半导体衬底中的沟槽。

55. 发明申请

US20080237751A1 CMOS Structure and method of manufacturing same 审中-公开
标题翻译： CMOS结构及其制造方法
公开(公告)号：US20080237751A1
公开(公告)日：2008-10-02
申请号：US11731163
申请日：2007-03-30
申请人： Uday Shah , Brian S. Doyle , Jack T. Kavalieros , Willy Rachmady
发明人： Uday Shah , Brian S. Doyle , Jack T. Kavalieros , Willy Rachmady
IPC分类号： H01L21/8238
CPC分类号： H01L21/82385 , H01L29/785
摘要： A CMOS structure includes a substrate (110, 310), an electrically insulating layer (120, 320) over the substrate, NMOS (130, 330) and PMOS (140, 340) semiconducting structures over the electrically insulating layer, and a dielectric layer (150, 350) having first (151, 351) and second (152, 352) portions over, respectively, the NMOS and PMOS semiconducting structures. The NMOS and PMOS semiconducting structures have, respectively, a first height (135, 335) and a second height (145, 345). The CMOS structure further includes a first electrically conducting layer (160, 360) over the first portion of the dielectric layer, a second electrically conducting layer (170, 370) over the second portion of the dielectric layer and thicker than the first electrically conducting layer, a first polysilicon layer (180, 780) over the first electrically conducting layer, and a second polysilicon layer (190, 790) over the second electrically conducting layer and thinner than the first polysilicon layer.
摘要翻译： CMOS结构包括衬底（110,310），衬底上的电绝缘层（120,320），电绝缘层上的NMOS（130,330）和PMOS（140,340）半导体结构，以及介电层（150,350）分别在NMOS和PMOS半导体结构之上具有第一（151,351）和第二（152,352）部分。 NMOS和PMOS半导体结构分别具有第一高度（135,335）和第二高度（145,345）。 CMOS结构还包括位于电介质层的第一部分上的第一导电层（160,360），在介电层的第二部分上方的第二导电层（170,370），并且比第一导电层，在所述第一导电层上方的第一多晶硅层（180,780）以及所述第二导电层上的第二多晶硅层（190,790）并且比所述第一多晶硅层更薄。

56. 发明申请

US20080157225A1 SRAM and logic transistors with variable height multi-gate transistor architecture 审中-公开
标题翻译：具有可变高度多栅极晶体管结构的SRAM和逻辑晶体管
公开(公告)号：US20080157225A1
公开(公告)日：2008-07-03
申请号：US11648521
申请日：2006-12-29
申请人： Suman Datta , Brian S. Doyle , Jack T. Kavalieros , Yih Wang
发明人： Suman Datta , Brian S. Doyle , Jack T. Kavalieros , Yih Wang
IPC分类号： H01L21/336 , H01L29/768
CPC分类号： H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/66795 , H01L29/7851
摘要： Multi-gate transistors having different channel widths formed on non-planar semiconductor bodies have different sidewall heights and method of manufacturing the same. In an embodiment, a multi-gate SRAM transistor is formed on a non-planar semiconductor body having a greater sidewall height than a non-planar semiconductor body utilized for a multi-gate logic transistor to improve performance of SRAM and logic transistors formed on the same substrate. In another embodiment, to reduce cell area, a first SRAM transistor is formed on a non-planar semiconductor body having a greater sidewall height than a non-planar semiconductor body utilized for a second multi-gate SRAM transistor.
摘要翻译：形成在非平面半导体主体上的具有不同沟道宽度的多栅极晶体管具有不同的侧壁高度及其制造方法。在一个实施例中，多栅极SRAM晶体管形成在具有比用于多栅极逻辑晶体管的非平面半导体主体更大的侧壁高度的非平面半导体主体上，以改善在栅极上形成的SRAM和逻辑晶体管的性能相同的底物。在另一个实施例中，为了减小单元面积，第一SRAM晶体管形成在具有比用于第二多栅极SRAM晶体管的非平面半导体主体更大的侧壁高度的非平面半导体本体上。

57. 发明申请

US20080003755A1 Sacrificial oxide layer which enables spacer over-etch in tri-gate architectures 审中-公开
标题翻译：牺牲氧化物层，其在三栅结构中实现间隔体过蚀刻
公开(公告)号：US20080003755A1
公开(公告)日：2008-01-03
申请号：US11479713
申请日：2006-06-30
申请人： Uday Shah , Willy Rachmady , Jack T. Kavalieros , Brian S. Doyle
发明人： Uday Shah , Willy Rachmady , Jack T. Kavalieros , Brian S. Doyle
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L29/66795 , H01L29/7851
摘要： Embodiments of methods and apparatus for a sacrificial oxide layer which enables spacer over-etch in multi-gate architectures are generally described herein. Other embodiments may be described and claimed.
摘要翻译：这里通常描述了能够在多门体系结构中实现间隔物过蚀刻的牺牲氧化物层的方法和装置的实施例。可以描述和要求保护其他实施例。

58. 发明授权

US06972225B2 integrating n-type and P-type metal gate transistors 有权
标题翻译：集成n型和P型金属栅极晶体管
公开(公告)号：US06972225B2
公开(公告)日：2005-12-06
申请号：US10946502
申请日：2004-09-20
申请人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
发明人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
IPC分类号： H01L21/3213 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66545 , H01L21/32134 , H01L21/32137 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/7833 , Y10S438/926
摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.
摘要翻译：至少p型和n型半导体器件沉积在包含金属或金属合金栅极的半导体晶片上。更具体地，在具有n型和p型金属栅极的半导体晶片上形成互补金属氧化物半导体（CMOS）器件。

59. 发明授权

US06858483B2 Integrating n-type and p-type metal gate transistors 有权
标题翻译：集成n型和p型金属栅晶体管
公开(公告)号：US06858483B2
公开(公告)日：2005-02-22
申请号：US10327293
申请日：2002-12-20
申请人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
发明人： Mark Doczy , Justin K. Brask , Steven J. Keating , Chris E. Barns , Brian S. Doyle , Michael L. McSwiney , Jack T. Kavalieros , John P. Barnak
IPC分类号： H01L21/3213 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66545 , H01L21/32134 , H01L21/32137 , H01L21/823842 , H01L29/495 , H01L29/4966 , H01L29/7833 , Y10S438/926
摘要： At least a p-type and n-type semiconductor device deposited upon a semiconductor wafer containing metal or metal alloy gates. More particularly, a complementary metal-oxide-semiconductor (CMOS) device is formed on a semiconductor wafer having n-type and p-type metal gates.
摘要翻译：至少p型和n型半导体器件沉积在包含金属或金属合金栅极的半导体晶片上。更具体地，在具有n型和p型金属栅极的半导体晶片上形成互补金属氧化物半导体（CMOS）器件。

60. 发明申请

US20100163945A1 Embedded memory cell and method of manufacturing same 有权
标题翻译：嵌入式存储单元及其制造方法
公开(公告)号：US20100163945A1
公开(公告)日：2010-07-01
申请号：US12319101
申请日：2008-12-30
申请人： Jack T. Kavalieros , Niloy Mukherjee , Gilbert Dewey , Dinesh Somasekhar , Brian S. Doyle
发明人： Jack T. Kavalieros , Niloy Mukherjee , Gilbert Dewey , Dinesh Somasekhar , Brian S. Doyle
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L29/66181 , H01L27/10832 , H01L27/10861 , H01L27/10867 , H01L27/1087 , H01L27/10876 , H01L28/90 , H01L29/66666 , H01L29/7827
摘要： An embedded memory cell includes a semiconducting substrate (110), a transistor (120) having a source/drain region (121) at least partially embedded in the semiconducting substrate, and a capacitor (130) at least partially embedded in the semiconducting substrate. The capacitor includes a first electrode (131) and a second electrode (132) that are electrically isolated from each other by a first electrically insulating material (133). The first electrode is electrically connected to the semiconducting substrate and the second electrode is electrically connected to the source/drain region of the transistor.
摘要翻译：嵌入式存储单元包括半导体衬底（110），具有至少部分地嵌入在半导体衬底中的源极/漏极区域（121）的晶体管（120）以及至少部分地嵌入在半导体衬底中的电容器（130）。电容器包括通过第一电绝缘材料（133）彼此电绝缘的第一电极（131）和第二电极（132）。第一电极电连接到半导体衬底，第二电极电连接到晶体管的源极/漏极区域。

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