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51. 发明授权

US4688152A Molded pin grid array package GPT 失效
标题翻译：模压针阵列封装GPT
公开(公告)号：US4688152A
公开(公告)日：1987-08-18
申请号：US895395
申请日：1986-08-11
申请人： Chok J. Chia
发明人： Chok J. Chia
IPC分类号： H01L23/498 , H05K7/06
CPC分类号： H01L23/49827 , H01L2224/48091 , Y10T29/49146
摘要： A pin-grid package is created by starting with printed wiring boards that have plated through holes that can accommodate wire pins. Pins are secured in position to extend outward from one face of the PW board in the form of a pin grid array of the desired configuration which is typically a plurality of concentric rings thereby creating a square grid pattern of predetermined spacing. The opposing PW board face includes a central pin-free area to which is secured a semiconductor die. This face of the PW board includes a plurality of wiring traces that connect each pin to an array that surrounds the semiconductor die. The traces are connected to the bonding pads of the semiconductor die by either wire bonds or a spider assembly using tape assembly bonding. The PW board is located in a mold that has a flat faced first platen that contains cut-out regions that will accommodate the package pins. The other flat-faced mold platen contains molding cavities that are in registry with and slightly larger than the PW boards. The mold cavities include a series of ribs that are distributed around the cavity periphery. These ribs bear against the PW board when the mold is assembled so that the PW board is centered and pressed against the flat face of first platen in the region outboard of the pin-grid pattern. When a liquified plastic encapsulant is forced into the mold the cavities will be filled and the liquid will be excluded from the pin side of the PW board.
摘要翻译：通过从具有电镀通孔的印刷电路板开始，可以容纳线引脚，从而创建一个针格栅封装。引脚被固定就位，从PW板的一个面向外延伸，形式为通常是多个同心环的所需结构的销栅格阵列形式，从而产生预定间隔的正方形网格图案。相对的PW板面包括固定半导体管芯的中心无引脚区域。 PW板的该面包括将每个引脚连接到围绕半导体管芯的阵列的多个布线迹线。迹线通过线接合或者使用带组件接合的蜘蛛组件连接到半导体管芯的接合焊盘。 PW板位于模具中，该模具具有平坦的第一压板，其包含将容纳封装销的切口区域。另一个平面模具压板包含与PW板对准并略大的模制腔。模腔包括分布在腔周边周围的一系列肋。当模具组装时，这些肋承载在PW板上，使得PW板在针脚格栅图案外侧的区域中心并压靠在第一压板的平面上。当液态塑料密封剂被迫进入模具时，空腔将被填充，并且液体将从PW板的销侧排除。

52. 发明授权

US07804167B2 Wire bond integrated circuit package for high speed I/O 有权
标题翻译： Wire Bond集成电路封装，适用于高速I / O
公开(公告)号：US07804167B2
公开(公告)日：2010-09-28
申请号：US11565701
申请日：2006-12-01
申请人： Clifford Fishley , Abiola Awujoola , Leonard Mora , Amar Amin , Maurice Othieno , Chok J. Chia
发明人： Clifford Fishley , Abiola Awujoola , Leonard Mora , Amar Amin , Maurice Othieno , Chok J. Chia
IPC分类号： H01L23/528 , H01L21/768
CPC分类号： H01L23/66 , H01L23/49838 , H01L23/50 , H01L24/45 , H01L24/48 , H01L2224/451 , H01L2224/45147 , H01L2224/48233 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00015 , H01L2224/05599
摘要： An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate, and a first plurality of bond fingers formed immediately adjacent to the ground bonding ring for attaching a first set of I/O signal bond wires between the package substrate and the die.
摘要翻译：一种集成电路封装，包括封装基板，形成在封装基板上的管芯安装焊盘，用于将管芯固定到封装基板;形成在封装基板上的接地环，用于将芯和I / O接地线连接在管芯和管芯之间; 所述封装基板和紧邻所述接地环形成的第一多个接合指，用于在所述封装基板和所述管芯之间附接第一组I / O信号接合线。

53. 发明申请

US20100067207A1 SEMICONDUCTOR PACKAGE AND METHOD USING ISOLATED VSS PLANE TO ACCOMMADATE HIGH SPEED CIRCUITRY GROUND ISOLATION 有权
标题翻译：半导体封装和使用隔离的VSS平面到接地高速电路分离的方法
公开(公告)号：US20100067207A1
公开(公告)日：2010-03-18
申请号：US12625457
申请日：2009-11-24
申请人： Maurice O. Othieno , Chok J. Chia , Amar J. Amin
发明人： Maurice O. Othieno , Chok J. Chia , Amar J. Amin
IPC分类号： H01R9/00 , H01L23/48
CPC分类号： H01L23/50 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L2224/05553 , H01L2224/48091 , H01L2224/4943 , H01L2225/06562 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/10162 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/3025 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.
摘要翻译：本发明的实施例包括半导体集成电路封装，其包括可以具有附接到其上的集成电路管芯的衬底。该封装包括与用于接地封装的低速电路的地平面电隔离的专用高速接地层。

54. 发明申请

US20080128919A1 WIRE BOND INTEGRATED CIRCUIT PACKAGE FOR HIGH SPEED I/O 有权
标题翻译：用于高速I / O的线束集成电路封装
公开(公告)号：US20080128919A1
公开(公告)日：2008-06-05
申请号：US11565701
申请日：2006-12-01
申请人： Clifford Fishley , Abiola Awujoola , Leonard Mora , Amar Amin , Maurice Othieno , Chok J. Chia
发明人： Clifford Fishley , Abiola Awujoola , Leonard Mora , Amar Amin , Maurice Othieno , Chok J. Chia
IPC分类号： H01L23/49 , H01L21/44
CPC分类号： H01L23/66 , H01L23/49838 , H01L23/50 , H01L24/45 , H01L24/48 , H01L2224/451 , H01L2224/45147 , H01L2224/48233 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00015 , H01L2224/05599
摘要： An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate, and a first plurality of bond fingers formed immediately adjacent to the ground bonding ring for attaching a first set of I/O signal bond wires between the package substrate and the die.
摘要翻译：一种集成电路封装，包括封装基板，形成在封装基板上的管芯安装焊盘，用于将管芯固定到封装基板;形成在封装基板上的接地环，用于将芯和I / O接地线连接在管芯和管芯之间; 所述封装衬底以及紧邻所述接地环形成的第一多个接合指，用于在所述封装衬底和所述管芯之间附接第一组I / O信号接合线。

55. 发明授权

US06991147B2 Insulated bonding wire tool for microelectronic packaging 失效
标题翻译：用于微电子封装的绝缘接合线工具
公开(公告)号：US06991147B2
公开(公告)日：2006-01-31
申请号：US10642706
申请日：2003-08-18
申请人： Chok J. Chia , Owai H. Low , Ramaswamy Ranganathan
发明人： Chok J. Chia , Owai H. Low , Ramaswamy Ranganathan
IPC分类号： B23K31/02 , B05D5/12
CPC分类号： H01L24/85 , H01L23/4952 , H01L24/45 , H01L24/48 , H01L24/78 , H01L2224/05554 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48599 , H01L2224/48699 , H01L2224/78301 , H01L2224/8502 , H01L2224/85181 , H01L2224/8592 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01079 , H01L2924/20753 , H01L2924/06 , H01L2924/00 , H01L2224/85399 , H01L2224/05599
摘要： A method for insulating a bonding wire that includes the steps of attaching a bonding wire to a bond pad and coating the bonding wire with an insulating liquid while drawing the bonding wire through a bond tool from the bond pad to a package lead.
摘要翻译：一种用于绝缘接合线的方法，包括以下步骤：将接合线附接到接合焊盘，并且用绝缘液体涂覆接合线，同时将接合线通过接合工具从接合焊盘牵引到封装引线。

56. 发明授权

US06285077B1 Multiple layer tape ball grid array package 有权
标题翻译：多层磁带球栅阵列封装
公开(公告)号：US06285077B1
公开(公告)日：2001-09-04
申请号：US09377887
申请日：1999-08-19
申请人： Chok J. Chia , Seng-Sooi Allen Lim , Qwai Hoong Low
发明人： Chok J. Chia , Seng-Sooi Allen Lim , Qwai Hoong Low
IPC分类号： H01L2348
CPC分类号： H01L23/3128 , H01L23/49833 , H01L24/48 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A package for an integrated circuit is disclosed. The package comprises two layers (a top layer and a bottom layer) of flexible tape, each of which has a top surface and a bottom surface, with metal traces on the top surface. A die is mounted on top of the two layers and wire bonds connect bond pads on the die to metal traces on each of the two flexible tapes. The metal traces are routed along the top surfaces of the flexible tapes and are coupled to solder balls through holes in the tapes. These solder balls are mounted along the bottom of the package and serve as the electrical interface to a printed circuit board. Additional holes in the bottom layer tape allow solder balls to extend through the bottom layer tape so that they may be electrically coupled to traces on the top layer tape.
摘要翻译：公开了一种用于集成电路的封装。该包装包括柔性带的两层（顶层和底层），每层具有顶表面和底表面，顶表面具有金属迹线。模具安装在两层的顶部，引线接合将模具上的接合焊盘连接到两个柔性带中的每一个上的金属迹线。金属迹线沿着柔性带的顶表面布线，并通过带中的孔耦合到焊球。这些焊球沿着封装的底部安装并用作印刷电路板的电接口。底层带中的另外的孔允许焊球延伸穿过底层带，使得它们可以电耦合到顶层带上的迹线。

57. 发明授权

US5901437A Method for planarizing an array of solder balls 失效
公开(公告)号：US5901437A
公开(公告)日：1999-05-11
申请号：US960831
申请日：1997-10-30
申请人： Patrick Variot , Chok J. Chia , Robert T. Trabucco
发明人： Patrick Variot , Chok J. Chia , Robert T. Trabucco
IPC分类号： H01L21/00 , H01L21/48 , H05K3/34 , H05K13/04
CPC分类号： H01L21/67092 , H01L21/4853 , H01L2224/0401 , H01L2224/0603 , H01L2224/1403 , H01L2224/75 , H01L2224/75251 , H01L2224/75743 , H01L2924/3511 , H05K3/3431 , H05K3/3436 , H05K3/3457 , H05K2201/094 , H05K2201/10734 , H05K2203/0278 , Y02P70/613 , Y10S29/044 , Y10T29/49144 , Y10T29/49149 , Y10T29/53191
摘要： A method for mounting an integrated circuit includes a plurality of solder balls arrayed on the bottom surface of a package of the integrated circuit onto to a circuit board. These solder balls provide for surface mounting of the integrated circuit to a circuit board by solder reflow. The array of solder balls can be planarized so that each of the plural solder balls participate in defining a truly planar solder ball contact array for the integrated circuit package. Methods of manufacturing the integrated circuit with a package having planarized solder balls in an array dependent from a bottom surface thereof are set forth. The truly planarized solder ball contact array of the integrated circuit package affords nearly absolute reliability in forming of surface-mount electrical connections between the integrated circuit package and the circuit board on which the package is to mount. Additionally, the planarized solder ball contacts locally compensate individually for warpage of the integrated circuit package by variation in the individual dimensions of dependency of each solder ball below the bottom surface of the package.

58. 发明授权

US5869889A Thin power tape ball grid array package 失效
标题翻译：薄电动带球栅阵列封装
公开(公告)号：US5869889A
公开(公告)日：1999-02-09
申请号：US840614
申请日：1997-04-21
申请人： Chok J. Chia , Patrick Variot , Maniam Alagaratnam
发明人： Chok J. Chia , Patrick Variot , Maniam Alagaratnam
IPC分类号： H01L23/29 , H01L21/60 , H01L23/12 , H01L23/24 , H01L23/31 , H01L23/36 , H01L23/498 , H01L23/34
CPC分类号： H01L23/36 , H01L23/24 , H01L23/4985 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L24/48 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/181
摘要： An integrated circuit package includes a heatspreader which is formed to have a centrally disposed recessed portion between planar surfaces, and flex tape extending from the planar surfaces into the centrally disposed surface. A semiconductor chip is mounted on the centrally disposed surface between the flex tape, and wire bonds interconnect bonding pads on the chip to the metal interconnect patterns on the flex tape. Plastic molding or epoxy is then applied to encapsulate the chip and wire bonding in the centrally disposed planar surface of the heat spreader. The package is then readily mounted on a motherboard using solder balls.
摘要翻译：集成电路封装包括散热器，其形成为在平面之间具有居中设置的凹部，以及从平面延伸到中心设置表面的柔性带。半导体芯片安装在柔性带之间的中央布置的表面上，并且引线将芯片上的接合焊盘互连到柔性带上的金属互连图案。然后施加塑料模制或环氧树脂以将芯片和引线接合封装在散热器的中心设置的平坦表面中。然后使用焊球将封装容易地安装在母板上。

59. 发明授权

US5789811A Surface mount peripheral leaded and ball grid array package 失效
公开(公告)号：US5789811A
公开(公告)日：1998-08-04
申请号：US725735
申请日：1996-10-04
申请人： Chok J. Chia , Patrick Variot
发明人： Chok J. Chia , Patrick Variot
IPC分类号： H01L23/12 , H01L23/24 , H01L23/31 , H01L23/495 , H01L23/498 , H05K3/34 , H01L23/02
CPC分类号： H01L23/24 , H01L23/3128 , H01L23/49531 , H01L23/49811 , H01L23/49816 , H05K3/341 , H01L2224/05554 , H01L2224/16 , H01L2224/48091 , H01L24/48 , H01L2924/00014 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/16195 , H01L2924/181 , H05K2201/10659 , H05K2201/10681 , H05K2201/10689 , H05K2201/10734 , Y02P70/613
摘要： A surface mounted integrated circuit die package includes a group of peripheral leads extending laterally outwardly from the perimeter of the package and also includes an array of solder balls on the bottom of the package. The arrangement provides for a greater number of input/output connections to a die package by utilizing both peripheral leads and a ball grid array without requiring increases in package size or a reduction in the width of electrically conductive interconnections.

60. 发明授权

US5557150A Overmolded semiconductor package 失效
标题翻译：包覆半导体封装
公开(公告)号：US5557150A
公开(公告)日：1996-09-17
申请号：US429605
申请日：1995-04-27
申请人： Patrick Variot , Chok J. Chia
发明人： Patrick Variot , Chok J. Chia
IPC分类号： G03F7/20 , H01L23/31 , H01L23/495 , H01L23/498 , H01L23/544 , H01L29/06 , H01L23/28
CPC分类号： G03F7/70433 , H01L23/3121 , H01L23/49517 , H01L23/49541 , H01L23/49838 , H01L23/49861 , H01L23/544 , H01L2223/54473 , H01L2224/48091 , H01L2224/48227 , H01L2224/49109 , H01L2224/73265 , H01L24/48 , H01L24/49 , H01L29/0657 , H01L2924/00014 , H01L2924/01078 , H01L2924/14 , H01L2924/15151 , H01L2924/15162 , H01L2924/15311 , H01L2924/15312 , H01L2924/181 , H01L2924/1815 , H01L2924/18301
摘要： A technique for providing partially and fully overmolded semiconductor packages is described which prevents delamination (detachment) of the molding compound from the substrate by allowing the molding compound to flow through holes in the substrate and forming it into rivet-like anchors on the opposite side of the substrate. Various shapes of rivet-like anchors are described. Different embodiments provide for the formation of molded standoffs and locating pins integral to the anchor structures.
摘要翻译：描述了一种用于提供部分和完全包覆模制的半导体封装的技术，其通过允许模塑料流过衬底中的孔并将其形成铆钉状锚固体，从而防止模塑料从衬底的分层（脱离）底物。描述了各种形状的铆钉状锚固件。不同的实施例提供模制支座的形成和与锚结构一体的定位销。

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