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    • 54. 发明授权
    • Lateral DMOS transistor and method for the production thereof
    • 侧面DMOS晶体管及其制造方法
    • US07973333B2
    • 2011-07-05
    • US11730514
    • 2007-04-02
    • Franz DietzVolker DudekThomas HoffmannMichael GrafStefan Schwantes
    • Franz DietzVolker DudekThomas HoffmannMichael GrafStefan Schwantes
    • H01L29/66
    • H01L29/66659H01L29/42368H01L29/66681H01L29/7816H01L29/7835
    • A lateral DMOS-transistor is provided that includes a MOS-diode made of a semi-conductor material of a first type of conductivity, a source-area of a second type of conductivity and a drain-area of a second type of conductivity which is separated from the MOS-diode by a drift region made of a semi-conductor material of a second type of conductivity which is at least partially covered by a dielectric gate layer which also covers the semi-conductor material of the MOS-diode. The dielectric gate-layer comprises a first region of a first thickness and a second region of a second thickness. The first region covers the semi-conductor material of the MOS-diode and the second region is arranged on the drift region. A transition takes place from the first thickness to the second thickness such that an edge area of the drift region which is oriented towards the MOS-diode is arranged below the second area of the gate layer. The invention also relates to a method for the production of these types of DMOS-transistors.
    • 提供了一种横向DMOS晶体管,其包括由第一导电类型的半导体材料制成的MOS二极管,第二导电类型的源极区域和第二导电类型的漏极区域,其为 通过由第二导电类型的半导体材料制成的漂移区域与MOS二极管分开,所述漂移区域至少部分被还覆盖MOS二极管的半导体材料的介电栅极层覆盖。 介电栅极层包括第一厚度的第一区域和第二厚度的第二区域。 第一区域覆盖MOS二极管的半导体材料,第二区域布置在漂移区域上。 从第一厚度到第二厚度发生转变,使得朝向MOS二极管定向的漂移区的边缘区域布置在栅极层的第二区域的下方。 本发明还涉及一种用于生产这些类型的DMOS晶体管的方法。
    • 59. 发明申请
    • REDUCED ELECTRIC FIELD DMOS USING SELF-ALIGNED TRENCH ISOLATION
    • 使用自对准TRENCH隔离的减少电场DMOS
    • US20080173940A1
    • 2008-07-24
    • US12018721
    • 2008-01-23
    • Gayle W. MillerVolker DudekMichael Graf
    • Gayle W. MillerVolker DudekMichael Graf
    • H01L29/78
    • H01L29/7824H01L21/823481H01L29/0653H01L29/0847H01L29/086H01L29/42368H01L29/66659H01L29/66689H01L29/7835
    • A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.
    • 一种制造电子装置的方法和所得到的电子装置。 该方法包括在绝缘体上硅衬底的最上侧形成栅极氧化物; 在所述栅极氧化物上形成第一多晶硅层; 以及在所述第一多晶硅层上形成第一二氧化硅层。 然后在第一二氧化硅层上形成第一氮化硅层,接着形成第二二氧化硅层。 通过所有以前的介电层蚀刻浅沟槽并进入SOI衬底。 蚀刻的沟槽用另一介质层(例如二氧化硅)填充并平坦化。 去除每个前述电介质层,留下电介质层的最上面的侧壁区域暴露以与稍后施加的多晶硅栅极区域接触。 侧壁区域的形成确保全场氧化物厚度,从而产生具有减小的电场和栅极和漂移区域之间的减小的电容的器件。