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51. 发明授权

US06233528B1 Method and device for signal testing 有权
标题翻译：用于信号测试的方法和装置
公开(公告)号：US06233528B1
公开(公告)日：2001-05-15
申请号：US09148949
申请日：1998-09-08
申请人： Jiin Lai , Jyhfong Lin , Hsin-Chieh Lin
发明人： Jiin Lai , Jyhfong Lin , Hsin-Chieh Lin
IPC分类号： G01R1300
CPC分类号： G01R31/31709 , G01R31/3016
摘要： A signal-testing device used with a tester for testing a first signal and a second signal includes a selected signal generator receiving first signal and second signal for generating a selected signal the state of which is changed when first signal and second signal are in specific states, and a signal selector for selectively outputting one of first and second signals in response to the selected signal state. The present invention also provides a signal-testing method including steps of a) generating a selected signal having a plurality of pulses in response to a first signal and a second signal, b) obtaining a plurality of time differences between times when two inter-adjacent respective pulses respectively reach a specific voltage, c) obtaining a plurality of absolute values between two inter-adjacent respective time differences, and d) obtaining a phase difference by dividing by 2 an average value of the absolute values.
摘要翻译：与用于测试第一信号和第二信号的测试仪一起使用的信号测试装置包括接收第一信号的选择信号发生器和用于产生当第一信号和第二信号处于特定状态时其状态改变的选择信号的第二信号以及信号选择器，用于响应于所选择的信号状态选择性地输出第一和第二信号之一。本发明还提供了一种信号测试方法，包括以下步骤：a）响应于第一信号和第二信号产生具有多个脉冲的选定信号，b）获得两个相邻时间之间的多个时间差各个脉冲分别达到特定电压，c）在两个相邻的相应时间差之间获得多个绝对值，以及d）通过将绝对值的平均值除以2来获得相位差。

52. 发明授权

US08700859B2 Transfer request block cache system and method 有权
标题翻译：传输请求块缓存系统和方法
公开(公告)号：US08700859B2
公开(公告)日：2014-04-15
申请号：US12829343
申请日：2010-07-01
申请人： Shuang-Shuang Qin , Jiin Lai , Zhi-Qiang Hui , Xiu-Li Guo
发明人： Shuang-Shuang Qin , Jiin Lai , Zhi-Qiang Hui , Xiu-Li Guo
IPC分类号： G06F12/00
CPC分类号： G06F12/0862
摘要： The present invention is directed to a transfer request block (TRB) cache system and method. A cache is used to store plural TRBs, and a mapping table is utilized to store corresponding TRB addresses in a system memory. A cache controller pre-fetches the TRBs and stores them in the cache according to the content of the mapping table.
摘要翻译：本发明涉及一种传输请求块（TRB）高速缓存系统和方法。高速缓存用于存储多个TRB，并且利用映射表将对应的TRB地址存储在系统存储器中。缓存控制器根据映射表的内容预取TRB并将其存储在缓存中。

53. 发明授权

US08504850B2 Method and controller for power management 有权
标题翻译：电源管理方法和控制器
公开(公告)号：US08504850B2
公开(公告)日：2013-08-06
申请号：US12358441
申请日：2009-01-23
申请人： Chung-Che Wu , Jiin Lai
发明人： Chung-Che Wu , Jiin Lai
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： Power management of a system. A request may be received to enter a first sleep state for a system. One or more processes may be performed to enter the first sleep state in response to the request to enter the first sleep state. A system memory of the system may be stored in a nonvolatile memory (NVM) in response to the request to enter the first sleep state in order to enter a second sleep state. Power may be removed from the system memory after storing the system memory in the NVM in response to the request to enter the first sleep state. After removing power to the system memory, the system may be in the second sleep state.
摘要翻译：一个系统的电源管理可以接收请求以进入系统的第一睡眠状态。响应于进入第一睡眠状态的请求，可以执行一个或多个进程以进入第一睡眠状态。响应于进入第一睡眠状态的请求以进入第二睡眠状态，系统的系统存储器可被存储在非易失性存储器（NVM）中。在将系统存储器存储在NVM中以响应于进入第一睡眠状态的请求时，可以将系统存储器中的电源移除。在取消系统内存的电源后，系统可能处于第二个睡眠状态。

54. 发明授权

US08386908B2 Data transmission methods and universal serial bus host controllers utilizing the same 有权
标题翻译：数据传输方法和通用串行总线主机控制器
公开(公告)号：US08386908B2
公开(公告)日：2013-02-26
申请号：US12872526
申请日：2010-08-31
申请人： Xingchen Chen , Jiin Lai , Di Dai , Shanna Pang
发明人： Xingchen Chen , Jiin Lai , Di Dai , Shanna Pang
IPC分类号： G06F11/10 , H03M13/00
CPC分类号： G06F13/28
摘要： A data transmission method for a universal serial bus (USB) host controller is provided. First, input data is received. A cyclic redundancy check (CRC) result of the input data is calculated, and, simultaneously, the input data is transmitted to a system memory of a host. Then, it is determined whether the input data is the last input data of a data packet. When it is determined that the input data is the last input data of the data packet, the CRC result of the last input data of the data packet is calculated. Thus, the CRC result of the data packet is accumulated. The accumulated CRC result is combined with the last input data, and transmitted the combination to the system memory of the host.
摘要翻译：提供了一种用于通用串行总线（USB）主机控制器的数据传输方法。首先，接收输入数据。计算输入数据的循环冗余校验（CRC）结果，同时将输入数据发送到主机的系统存储器。然后，确定输入数据是否是数据分组的最后输入数据。当确定输入数据是数据分组的最后输入数据时，计算数据分组的最后输入数据的CRC结果。因此，累积了数据分组的CRC结果。累积CRC结果与最后一个输入数据组合，并将组合传输到主机的系统存储器。

55. 发明申请

US20110099305A1 Universal Serial Bus Host Control Methods and Universal Serial Bus Host Controllers 有权
标题翻译：通用串行总线主机控制方法和通用串行总线主机控制器
公开(公告)号：US20110099305A1
公开(公告)日：2011-04-28
申请号：US12906431
申请日：2010-10-18
申请人： Di Dai , Jiin Lai , Zhiqiang Hui , Shanna Pang
发明人： Di Dai , Jiin Lai , Zhiqiang Hui , Shanna Pang
IPC分类号： G06F3/00
CPC分类号： G06F13/385
摘要： A USB host control method is provided for a USB host controller. The USB host controller includes a USB device and a buffer, the USB device includes one or more endpoints. The USB host control method includes the steps of: storing first output data to be sent to a first endpoint into one or more buffer units used for the first endpoint; sending the first output data to the first endpoint; and when a first predetermined response from the first endpoint is received, configuring fake releasing labels and information tags corresponding to the first endpoint in the one or more buffer units, and not releasing the one or more buffer units.
摘要翻译： USB主机控制器提供USB主机控制方式。 USB主机控制器包括USB设备和缓冲器，USB设备包括一个或多个端点。 USB主机控制方法包括以下步骤：将要发送到第一端点的第一输出数据存储为用于第一端点的一个或多个缓冲单元; 将第一输出数据发送到第一端点; 并且当接收到来自所述第一端点的第一预定响应时，配置与所述一个或多个缓冲器单元中的所述第一端点对应的假释放标签和信息标签，并且不释放所述一个或多个缓冲器单元。

56. 发明申请

US20110093640A1 Universal Serial Bus Host Controller and Control Method Thereof 有权
标题翻译：通用串行总线主机控制器及其控制方法
公开(公告)号：US20110093640A1
公开(公告)日：2011-04-21
申请号：US12900309
申请日：2010-10-07
申请人： Zhiqiang Hui , Jiin Lai , Shanna Pang , Di Dai
发明人： Zhiqiang Hui , Jiin Lai , Shanna Pang , Di Dai
IPC分类号： G06F13/36
CPC分类号： G06F13/385 , G06F2213/3812
摘要： A USB host controller is provided. The USB host controller is capable of communicating with multiple USB apparatuses having endpoints and sends a request to a first endpoint. The USB host controller includes a first storage and a first control unit. The first control unit stores endpoint information from the first endpoint into the first storage when the first endpoint issues an unready transaction packet in response to the request. The unready transaction packet indicates that the first endpoint is not ready.
摘要翻译：提供USB主机控制器。 USB主机控制器能够与具有端点的多个USB设备通信，并向第一端点发送请求。 USB主机控制器包括第一存储器和第一控制单元。当第一端点响应于该请求发出未获得的事务分组时，第一控制单元将端点信息从第一端点存储到第一存储器中。未完成的事务数据包指示第一个端点尚未就绪。

57. 发明授权

US07779215B2 Method and related apparatus for accessing memory 有权
标题翻译：用于访问存储器的方法和相关装置
公开(公告)号：US07779215B2
公开(公告)日：2010-08-17
申请号：US10906748
申请日：2005-03-04
申请人： Ming-Shi Liou , Bowei Hsieh , Jiin Lai
发明人： Ming-Shi Liou , Bowei Hsieh , Jiin Lai
IPC分类号： G06F12/06
CPC分类号： G06F13/1684 , G11C2207/2281
摘要： A method for utilizing the multi-channel transmission bandwidth in an asymmetrically arranged memory is provides. The present invention defines symmetrically arranged parts of the memory ranks of the memory as a virtual ranks. If data is stored in symmetrically arranged memory ranks of the memory, channels corresponding to the symmetrically arranged memory ranks could be simultaneously utilized to transfer data. If data is stored in an asymmetrically arranged memory rank of the memory, the channel corresponding to the asymmetrically arranged memory rank could only be utilized to transfer data.
摘要翻译：提供了一种在不对称布置的存储器中利用多通道传输带宽的方法。本发明将存储器的存储器级别的对称布置部分定义为虚拟等级。如果数据存储在存储器的对称布置的存储器级中，则对应于对称排列的存储器级别的通道可以同时用于传送数据。如果数据被存储在存储器的不对称排列的存储器级中，则对应于不对称布置的存储器级的通道只能用于传送数据。

58. 发明授权

US07624286B2 Power management method of north bridge 有权
标题翻译：北桥电力管理方法
公开(公告)号：US07624286B2
公开(公告)日：2009-11-24
申请号：US11215222
申请日：2005-08-30
申请人： Ruei-Ling Lin , Jiin Lai , Hung-Yi Kuo
发明人： Ruei-Ling Lin , Jiin Lai , Hung-Yi Kuo
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3296 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： A power state management method of north bridge. The north bridge monitors power transition state of processor; then adjusting operating clocks and operating voltage of the processor and the main memory according to the determined power state to saving power consumption.
摘要翻译：北桥电力状态管理方法。北桥监控处理器的电源转换状态; 然后根据确定的功率状态调整处理器和主存储器的工作时钟和工作电压，以节省功耗。

59. 发明申请

US20070101026A1 BUS CONTROLLER AND DATA BUFFER SPACE CONFIGURATION METHOD OF THE SAME 审中-公开
标题翻译：总线控制器和数据缓冲器空间配置方法
公开(公告)号：US20070101026A1
公开(公告)日：2007-05-03
申请号：US11538747
申请日：2006-10-04
申请人： Jiin Lai , Chun-Yuan Su , Yuan-Zong Cheng
发明人： Jiin Lai , Chun-Yuan Su , Yuan-Zong Cheng
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F13/4059 , G06F2213/0024
摘要： In a data buffer space configuration method for requesting data from a target device via a bus, a device count of master device coupled to the bus is detected by the operating system. Then, a first data buffer space is configured to the master device if the device count is not greater than a threshold. On the other hand, a second data buffer space is configured to the master device if the device count is greater than the threshold.
摘要翻译：在用于经由总线从目标设备请求数据的数据缓冲器空间配置方法中，操作系统检测耦合到总线的主设备的设备数量。然后，如果设备计数不大于阈值，则将第一数据缓冲区配置给主设备。另一方面，如果设备计数大于阈值，则将第二数据缓冲空间配置到主设备。

60. 发明申请

US20060184757A1 Data memory controller that supports data bus invert 有权
公开(公告)号：US20060184757A1
公开(公告)日：2006-08-17
申请号：US11402700
申请日：2006-04-11
申请人： Bi-Yun Yeh , Jiin Lai , Sheng-Chung Wu
发明人： Bi-Yun Yeh , Jiin Lai , Sheng-Chung Wu
IPC分类号： G06F13/00
CPC分类号： G06F13/1668 , G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： The present invention provides a data memory controller that supports for the invert of data bus. Data transmitted from a memory is received in a chip set, which further transmits the data to a data processing apparatus. While receiving the memory data, the chip set doubles the bandwidth and reduces the frequency, such that the time margin for processing data is increased. In addition, after outputting data to the data processing apparatus, a first frame of data is compared to bus idle state to further reduce frequency of data invert and power consumption.

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