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51. 发明申请

US20050041809A1 Device and method for encrypting data 有权
标题翻译：用于加密数据的设备和方法
公开(公告)号：US20050041809A1
公开(公告)日：2005-02-24
申请号：US10874687
申请日：2004-06-22
申请人： Wieland Fischer , Jean-Pierre Seifert
发明人： Wieland Fischer , Jean-Pierre Seifert
IPC分类号： H04L9/00 , H04L9/06 , H04L9/08 , H04L9/30 , H04K1/00
CPC分类号： H04L9/004 , H04L9/0861
摘要： For a secure encryption of original data the original data are first of all encrypted using an encryption key or an encryption algorithm. The thus obtained data are then again decrypted using a decryption algorithm and a decryption key in order to obtain decrypted data. These data are again used together with the original data in order to calculate an auxiliary key. The decrypted data are then encrypted using the calculated auxiliary key in order to obtain output data. In case of a DFA attack no output of the device is suppressed, but the output result is encrypted using the auxiliary key which deviates from the original encryption key in case of the DFA attack so that an attacker cannot use the output data anymore and the DFA attack is useless.
摘要翻译：对于原始数据的安全加密，原始数据首先使用加密密钥或加密算法进行加密。然后使用解密算法和解密密钥再次对由此获得的数据进行解密，以便获得解密的数据。这些数据再次与原始数据一起使用，以便计算辅助键。然后使用所计算的辅助密钥对解密的数据进行加密，以获得输出数据。在DFA攻击的情况下，没有设备的输出被抑制，但是在DFA攻击的情况下，使用辅助密钥来加密输出结果，该辅助密钥偏离了原始加密密钥，以致攻击者不能再使用输出数据，而DFA 攻击是无用的

52. 发明授权

US07831777B2 Apparatus and method for reducing information leakage between processes sharing a cache 有权
标题翻译：用于减少共享缓存的进程之间的信息泄漏的装置和方法
公开(公告)号：US07831777B2
公开(公告)日：2010-11-09
申请号：US11442229
申请日：2006-05-26
申请人： Michael Neve de Mevergnies , Jean-Pierre Seifert
发明人： Michael Neve de Mevergnies , Jean-Pierre Seifert
IPC分类号： G06F13/14
CPC分类号： G06F12/084 , G06F12/0842 , G06F12/126 , G06F21/556 , G06F2212/1052
摘要： Apparatus and methods for reducing information leakage between processes sharing a cache are disclosed. In one embodiment, an apparatus includes execution logic, a cache memory, and cache security logic. The execution unit is to execute a plurality of processes. The cache memory is to be shared between the plurality of processes. The cache security logic is to cause a stored cache state to be loaded into the cache memory.
摘要翻译：公开了用于减少共享高速缓存的进程之间的信息泄漏的装置和方法。在一个实施例中，一种装置包括执行逻辑，高速缓冲存储器和高速缓存安全逻辑。执行单元执行多个处理。缓存存储器将在多个进程之间共享。缓存安全逻辑是将存储的高速缓存状态加载到高速缓冲存储器中。

53. 发明授权

US07698357B2 Modular multiplication with parallel calculation of the look-ahead parameters 有权
标题翻译：模拟乘法与先行参数的并行计算
公开(公告)号：US07698357B2
公开(公告)日：2010-04-13
申请号：US11165834
申请日：2005-06-23
申请人： Wieland Fischer , Holger Sedlak , Jean-Pierre Seifert
发明人： Wieland Fischer , Holger Sedlak , Jean-Pierre Seifert
IPC分类号： G06F15/00
CPC分类号： G06F7/722
摘要： A device for calculating a multiplication of a multiplier and a multiplicand includes a first performer that performs an exact three operand addition and a second performer that performs an approximated operand addition and a calculator that calculates current look-ahead parameters using the approximated intermediate results. The first performer is further implemented to perform an exact three operand addition in the current iteration step using the exact intermediate result for the current iteration step and using the look-ahead parameters calculated for the current iteration step.
摘要翻译：用于计算乘法器和乘法器的乘法的装置包括执行精确三个操作数相加的第一执行器和执行近似操作数相加的第二执行器，以及使用近似中间结果来计算当前先行参数的计算器。第一执行者进一步实施，以在当前迭代步骤中使用当前迭代步骤的确切中间结果并使用为当前迭代步骤计算的预先参数来执行精确的三操作数添加。

54. 发明授权

US07502814B2 Device and method for generating a pseudorandom sequence of numbers 有权
标题翻译：用于产生数字的伪随机序列的装置和方法
公开(公告)号：US07502814B2
公开(公告)日：2009-03-10
申请号：US11120659
申请日：2005-05-02
申请人： Gerd Dirscherl , Rainer Goettfert , Bernd Meyer , Jean-Pierre Seifert
发明人： Gerd Dirscherl , Rainer Goettfert , Bernd Meyer , Jean-Pierre Seifert
IPC分类号： G06F1/02
CPC分类号： G06F7/584
摘要： A device for generating a pseudorandom sequence of numbers includes a feedforward coupler, which has a plurality of memory units, and a feedback coupler connected between an input and an output of the feedforward coupler. The feedback coupler includes a changeable feedback characteristic and is embodied to change the feedback characteristic depending on a state of a memory unit of the plurality of memory units of the feedforward coupler.
摘要翻译：用于产生伪随机序列序列的装置包括具有多个存储器单元的前馈耦合器和连接在前馈耦合器的输入和输出端之间的反馈耦合器。反馈耦合器包括可变的反馈特性，并且被实现为根据前馈耦合器的多个存储器单元的存储器单元的状态来改变反馈特性。

55. 发明申请

US20070277001A1 Apparatus and method for reducing information leakage between processes sharing a cache 有权
标题翻译：用于减少共享缓存的进程之间的信息泄漏的装置和方法
公开(公告)号：US20070277001A1
公开(公告)日：2007-11-29
申请号：US11442229
申请日：2006-05-26
申请人： Michael Neve de Mevergnies , Jean-Pierre Seifert
发明人： Michael Neve de Mevergnies , Jean-Pierre Seifert
IPC分类号： G06F13/28
CPC分类号： G06F12/084 , G06F12/0842 , G06F12/126 , G06F21/556 , G06F2212/1052
摘要： Apparatus and methods for reducing information leakage between processes sharing a cache are disclosed. In one embodiment, an apparatus includes execution logic, a cache memory, and cache security logic. The execution unit is to execute a plurality of processes. The cache memory is to be shared between the plurality of processes. The cache security logic is to cause a stored cache state to be loaded into the cache memory.
摘要翻译：公开了用于减少共享高速缓存的进程之间的信息泄漏的装置和方法。在一个实施例中，一种装置包括执行逻辑，高速缓冲存储器和高速缓存安全逻辑。执行单元执行多个处理。缓存存储器将在多个进程之间共享。缓存安全逻辑是将存储的高速缓存状态加载到高速缓冲存储器中。

56. 发明授权

US07248700B2 Device and method for calculating a result of a modular exponentiation 有权
标题翻译：用于计算模幂运算结果的装置和方法
公开(公告)号：US07248700B2
公开(公告)日：2007-07-24
申请号：US10789373
申请日：2004-02-27
申请人： Jean-Pierre Seifert , Joachim Velten
发明人： Jean-Pierre Seifert , Joachim Velten
IPC分类号： G06F7/00
CPC分类号： G06F7/723 , G06F2207/7242 , G06F2207/7247 , G06F2207/7271 , H04L9/004 , H04L9/302
摘要： In a device for calculating a result of a modular exponentiation, the Chinese Residue Theorem (CRT) is used, wherein two auxiliary exponentiations are calculated using two auxiliary exponents and two sub-moduli. In order to improve the safety of the RSA CRT calculations against cryptographic attacks, a randomization of the auxiliary exponents and/or a change of the sub-moduli are performed. Thus, there is a safe RSA decryption and RSA encryption, respectively, by means of the calculating time efficient Chinese Residue Theorem.
摘要翻译：在用于计算模幂结果的装置中，使用中文残差定理（CRT），其中使用两个辅助指数和两个子模数计算两个辅助指数。为了提高针对加密攻击的RSA CRT计算的安全性，执行辅助指数的随机化和/或子模块的改变。因此，通过计算时间有效的中国残差定理，分别有一个安全的RSA解密和RSA加密。

57. 发明申请

US20070006306A1 Tamper-aware virtual TPM 有权
标题翻译：防篡改虚拟TPM
公开(公告)号：US20070006306A1
公开(公告)日：2007-01-04
申请号：US11173776
申请日：2005-06-30
申请人： Jean-Pierre Seifert , Ryan Ware
发明人： Jean-Pierre Seifert , Ryan Ware
IPC分类号： G06F12/14
CPC分类号： G06F21/57 , G06F21/554
摘要： Methods, software/firmware and apparatus for implementing a tamper-aware virtual trusted platform module (TPM). Under the method, respective threads comprising a virtual TPM thread and a security-patrol threads are executed on a host processor. In one embodiment, the host processor is a multi-threaded processor having multiple logical processors, and the respective threads are executed on different logical processors. While the virtual TPM thread is used to perform various TPM functions, the security-patrol thread monitors for physical attacks on the processor by implementing various numerical calculation loops, wherein an erroneous calculation is indicative of a physical attack. In response to detection of such an attack, various actions can be taken in view of one or more predefined security policies, such as logging the event, shutting down the platform and/or informing a remote management entity.
摘要翻译：方法，用于实现篡改感知虚拟可信平台模块（TPM）的软件/固件和装置。在该方法下，在主处理器上执行包括虚拟TPM线程和安全巡检线程的相应线程。在一个实施例中，主处理器是具有多个逻辑处理器的多线程处理器，并且相应的线程在不同的逻辑处理器上执行。当虚拟TPM线程用于执行各种TPM功能时，安全巡逻线程通过实现各种数值计算循环来监视对处理器的物理攻击，其中错误的计算表示物理攻击。响应于这种攻击的检测，可以考虑到一个或多个预定义的安全策略来采取各种动作，诸如记录事件，关闭平台和/或通知远程管理实体。

58. 发明申请

US20060067380A1 Device and method for generating a pseudorandom sequence of numbers 有权
公开(公告)号：US20060067380A1
公开(公告)日：2006-03-30
申请号：US11120659
申请日：2005-05-02
申请人： Gerd Dirscherl , Rainer Goettfert , Bernd Meyer , Jean-Pierre Seifert
发明人： Gerd Dirscherl , Rainer Goettfert , Bernd Meyer , Jean-Pierre Seifert
IPC分类号： H04B1/69
CPC分类号： G06F7/584
摘要： A device for generating a pseudorandom sequence of numbers includes a feedforward coupler, which has a plurality of memory units, and a feedback coupler connected between an input and an output of the feedforward coupler. The feedback coupler includes a changeable feedback characteristic and is embodied to change the feedback characteristic depending on a state of a memory unit of the plurality of memory units of the feedforward coupler.

59. 发明申请

US20060064453A1 Modular multiplication with parallel calculation of the look-ahead parameters 有权
标题翻译：模拟乘法与先行参数的并行计算
公开(公告)号：US20060064453A1
公开(公告)日：2006-03-23
申请号：US11165834
申请日：2005-06-23
申请人： Wieland Fischer , Holger Sedlak , Jean-Pierre Seifert
发明人： Wieland Fischer , Holger Sedlak , Jean-Pierre Seifert
IPC分类号： G06F7/52
CPC分类号： G06F7/722
摘要： A device for calculating a multiplication of a multiplier and a multiplicand includes a first performer that performs an exact three operand addition and a second performer that performs an approximated operand addition and a calculator that calculates current look-ahead parameters using the approximated intermediate results. The first performer is further implemented to perform an exact three operand addition in the current iteration step using the exact intermediate result for the current iteration step and using the look-ahead parameters calculated for the current iteration step.
摘要翻译：用于计算乘法器和乘法器的乘法的装置包括执行精确三个操作数相加的第一执行器和执行近似操作数相加的第二执行器，以及使用近似中间结果来计算当前先行参数的计算器。第一执行者进一步实施，以在当前迭代步骤中使用当前迭代步骤的确切中间结果并使用为当前迭代步骤计算的预先参数来执行精确的三操作数添加。

60. 发明申请

US20050149597A1 Device and method for converting a term 有权
标题翻译：用于转换术语的设备和方法
公开(公告)号：US20050149597A1
公开(公告)日：2005-07-07
申请号：US10976249
申请日：2004-10-28
申请人： Wieland Fischer , Jean-Pierre Seifert
发明人： Wieland Fischer , Jean-Pierre Seifert
IPC分类号： G06F7/00 , G06F7/52 , G06F7/535 , G06F7/72
CPC分类号： G06F7/535 , G06F7/72 , G06F7/722
摘要： A device for converting a term comprising a product of a first operand and a second operand into a representation having an integer quotient regarding a modulus and a remainder, the integer quotient being defined by T/N, T being the term and N being the modulus, and the remainder being defined by T mod N, N being the modulus, includes means for modularly reducing the term using the modulus on the one hand and for modularly reducing the term using an auxiliary modulus, which is greater than the modulus, on the other hand to obtain the remainder on the one hand and the auxiliary remainder on the other hand. Both the remainder and the auxiliary remainder are fed into means for combining to obtain the integer quotient. The inventive device makes it possible to calculate even the integer quotient, that is the result of the DIV operation, by performing a command for a modular multiplication existing on conventional cryptoprocessors two times.
摘要翻译：一种用于将包括第一操作数和第二操作数的乘积的项转换成具有关于模数和余数的整数商的表示的装置，所述整数商由T / N定义，T是项，N是模数，其余由T mod N定义，N为模数，包括一方面模块化减少项目的模块，一方面使用模量，并使用大于模数的辅助模量模块化减少术语另一方面要获得剩余部分和另一方面辅助剩余部分。余数和辅助余数都被馈入组合的手段以获得整数商。本发明的装置使得可以通过对存在于常规封装处理器上的模乘进行两次的命令来计算偶数商，即DIV操作的结果。

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