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51. 发明申请

US20080244124A1 Bus system for use with information processing apparatus 失效
标题翻译：与信息处理设备一起使用的总线系统
公开(公告)号：US20080244124A1
公开(公告)日：2008-10-02
申请号：US12155047
申请日：2008-05-29
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on t
摘要翻译：与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以经由其间的数据总线传送数据，取决于t

52. 发明申请

US20070033316A1 Bus system for use with information processing apparatus 失效
标题翻译：与信息处理设备一起使用的总线系统
公开(公告)号：US20070033316A1
公开(公告)日：2007-02-08
申请号：US11543878
申请日：2006-10-06
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/36
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
摘要翻译：与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。

53. 发明授权

US07152130B2 Bus system for use with information processing apparatus 失效
公开(公告)号：US07152130B2
公开(公告)日：2006-12-19
申请号：US11032051
申请日：2005-01-11
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

54. 发明申请

US20050149580A1 Data processing apparatus and network system that outputs quality of service information to a user 失效
公开(公告)号：US20050149580A1
公开(公告)日：2005-07-07
申请号：US11054387
申请日：2005-02-10
申请人： Ryuichi Hattori , Toshihiko Ogura , Takashi Oeda , Koichi Okazawa , Hideki Osaka , Tsunehiro Tobita , Tsutomu Hara
发明人： Ryuichi Hattori , Toshihiko Ogura , Takashi Oeda , Koichi Okazawa , Hideki Osaka , Tsunehiro Tobita , Tsutomu Hara
IPC分类号： G06F15/00 , G06F9/50 , G06F11/32 , G06F12/00 , G06F13/00 , G06F13/368 , G06F15/16 , G06F15/173
CPC分类号： G06F9/5055 , G06F9/5044 , G06F2209/5015 , H04L29/12047 , H04L41/5009 , H04L61/15 , H04L67/36
摘要： In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.

55. 发明授权

US06370577B1 Information processing system having a network and a directory which may be referenced to supply information to an apparatus 有权
标题翻译：具有网络的信息处理系统和可以参考的目录以向设备提供信息
公开(公告)号：US06370577B1
公开(公告)日：2002-04-09
申请号：US09518147
申请日：2000-03-03
申请人： Ryuichi Hattori , Toshihiko Ogura , Takashi Oeda , Koichi Okazawa , Hideki Osaka , Tsunehiro Tobita , Tsutomu Hara
发明人： Ryuichi Hattori , Toshihiko Ogura , Takashi Oeda , Koichi Okazawa , Hideki Osaka , Tsunehiro Tobita , Tsutomu Hara
IPC分类号： G06F1516
CPC分类号： G06F9/5055 , G06F9/5044 , G06F2209/5015 , H04L29/12047 , H04L41/5009 , H04L61/15 , H04L67/36
摘要： In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.
摘要翻译：在通过网络彼此连接的每个信息处理设备中，布置了其功能和性能被注册到其中的服务质量（QOS）表。当信息处理设备另外与网络链接时，其QOS表被自动地注册到网络的本地目录，使得代理将QOS表的内容转换成要经由用户界面提供给用户的服务信息。由于操作，连接到网络的每个信息处理设备的功能和性能的信息被转换成用户的服务信息。因此，用户可以更多地直接接收必要的服务。

56. 发明授权

US6131169A Reliability of crossbar switches in an information processing system 失效
标题翻译：交叉开关在信息处理系统中的可靠性
公开(公告)号：US6131169A
公开(公告)日：2000-10-10
申请号：US460513
申请日：1999-12-14
申请人： Koichi Okazawa , Toshiaki Tarui , Yasuyuki Okada
发明人： Koichi Okazawa , Toshiaki Tarui , Yasuyuki Okada
IPC分类号： G06F13/36 , G06F11/00 , G06F11/20 , G06F15/167
CPC分类号： G06F11/2005 , G06F11/2007
摘要： An information processing apparatus includes a crossbar switch having a plurality of switching circuits for data transfer; connection lines having address data transfer paths of m-bit unit connected to each of the input/output ports of the switching circuits, control signal transfer paths of m-bit unit connected to each of the input/output ports of the control circuits and back-up transfer paths of m-bit unit connected to each of the input/output ports of the back-up circuits; and transfer path processing circuit connected correspondingly to the connection lines constructed by the n-bit provided on each of the processing units, monitored transfer of data and control signal between the processing units through the switching circuit and the control circuit in the crossbar switch, and detected a failure of at least the switching circuit and the control circuit to thereby change the connection of at least one of the failed switching circuit and control circuit to a connection of the back-up circuit.
摘要翻译：一种信息处理设备，包括具有用于数据传送的多个切换电路的交叉开关; 具有连接到开关电路的每个输入/输出端口的m位单元的地址数据传送路径的连接线，连接到控制电路的每个输入/输出端口的m位单元的控制信号传送路径和后面 - 连接到备用电路的每个输入/输出端口的m位单元的传送路径; 以及传送路径处理电路，其对应于由在每个处理单元上提供的n位构成的连接线，通过开关电路和交叉开关中的控制电路在处理单元之间监视的数据传输和控制信号，以及检测到至少开关电路和控制电路的故障，从而将故障切换电路和控制电路中的至少一个的连接改变为备用电路的连接。

57. 发明授权

US6098136A Multiple bus system using a data transfer unit 失效
标题翻译：多总线系统使用数据传输单元
公开(公告)号：US6098136A
公开(公告)日：2000-08-01
申请号：US375356
申请日：1999-08-17
申请人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
发明人： Koichi Okazawa , Koichi Kimura , Hitoshi Kawaguchi , Ichiharu Aburano , Kazushi Kobayashi , Tetsuya Mochida
IPC分类号： G06F13/40 , G06F13/14 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/4027
摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controlling connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.
摘要翻译：与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。控制系统包括总线存储器连接，其控制分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。

58. 发明授权

US6088770A Shared memory multiprocessor performing cache coherency 失效
公开(公告)号：US6088770A
公开(公告)日：2000-07-11
申请号：US30957
申请日：1998-02-26
申请人： Toshiaki Tarui , Koichi Okazawa , Yasuyuki Okada , Toru Shonai , Toshio Okochi , Hideya Akashi
发明人： Toshiaki Tarui , Koichi Okazawa , Yasuyuki Okada , Toru Shonai , Toshio Okochi , Hideya Akashi
IPC分类号： G06F15/177 , G06F12/02 , G06F12/08 , G06F15/17 , G06F13/14
CPC分类号： G06F12/0826 , G06F12/0284 , G06F2212/2542
摘要： A shared memory multiprocessor (SMP) has efficient access to a main memory included in a particular node and a management of partitions that include the nodes. In correspondence with each page of main memory included in a node, a bit stored in a register indicates if the page has been accessed from any other node. In a case where the bit is "0", a cache coherent command to be sent to the other nodes is not transmitted. The bit is reset by software at the time of initialization and memory allocation, and it is set by hardware when the page of the main memory is accessed from any other node. In a case where the interior of an SMP is divided into partitions, the main memory of each node is divided into local and shared areas, for which respectively separate addresses can be designated. In each node, the configuration information items of the shared area and the local area are stored in registers. The command of access to the shared area is multicast to all of the nodes, whereas the command is multicast only to the nodes within the corresponding partition when the local area is accessed.

59. 发明授权

US6035414A Reliability of crossbar switches in an information processing system 失效
公开(公告)号：US6035414A
公开(公告)日：2000-03-07
申请号：US962683
申请日：1997-11-03
申请人： Koichi Okazawa , Toshiaki Tarui , Yasuyuki Okada
发明人： Koichi Okazawa , Toshiaki Tarui , Yasuyuki Okada
IPC分类号： G06F13/36 , G06F11/00 , G06F11/20 , G06F15/167
CPC分类号： G06F11/2005 , G06F11/2007
摘要： An information processing apparatus includes a crossbar switch having a plurality of switching circuits for data transfer; connection lines having address data transfer paths of m-bit unit connected to each of the input/output ports of the switching circuits, control signal transfer paths of m-bit unit connected to each of the input/output ports of the control circuits and back-up transfer paths of m-bit unit connected to each of the input/output ports of the back-up circuits; and transfer path processing circuit connected correspondingly to the connection lines constructed by the n-bit provided on each of the processing units, monitored transfer of data and control signal between the processing units through the switching circuit and the control circuit in the crossbar switch, and detected a failure of at least the switching circuit and the control circuit to thereby change the connection of at least one of the failed switching circuit and control circuit to a connection of the back-up circuit.

60. 发明授权

US5754802A Increasing data transfer efficiency for a read operation in a non-split transaction bus environment by substituting a write operation for the read operation 失效
标题翻译：通过将读取操作替换为读取操作，在非分割事务总线环境中提高数据传输效率
公开(公告)号：US5754802A
公开(公告)日：1998-05-19
申请号：US648424
申请日：1996-05-15
申请人： Koichi Okazawa , Hideki Osaka , Kenichi Saitou
发明人： Koichi Okazawa , Hideki Osaka , Kenichi Saitou
IPC分类号： G06F13/36 , G06F13/12 , G06F13/40 , G06F13/42 , G06F13/00
CPC分类号： G06F13/423 , G06F13/126 , G06F13/4027 , G06F13/4036
摘要： A method and apparatus for increasing data transfer efficiency for a read operation in a non-split transaction bus environment by substituting a write operation for the read operation. The data transfer efficiency is increased and deadlocking is reduced by substituting two write operations (one from an I/O device to a bus controller and the other from the bus controller to the I/O device) for one read operation. Further, the present invention improves the efficiency of data transfer by maintaining the compatibility of a bus specification when DMA of an I/O bus having no split transfer function, such as a PCI bus or inter-I/O transfer, is executed. A processor instructs a data transfer operation to an I/O device or bus conversion adapter. The I/O device or bus conversion adapter connected to a bus outputs a write access, and a bus connection controller connected to the bus receives the write access and reads data in a main memory. The bus connection controller then transfers read data to the I/O device or the bus conversion adapter. Such an operation may also be performed between two I/O devices or bus conversion adapters.
摘要翻译：一种用于通过将写入操作替换为读取操作来增加在非分割事务总线环境中的读取操作的数据传输效率的方法和装置。通过将两个写入操作（一个从I / O设备到总线控制器，另一个从总线控制器到I / O设备）替换为一次读取操作，数据传输效率提高并且死锁降低。此外，本发明通过在不执行诸如PCI总线或I / O转移之类的分离传递功能的I / O总线的DMA执行时，通过维持总线规格的兼容性来提高数据传输的效率。处理器指示对I / O设备或总线转换适配器的数据传输操作。连接到总线的I / O设备或总线转换适配器输出写访问，连接到总线的总线连接控制器接收写入访问并读取主存储器中的数据。总线连接控制器然后将读取的数据传送到I / O设备或总线转换适配器。这样的操作也可以在两个I / O设备或总线转换适配器之间执行。

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