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51. 发明授权

US06830500B2 Slurry for use with fixed-abrasive polishing pads in polishing semiconductor device conductive structures that include copper and tungsten and polishing methods 失效
标题翻译：用于抛光半导体器件导电结构（包括铜和钨）和抛光方法的固定研磨抛光垫的浆料
公开(公告)号：US06830500B2
公开(公告)日：2004-12-14
申请号：US10132827
申请日：2002-04-25
申请人： Dinesh Chopra , Nishant Sinha
发明人： Dinesh Chopra , Nishant Sinha
IPC分类号： B24B100
CPC分类号： B24B37/0056 , B24B37/04 , H01L21/3212
摘要： A method for substantially simultaneously polishing a copper conductive structure of a semiconductor device structure and an adjacent barrier layer includes use of a fixed-abrasive type polishing pad with a substantially abrasive-free slurry in which copper is removed at a rate that is substantially the same as or faster than a rate at which a material, such as tungsten, of the barrier layer is removed. The slurry is formulated so as to oxidize copper at substantially the same rate as or at a faster rate than a material of the barrier layer is oxidized. Thus, copper and the barrier layer material have substantially the same oxidation energies in the slurry or the oxidation energy of the barrier layer material in the slurry may be greater than that of copper. Systems for substantially polishing copper conductive structures and adjacent barrier structures on semiconductor device structures are also disclosed.
摘要翻译：用于基本上同时抛光半导体器件结构和相邻阻挡层的铜导电结构的方法包括使用具有基本上无磨料的浆料的固定研磨型抛光垫，其中铜以基本相同的速率被去除等于或快于去除阻挡层的材料（例如钨）的速率。将浆料配制成以与阻挡层的材料氧化为基本相同的速率或以更快的速率氧化铜。因此，铜和阻挡层材料在浆料中具有基本相同的氧化能量，或者浆料中的阻挡层材料的氧化能可能大于铜的氧化能。还公开了用于在半导体器件结构上基本抛光铜导电结构和相邻阻挡结构的系统。

52. 发明授权

US06759751B2 Constructions comprising solder bumps 有权
标题翻译：包括焊料凸块的构造
公开(公告)号：US06759751B2
公开(公告)日：2004-07-06
申请号：US10425378
申请日：2003-04-28
申请人： Nishant Sinha
发明人： Nishant Sinha
IPC分类号： H01L2348
CPC分类号： C23C18/1605 , H01L21/288 , H01L24/11 , H01L2224/05001 , H01L2224/05023 , H01L2224/05027 , H01L2224/0508 , H01L2224/05571 , H01L2224/131 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/0103 , H01L2924/01046 , H01L2924/01072 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/19041 , Y10T428/24917 , H01L2224/13099
摘要： The invention includes a method of electroless deposition of nickel over an aluminum-containing material. A mass is formed over the aluminum-containing material, with the mass predominantly comprising a metal other than aluminum. The mass is exposed to palladium, and subsequently nickel is electroless deposited over the mass. The invention also includes a method of electroless deposition of nickel over aluminum-containing materials and copper-containing materials. The aluminum-containing materials and copper-containing materials are both exposed to palladium-containing solutions prior to electroless deposition of nickel over the aluminum-containing materials and copper-containing materials. Additionally, the invention includes a method of forming a solder bump over an aluminum-containing material.
摘要翻译：本发明包括在含铝材料上无电沉积镍的方法。在含铝材料上形成质量，其中质量主要包含除铝之外的金属。质量暴露于钯，随后镍在化学物质上无电沉积。本发明还包括在含铝材料和含铜材料上无电沉积镍的方法。在含镍材料和含铜材料上无电沉积镍之前，将含铝材料和含铜材料都暴露于含钯溶液中。此外，本发明包括在含铝材料上形成焊料凸块的方法。

53. 发明授权

US06586043B1 Methods of electroless deposition of nickel, methods of forming under bump metallurgy, and constructions comprising solder bumps 有权
标题翻译：无电沉积镍的方法，形成凸块下冶金的方法以及包括焊料凸块的结构
公开(公告)号：US06586043B1
公开(公告)日：2003-07-01
申请号：US10043431
申请日：2002-01-09
申请人： Nishant Sinha
发明人： Nishant Sinha
IPC分类号： B05D512
CPC分类号： C23C18/1605 , H01L21/288 , H01L24/11 , H01L2224/05001 , H01L2224/05023 , H01L2224/05027 , H01L2224/0508 , H01L2224/05571 , H01L2224/131 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/0103 , H01L2924/01046 , H01L2924/01072 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/19041 , Y10T428/24917 , H01L2224/13099
摘要： The invention includes a method of electroless deposition of nickel over an aluminum-containing material. A mass is formed over the aluminum-containing material, with the mass predominantly comprising a metal other than aluminum. The mass is exposed to palladium, and subsequently nickel is electroless deposited over the mass. The invention also includes a method of electroless deposition of nickel over aluminum-containing materials and copper-containing materials. The aluminum-containing materials and copper-containing materials are both exposed to palladium-containing solutions prior to electroless deposition of nickel over the aluminum-containing materials and copper-containing materials. Additionally, the invention includes a method of forming a solder bump over an aluminum-containing material.
摘要翻译：本发明包括在含铝材料上无电沉积镍的方法。在含铝材料上形成质量，其中质量主要包含除铝之外的金属。质量暴露于钯，随后镍在化学物质上无电沉积。本发明还包括在含铝材料和含铜材料上无电沉积镍的方法。在含镍材料和含铜材料上无电沉积镍之前，将含铝材料和含铜材料都暴露于含钯溶液中。此外，本发明包括在含铝材料上形成焊料凸块的方法。

54. 发明授权

US06551935B1 Slurry for use in polishing semiconductor device conductive structures that include copper and tungsten and polishing methods 有权
标题翻译：用于抛光包括铜和钨的半导体器件导电结构的浆料和抛光方法
公开(公告)号：US06551935B1
公开(公告)日：2003-04-22
申请号：US09653392
申请日：2000-08-31
申请人： Nishant Sinha , Dinesh Chopra
发明人： Nishant Sinha , Dinesh Chopra
IPC分类号： H01L2100
CPC分类号： C23F3/04 , C09G1/02 , C23F3/06 , H01L21/3212
摘要： method for substantially simultaneously polishing a copper conductive structure of a semiconductor device structure and an adjacent barrier layer. The method includes use of a polishing pad with a slurry solution in which copper and a material, such as tungsten, of the barrier layer are removed at substantially the same rate. The slurry is formulated so as to oxidize copper and a material of the barrier layer at substantially the same rates. Thus, copper and the barrier layer material have substantially the same oxidation energies in the slurry. Systems for substantially polishing copper conductive structures and adjacent barrier structures on semiconductor device structures are also disclosed.
摘要翻译：用于基本上同时抛光半导体器件结构的铜导电结构和相邻阻挡层的方法。该方法包括使用具有浆料溶液的抛光垫，其中阻挡层的铜和诸如钨的材料以基本上相同的速率被去除。将浆料配制成以基本上相同的速率氧化铜和阻挡层的材料。因此，铜和阻挡层材料在浆料中具有基本上相同的氧化能。还公开了用于在半导体器件结构上基本抛光铜导电结构和相邻阻挡结构的系统。

55. 发明授权

US06511906B1 Selective CMP scheme 有权
标题翻译：选择性CMP方案
公开(公告)号：US06511906B1
公开(公告)日：2003-01-28
申请号：US09943381
申请日：2001-08-30
申请人： Nishant Sinha
发明人： Nishant Sinha
IPC分类号： H01L214763
CPC分类号： H01L21/3212 , H01L21/7684
摘要： A semiconductor substrate with a plurality of semiconductor devices formed therein is processed by initially forming a silicon nitride insulating layer over the semiconductor devices. Interconnect holes are formed in the insulating layer. The interconnect holes are filled with a silver-based conductive material so that portions of the silver-based conductive material extend beyond the uppermost boundary of the interconnect holes. The device is then chemically and mechanically planarized with a processing slurry selected to be minimally selective of silicon nitride and relatively highly selective of the silver-based conductive material. The processing slurry comprises an abrasive and an oxidizer. In this manner, the portions of the silver-based conductive material extending beyond said uppermost boundary of the interconnect holes are removed.
摘要翻译：通过在半导体器件上初始形成氮化硅绝缘层来处理其中形成有多个半导体器件的半导体衬底。互连孔形成在绝缘层中。互连孔填充有银基导电材料，使得银基导电材料的部分延伸超过互连孔的最上边界。然后将该装置化学和机械平面化，其中选择的处理浆料是氮化硅的最小选择性和相对高选择性的银基导电材料。处理浆料包括研磨剂和氧化剂。以这种方式，移除超过互连孔的最上边界的银基导电材料的部分。

56. 发明授权

US09269586B2 Selective metal deposition over dielectric layers 有权
标题翻译：介电层上的选择性金属沉积
公开(公告)号：US09269586B2
公开(公告)日：2016-02-23
申请号：US13686107
申请日：2012-11-27
申请人： Paul A. Morgan , Nishant Sinha
发明人： Paul A. Morgan , Nishant Sinha
IPC分类号： H01L21/44 , H01L21/283 , H01L21/768
CPC分类号： H01L21/283 , H01L21/76802 , H01L21/76834 , H01L21/76879
摘要： Selective deposition of metal over dielectric layers in a manner that minimizes or eliminates keyhole formation is provided. According to one embodiment, a dielectric target layer is formed over a substrate layer, wherein the target layer may be configured to allow conformal metal deposition, and a dielectric second layer is formed over the target layer, wherein the second layer may be configured to allow bottom-up metal deposition. An opening may then be formed in the second layer and metal may be selectively deposited over substrate layer.
摘要翻译：提供了以最小化或消除钥匙孔形成的方式在电介质层上选择性沉积金属。根据一个实施例，介电目标层形成在衬底层上，其中目标层可以被配置为允许保形金属沉积，并且在目标层上形成介电第二层，其中第二层可以被配置为允许自下而上的金属沉积。然后可以在第二层中形成开口，并且可以在衬底层上选择性地沉积金属。

57. 发明授权

US08664112B2 Methods for forming interconnect structures for integration of multi-layered integrated circuit devices 有权
标题翻译：形成用于集成多层集成电路器件的互连结构的方法
公开(公告)号：US08664112B2
公开(公告)日：2014-03-04
申请号：US13085122
申请日：2011-04-12
申请人： Gurtej S. Sandhu , Nishant Sinha , John A. Smythe
发明人： Gurtej S. Sandhu , Nishant Sinha , John A. Smythe
IPC分类号： H01L23/52
CPC分类号： H01L23/5283 , H01L21/76805 , H01L21/76816 , H01L21/76877 , H01L21/76879 , H01L23/5226 , H01L23/53209 , H01L23/5329 , H01L25/0657 , H01L25/50 , H01L27/105 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. Methods of forming semiconductor devices comprising at least one interconnect structure are also disclosed.
摘要翻译：半导体器件包括至少一个集成电路层，至少一个导电迹线和与至少一个导电迹线的至少一部分相邻的绝缘材料。至少一个互连结构延伸穿过所述至少一个导电迹线的一部分和所述绝缘材料的一部分，所述至少一个互连结构包括穿过所述至少一个导电迹线的横向截面尺寸，所述导电迹线与横向交叉不同通过绝缘材料的尺寸。还公开了形成包括至少一个互连结构的半导体器件的方法。

58. 发明申请

US20140059522A1 Generating Test Cases for Covering Enterprise Rules and Predicates 有权
标题翻译：生成覆盖企业规则和谓词的测试用例
公开(公告)号：US20140059522A1
公开(公告)日：2014-02-27
申请号：US13592754
申请日：2012-08-23
申请人： Satish Chandra , Suresh Thummalapenta , Nishant Sinha , Saurabh Sinha , Anand Vaishampayan , Vasanta K. Lakshmi
发明人： Satish Chandra , Suresh Thummalapenta , Nishant Sinha , Saurabh Sinha , Anand Vaishampayan , Vasanta K. Lakshmi
IPC分类号： G06F9/44
CPC分类号： G06F11/3676 , G06F11/3684
摘要： Techniques, an apparatus and an article of manufacture for generating test cases for covering enterprise rules and predicates. A method includes obtaining a web application and a specification of at least one enterprise rule, constructing a link graph that captures at least one navigation path in the web application, and performing a traversal of the web application guided by the link graph to generate an executable test case that drives the web application along one of the at least one navigation paths in which the at least one enterprise rule is covered to determine the web application's conformance to the at least one enterprise rule, wherein the executable test case is a sequence of one or more test steps, each test step representing an action to be performed on the web application and/or a verification of the application state.
摘要翻译：用于生成覆盖企业规则和谓词的测试用例的技术，设备和制造。一种方法包括获得网络应用程序和至少一个企业规则的规范，构建在web应用程序中捕获至少一个导航路径的链接图，以及执行由链接图引导的web应用程序的遍历以生成可执行文件测试用例，其沿着所述至少一个企业规则被覆盖的所述至少一个导航路径中的一个驱动所述web应用，以确定所述web应用程序对所述至少一个企业规则的一致性，其中所述可执行测试用例是一个或更多的测试步骤，每个测试步骤表示要在web应用上执行的动作和/或应用状态的验证。

59. 发明授权

US08595708B2 Systems and methods for concurrency analysis 有权
标题翻译：并发分析的系统和方法
公开(公告)号：US08595708B2
公开(公告)日：2013-11-26
申请号：US13109998
申请日：2011-05-18
申请人： Nishant Sinha , Chao Wang
发明人： Nishant Sinha , Chao Wang
IPC分类号： G06F11/00 , G06F3/048 , G06F9/44 , G06F9/45 , G06F9/46 , G01N33/50
CPC分类号： G06F11/3608
摘要： Systems and methods are disclosed to check properties of bounded concurrent programs by encoding concurrent control flow graph (CFG) and property for programming threads as a first-order formula F1; initializing an interference abstraction (IA); encoding the IA as a first-order formula F2; checking a conjunction of F1 and F2 (F1^F2); if the conjunction is satisfiable, checking if an interference relation (IR) is spurious, and iteratively refining the IA; and if the conjunction is unsatisfiable, checking if an interference relation (IR) is spurious, and iteratively refining the IA.
摘要翻译：公开了系统和方法，通过将并行控制流程图（CFG）和编程线程的属性编码为一阶公式F1来检查有界并发程序的属性; 初始化干扰抽象（IA）; 将IA编码为一阶公式F2; 检查F1和F2的连接（F1 ^ F2）; 如果连接是可满足的，则检查干扰关系（IR）是否是假的，并且迭代地改进IA; 并且如果连接不能令人满意，则检查干扰关系（IR）是否是伪造的，并且迭代地改进IA。

60. 发明申请

US20120326221A1 MULTI-TIERED SEMICONDUCTOR DEVICES AND ASSOCIATED METHODS 有权
标题翻译：多层半导体器件及相关方法
公开(公告)号：US20120326221A1
公开(公告)日：2012-12-27
申请号：US13165546
申请日：2011-06-21
申请人： Nishant Sinha
发明人： Nishant Sinha
IPC分类号： H01L29/788 , H01L21/28 , H01L21/311
CPC分类号： H01L27/11556 , H01L21/31111 , H01L21/31144 , H01L27/0688 , H01L29/78642 , H01L29/7889
摘要： Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first dielectric is formed, and a second dielectric is formed in contact with the first dielectric. A channel is formed through the first dielectric and the second dielectric with a first etch chemistry, a void is formed in the first dielectric with a second etch chemistry, and a device is formed at least partially in the void in the first dielectric. Additional embodiments are also described.
摘要翻译：描述制造多层半导体器件的方法以及包括它们的装置和系统。在一种这样的方法中，形成第一电介质，并且形成与第一电介质接触的第二电介质。通过第一电介质和第二电介质通过第一蚀刻化学品形成通道，在第一电介质中用第二蚀刻化学物质形成空隙，并且器件至少部分地形成在第一电介质的空隙中。还描述了另外的实施例。

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