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51. 发明申请

US20130119434A1 BIPOLAR TRANSISTOR WITH A COLLECTOR HAVING A PROTECTED OUTER EDGE PORTION FOR REDUCED BASED-COLLECTOR JUNCTION CAPACITANCE AND A METHOD OF FORMING THE TRANSISTOR 有权
标题翻译：具有收纳器的双极晶体管具有用于基于集电极结电容器的保护外边缘部分和形成晶体管的方法
公开(公告)号：US20130119434A1
公开(公告)日：2013-05-16
申请号：US13296496
申请日：2011-11-15
申请人： JAMES W. ADKISSON , David L. Harame , Robert K. Leidy , Qizhi Liu
发明人： JAMES W. ADKISSON , David L. Harame , Robert K. Leidy , Qizhi Liu
IPC分类号： H01L29/737 , H01L29/73 , H01L21/331
CPC分类号： H01L29/732 , H01L29/7371
摘要： Disclosed are embodiments of a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a collector region having a protected upper edge portion for reduced base-collector junction capacitance Cbc. In the embodiments, a collector region is positioned laterally adjacent to a trench isolation region within a substrate. Mask layer(s) cover the trench isolation region and further extend laterally onto the edge portion of the collector region. A first section of an intrinsic base layer is positioned above a center portion of the collector region and a second section of the intrinsic base layer is positioned above the mask layer(s). During processing these mask layer(s) prevent divot formation in the upper corner of the trench isolation region at the isolation region-collector region interface and further limit dopant diffusion from a subsequently formed raised extrinsic base layer into the collector region.
摘要翻译：公开了晶体管（例如双极结型晶体管（BJT）或异质结双极晶体管（HBT））的实施例以及形成具有集电极区域的晶体管的方法，该集电极区域具有用于还原的基极 - 集电极结电容Cbc的受保护的上边缘部分。在实施例中，集电极区域位于衬底内侧向与沟槽隔离区域相邻的位置。掩模层覆盖沟槽隔离区域并且进一步横向延伸到收集器区域的边缘部分上。本征基极层的第一部分位于集电极区域的中心部分的上方，并且本征基极层的第二部分位于掩模层之上。在处理期间，这些掩模层防止在隔离区域 - 集电极区界面处的沟槽隔离区的上角部形成裂缝，并且进一步限制从随后形成的凸起的外在基极层到集电极区域的掺杂剂扩散。

52. 发明授权

US07521327B2 High fT and fmax bipolar transistor and method of making same 失效
标题翻译：高fT和fmax双极晶体管及其制造方法
公开(公告)号：US07521327B2
公开(公告)日：2009-04-21
申请号：US11378927
申请日：2006-03-17
申请人： Alvin Jose Joseph , Qizhi Liu
发明人： Alvin Jose Joseph , Qizhi Liu
IPC分类号： H01L21/331
CPC分类号： H01L29/66287 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/732
摘要： A high fT and fmax bipolar transistor includes an emitter, a base, and a collector. The emitter has a lower portion and an upper portion that extends beyond the lower portion. The base includes an intrinsic base and an extrinsic base. The intrinsic base is located between the lower portion of the emitter and the collector. The extrinsic base extends from the lower portion of the emitter beyond the upper portion of the emitter and includes a continuous conductor that extends from underneath the upper portion of the emitter and out from underneath the upper portion of the emitter. The continuous conductor provides a low electrical resistance path from a base contact (not shown) to the intrinsic base. The transistor may include a second conductor that does not extend underneath the upper portion of the emitter, but which further reduces the electrical resistance through the extrinsic base.
摘要翻译：高fT和fmax双极晶体管包括发射极，基极和集电极。发射器具有延伸超出下部的下部和上部。基础包括内在基础和外在碱基。本征基极位于发射极的下部和集电极之间。外部基极从发射器的下部延伸超过发射器的上部，并且包括从发射器的上部下方延伸并从发射器的上部下方延伸的连续导体。连续导体提供从底部触点（未示出）到本征基极的低电阻路径。晶体管可以包括不延伸在发射极的上部下方的第二导体，但是通过外部基极进一步降低电阻。

53. 发明授权

US07491985B2 Method of collector formation in BiCMOS technology 有权
标题翻译： BiCMOS技术中收集器形成的方法
公开(公告)号：US07491985B2
公开(公告)日：2009-02-17
申请号：US11288843
申请日：2005-11-29
申请人： Peter J. Geiss , Peter B. Gray , Alvin J. Joseph , Qizhi Liu
发明人： Peter J. Geiss , Peter B. Gray , Alvin J. Joseph , Qizhi Liu
IPC分类号： H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/0821 , H01L21/8249 , H01L27/0623 , H01L29/66242 , H01L29/66318
摘要： A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. Specifically, the HBT of the present invention includes a substrate including at least a subcollector; a buried refractory metal silicide layer located on the subcollector; and a shallow trench isolation region located on a surface of the buried refractory metal silicide layer. The present invention also provides a method of fabricating such a HBT. The method includes forming a buried refractory metal silicide underneath the shallow trench isolation region on the subcollector of the device.
摘要翻译：提供了用于高速BiCMOS应用的异步双极晶体管（HBT），其中通过在器件的子集电极上的浅沟槽隔离区域的下面提供掩埋难熔金属硅化物层来降低集电极电阻Rc。具体地，本发明的HBT包括至少包括子集电极的基板; 位于子集电极上的埋置难熔金属硅化物层; 以及位于掩埋难熔金属硅化物层的表面上的浅沟槽隔离区域。本发明还提供一种制造这种HBT的方法。该方法包括在器件的子集电极上的浅沟槽隔离区域的下面形成埋置难熔金属硅化物。

54. 发明申请

US20060177986A1 High fT and fmax bipolar transistor and method of making same 失效
标题翻译：高fT和fmax双极晶体管及其制造方法
公开(公告)号：US20060177986A1
公开(公告)日：2006-08-10
申请号：US11378927
申请日：2006-03-17
申请人： Alvin Joseph , Qizhi Liu
发明人： Alvin Joseph , Qizhi Liu
IPC分类号： H01L21/8222
CPC分类号： H01L29/66287 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/732
摘要： A high fT and fmax bipolar transistor includes an emitter, a base, and a collector. The emitter has a lower portion and an upper portion that extends beyond the lower portion. The base includes an intrinsic base and an extrinsic base. The intrinsic base is located between the lower portion of the emitter and the collector. The extrinsic base extends from the lower portion of the emitter beyond the upper portion of the emitter and includes a continuous conductor that extends from underneath the upper portion of the emitter and out from underneath the upper portion of the emitter. The continuous conductor provides a low electrical resistance path from a base contact (not shown) to the intrinsic base. The transistor may include a second conductor that does not extend underneath the upper portion of the emitter, but which further reduces the electrical resistance through the extrinsic base.
摘要翻译：高电平和高压双极晶体管包括发射极，基极和集电极。发射器具有延伸超出下部的下部和上部。基础包括内在基础和外在碱基。本征基极位于发射极的下部和集电极之间。外部基极从发射器的下部延伸超过发射器的上部，并且包括从发射器的上部下方延伸并从发射器的上部下方延伸的连续导体。连续导体提供从底部触点（未示出）到本征基极的低电阻路径。晶体管可以包括不延伸在发射极的上部下方的第二导体，但是通过外部基极进一步降低电阻。

55. 发明授权

US07060557B1 Fabrication of high-density capacitors for mixed signal/RF circuits 有权
标题翻译：用于混合信号/ RF电路的高密度电容器的制造
公开(公告)号：US07060557B1
公开(公告)日：2006-06-13
申请号：US10190297
申请日：2002-07-05
申请人： Bin Zhao , Qizhi Liu , Maureen R. Brongo
发明人： Bin Zhao , Qizhi Liu , Maureen R. Brongo
IPC分类号： H01L21/8242
CPC分类号： H01L28/91
摘要： A method for fabricating a capacitor on a semiconductor substrate is disclosed. The method may include simultaneously forming at least one via and at least one upper capacitor plate opening in a first dielectric layer having an underlying cap dielectric layer deposited over a first material region having a first conductive material within a conductive region and forming a trench above the via. The underlying cap dielectric layer may be modified in a way that increases its dielectric constant as a result of simultaneously be heated by a heat source and impinged with and energy beam. The method may also include filling the via, trench, and upper capacitor plate opening with a second conductive material resulting in an integrated circuit structure and employing CMP to remove any excess second conductive material from the integrated circuit structure.
摘要翻译：公开了一种在半导体衬底上制造电容器的方法。该方法可以包括同时形成至少一个通孔和至少一个上电容器板开口，该第一电介质层具有沉积在具有导电区域内的第一导电材料的第一材料区域上的底层盖电介质层，并且形成在通过。底层盖电介质层可以以增加其介电常数的方式进行修改，这是由于同时被热源加热并与其碰撞而产生的能量束。该方法还可以包括用第二导电材料填充通孔，沟槽和上电容器板开口，得到集成电路结构，并采用CMP从集成电路结构中去除任何多余的第二导电材料。

56. 发明授权

US07038298B2 High fT and fmax bipolar transistor and method of making same 有权
标题翻译：高fT和fmax双极晶体管及其制造方法
公开(公告)号：US07038298B2
公开(公告)日：2006-05-02
申请号：US10604045
申请日：2003-06-24
申请人： Alvin Jose Joseph , Qizhi Liu
发明人： Alvin Jose Joseph , Qizhi Liu
IPC分类号： H01L27/082
CPC分类号： H01L29/66287 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/732
摘要： A high fT and fmax bipolar transistor (100) includes an emitter (104), a base (120), and a collector (116). The emitter has a lower portion (108) and an upper portion (112) that extends beyond the lower portion. The base includes an intrinsic base (14) and an extrinsic base (144). The intrinsic base is located between the lower portion of the emitter and the collector. The extrinsic base extends from the lower portion of the emitter beyond the upper portion of the emitter and includes a continuous conductor (148) that extends from underneath the upper portion of the emitter and out from underneath the upper portion of the emitter. The continuous conductor provides a low electrical resistance path from a base contact (not shown) to the intrinsic base. The transistor may include a second conductor (152) that does not extend underneath the upper portion of the emitter, but which further reduces the electrical resistance through the extrinsic base.
摘要翻译：高电平和高压双极晶体管（100）包括发射极（104），基极（120）和集电极（116）。发射器具有延伸超出下部的下部（108）和上部（112）。基部包括内在基极（14）和外部基极（144）。本征基极位于发射极的下部和集电极之间。外部基极从发射器的下部延伸超过发射器的上部，并且包括从发射器的上部下方延伸并从发射器的上部下方延伸的连续导体（148）。连续导体提供从底部触点（未示出）到本征基极的低电阻路径。晶体管可以包括第二导体（152），其不延伸在发射极的上部下方，但是通过外部基极进一步减小电阻。

57. 发明申请

US20060081934A1 Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same 失效
标题翻译：双极晶体管具有可选择的自对准的外部基极和其形成方法
公开(公告)号：US20060081934A1
公开(公告)日：2006-04-20
申请号：US11289915
申请日：2005-11-30
申请人： Marwan Khater , James Dunn , David Harame , Alvin Joseph , Qizhi Liu , Francois Pagette , Stephen Onge , Andreas Stricker
发明人： Marwan Khater , James Dunn , David Harame , Alvin Joseph , Qizhi Liu , Francois Pagette , Stephen Onge , Andreas Stricker
IPC分类号： H01L23/62
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.
摘要翻译：公开了一种具有凸起的外在基极和在本征基极和发射极之间可选自对准的双极晶体管。制造方法可以包括在内在基底上形成多晶硅或硅的第一非本征基极层的预定厚度。然后通过在第一非本征基层上的光刻形成电介质着色焊盘。接下来，在电介质贴片垫的顶部上形成第二非多晶硅或硅的非本征基极层，以最终确定凸出的非本征基本总厚度。使用光刻和RIE形成发射器开口，其中第二外部基极层被蚀刻停止在电介质着色焊盘上。通过选择第一非本征基极层厚度，电介质着陆焊盘宽度和间隔物宽度来实现发射极和凸出的外部基极之间的自对准程度。

58. 发明授权

US07002190B1 Method of collector formation in BiCMOS technology 有权
公开(公告)号：US07002190B1
公开(公告)日：2006-02-21
申请号：US10711479
申请日：2004-09-21
申请人： Peter J. Geiss , Peter B. Gray , Alvin J. Joseph , Qizhi Liu
发明人： Peter J. Geiss , Peter B. Gray , Alvin J. Joseph , Qizhi Liu
IPC分类号： H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/0821 , H01L21/8249 , H01L27/0623 , H01L29/66242 , H01L29/66318
摘要： A heterobipolar transistor (HBT) for high-speed BiCMOS applications is provided in which the collector resistance, Rc, is lowered by providing a buried refractory metal silicide layer underneath the shallow trench isolation region on the subcollector of the device. Specifically, the HBT of the present invention includes a substrate including at least a subcollector; a buried refractory metal silicide layer located on the subcollector; and a shallow trench isolation region located on a surface of the buried refractory metal silicide layer. The present invention also provides a method of fabricating such a HBT. The method includes forming a buried refractory metal silicide underneath the shallow trench isolation region on the subcollector of the device.

59. 发明授权

US08916446B2 Bipolar junction transistor with multiple emitter fingers 有权
标题翻译：具有多个发射极指的双极结晶体管
公开(公告)号：US08916446B2
公开(公告)日：2014-12-23
申请号：US13294671
申请日：2011-11-11
申请人： Renata Camillo-Castillo , David L. Harame , Qizhi Liu , Ramana M. Malladi , John J. Pekarik
发明人： Renata Camillo-Castillo , David L. Harame , Qizhi Liu , Ramana M. Malladi , John J. Pekarik
IPC分类号： H01L21/331 , H01L29/08 , H01L29/732 , H01L29/66
CPC分类号： H01L29/66303 , G06F17/5045 , H01L29/0649 , H01L29/0804 , H01L29/0808 , H01L29/0821 , H01L29/1008 , H01L29/66234 , H01L29/7322 , H01L29/735
摘要： Methods for fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. The bipolar junction transistor may include a plurality of emitters that are arranged in distinct emitter fingers. A silicide layer is formed that covers an extrinsic base layer of the bipolar junction transistor and that fills the gaps between adjacent emitters. Non-conductive spacers on the emitter sidewalls electrically insulate the emitters from the silicide layer. The emitters extend through the extrinsic base layer and the silicide layer to contact the intrinsic base layer. The emitters may be formed using sacrificial emitter pedestals in a replacement-type process.
摘要翻译：用于制造双极结型晶体管的方法，双极结型晶体管以及用于双极结型晶体管的设计结构。双极结晶体管可以包括布置在不同的发射极指中的多个发射极。形成了覆盖双极结型晶体管的非本征基极层并填充相邻发射极之间的间隙的硅化物层。发射极侧壁上的非导电间隔物使发射体与硅化物层电绝缘。发射极延伸通过外部基极层和硅化物层与本征基极层接触。发射器可以在替代型工艺中使用牺牲发射器基座形成。

60. 发明申请

US20130277804A1 BIPOLAR JUNCTION TRANSISTORS WITH REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE 审中-公开
标题翻译：具有降低的基极集电极结电容的双极晶体管
公开(公告)号：US20130277804A1
公开(公告)日：2013-10-24
申请号：US13452335
申请日：2012-04-20
申请人： Peng Cheng , David L. Harame , Robert K. Leidy , Qizhi Liu
发明人： Peng Cheng , David L. Harame , Robert K. Leidy , Qizhi Liu
IPC分类号： H01L29/732 , G06F17/50 , H01L21/331
CPC分类号： H01L29/66287 , H01L29/0649 , H01L29/0804 , H01L29/7325
摘要： Methods for fabricating a device structure such as a bipolar junction transistor, device structures for a bipolar junction transistor, and design structures for a bipolar junction transistor. The device structure includes a collector region formed in a substrate, an intrinsic base coextensive with the collector region, an emitter coupled with the intrinsic base, a first isolation region surrounding the collector region, and a second isolation region formed at least partially within the collector region. The first isolation region has a first sidewall and the second isolation region having a second sidewall peripherally inside the first sidewall. A portion of the collector region is disposed between the first sidewall of the first isolation region and the second sidewall of the second isolation region.
摘要翻译：用于制造诸如双极结型晶体管的器件结构的方法，用于双极结型晶体管的器件结构以及用于双极结型晶体管的设计结构。器件结构包括形成在衬底中的集电极区域，与集电极区域共同延伸的本征基极，与本征基极耦合的发射极，围绕集电极区域的第一隔离区域和至少部分地形成在集电极区域内的第二隔离区域地区。第一隔离区域具有第一侧壁，第二隔离区域在第一侧壁周围具有第二侧壁。集电极区域的一部分设置在第一隔离区域的第一侧壁和第二隔离区域的第二侧壁之间。

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