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51. 发明申请

US20090206392A1 Memory device and fabrication method thereof 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20090206392A1
公开(公告)日：2009-08-20
申请号：US12385664
申请日：2009-04-15
申请人： Yoo-Cheol Shin , Jeong-Hyuk Choi , Sung-Hoi Hur
发明人： Yoo-Cheol Shin , Jeong-Hyuk Choi , Sung-Hoi Hur
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573 , Y10S438/954
摘要： A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.
摘要翻译：一种形成存储器件的方法，其中可以在衬底上形成第一绝缘体层和电荷俘获层，并且可以对第一绝缘体层和电荷俘获层中的至少一个进行图案化以形成图案化区域。可以在图案化区域上形成第二绝缘层和导电层，并且可以对导电层，第二绝缘体层，电荷俘获层和第一绝缘体层中的一个或多个进行图案化以形成串选择线，接地选择线，在基板上的串选择线和地选择线之间的多个字线，低压栅电极和多个不同厚度的绝缘体。所形成的存储器件可以是例如具有SONOS栅极结构的NAND型非易失性存储器件。

52. 发明授权

US07285815B2 EEPROM device having selecting transistors and method of fabricating the same 有权
标题翻译：具有选择晶体管的EEPROM器件及其制造方法
公开(公告)号：US07285815B2
公开(公告)日：2007-10-23
申请号：US11336751
申请日：2006-01-20
申请人： Kwang-Shik Shin , Han-Soo Kim , Sung-Hoi Hur
发明人： Kwang-Shik Shin , Han-Soo Kim , Sung-Hoi Hur
IPC分类号： H01L29/76
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521
摘要： An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that extend across the active regions and are interposed between the control gate patterns. A floating gate pattern is formed on intersection regions where the control gate patterns extend across the active regions. A lower gate pattern is formed on intersection regions where the selection gate patterns extend across the active regions. An inter-gate dielectric pattern is disposed between the control gate pattern and the floating gate pattern and a dummy dielectric pattern is disposed between the selection gate pattern and the lower gate pattern. The dummy dielectric pattern is substantially parallel to the selection gate pattern, and self-aligned with one sidewall of the selection gate pattern to overlap a predetermine width of the selection gate pattern.
摘要翻译： EEPROM包括用于限定多个有源区的器件隔离层，跨越有源区延伸的一对控制栅极和跨越有源区延伸并插入在控制栅极图案之间的一对选择栅极图案。浮动栅极图案形成在跨越有源区域的控制栅极图案延伸的交叉区域上。在选择栅极图案跨越有源区域延伸的交叉区域上形成下部栅极图案。栅极间电介质图案设置在控制栅极图案和浮置栅极图案之间，并且虚设电介质图案设置在选择栅极图案和下部栅极图案之间。虚拟介质图案基本上平行于选择栅极图案，并且与选择栅极图案的一个侧壁自对准以重叠选择栅极图案的预定宽度。

53. 发明授权

US07223659B2 Memory device and fabrication method thereof 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US07223659B2
公开(公告)日：2007-05-29
申请号：US11048852
申请日：2005-02-03
申请人： Yoo-Cheol Shin , Jeong-Hyuk Choi , Sung-Hoi Hur
发明人： Yoo-Cheol Shin , Jeong-Hyuk Choi , Sung-Hoi Hur
IPC分类号： H01L21/8247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573 , Y10S438/954
摘要： A method of forming a memory device, where a first insulator layer and a charge trapping layer may be formed on a substrate, and at least one of the first insulator layer and charge trapping layer may be patterned to form patterned areas. A second insulation layer and a conductive layer may be formed on the patterned areas, and one or more of the conductive layer, second insulator layer, charge trapping layer and first insulator layer may be patterned to form a string selection line, ground selection line, a plurality of word lines between the string selection and ground selection lines on the substrate, a low voltage gate electrode, and a plurality of insulators of varying thickness. The formed memory device may be a NAND-type non-volatile memory device having a SONOS gate structure, for example.
摘要翻译：一种形成存储器件的方法，其中可以在衬底上形成第一绝缘体层和电荷俘获层，并且可以对第一绝缘体层和电荷俘获层中的至少一个进行图案化以形成图案化区域。可以在图案化区域上形成第二绝缘层和导电层，并且可以对导电层，第二绝缘体层，电荷俘获层和第一绝缘体层中的一个或多个进行图案化以形成串选择线，接地选择线，在基板上的串选择线和地选择线之间的多个字线，低压栅电极和多个不同厚度的绝缘体。所形成的存储器件可以是例如具有SONOS栅极结构的NAND型非易失性存储器件。

54. 发明申请

US20060120194A1 EEPROM device having selecting transistors and method fabricating the same 有权
标题翻译：具有选择晶体管的EEPROM器件及其制造方法
公开(公告)号：US20060120194A1
公开(公告)日：2006-06-08
申请号：US11336751
申请日：2006-01-20
申请人： Kwang-Shik Shin , Han-Soo Kim , Sung-Hoi Hur
发明人： Kwang-Shik Shin , Han-Soo Kim , Sung-Hoi Hur
IPC分类号： G11C7/00
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521
摘要： An EEPROM includes a device isolation layer for defining a plurality of active regions, a pair of control gates extending across the active regions and a pair of selection gates patterns that extend across the active regions and are interposed between the control gate patterns. A floating gate pattern is formed on intersection regions where the control gate patterns extend across the active regions. A lower gate pattern is formed on intersection regions where the selection gate patterns extend across the active regions. An inter-gate dielectric pattern is disposed between the control gate pattern and the floating gate pattern and a dummy dielectric pattern is disposed between the selection gate pattern and the lower gate pattern. The dummy dielectric pattern is substantially parallel to the selection gate pattern, and self-aligned with one sidewall of the selection gate pattern to overlap a predetermine width of the selection gate pattern.
摘要翻译： EEPROM包括用于限定多个有源区的器件隔离层，跨越有源区延伸的一对控制栅极和跨越有源区延伸并插入在控制栅极图案之间的一对选择栅极图案。浮动栅极图案形成在跨越有源区域的控制栅极图案延伸的交叉区域上。在选择栅极图案跨越有源区域延伸的交叉区域上形成下部栅极图案。栅极间电介质图案设置在控制栅极图案和浮置栅极图案之间，并且虚设电介质图案设置在选择栅极图案和下部栅极图案之间。虚拟介质图案基本上平行于选择栅极图案，并且与选择栅极图案的一个侧壁自对准以重叠选择栅极图案的预定宽度。

55. 发明授权

US06583478B2 Transfer circuit of semiconductor device and structure thereof 有权
公开(公告)号：US06583478B2
公开(公告)日：2003-06-24
申请号：US09948201
申请日：2001-09-06
申请人： Sung-Hoi Hur
发明人： Sung-Hoi Hur
IPC分类号： H01L2976
CPC分类号： H01L27/0629 , H01L21/76895 , H01L27/115 , H01L28/40
摘要： A semiconductor transfer circuit and a structure thereof are provided. The transfer circuit and the structure thereof include a stack gate MOS transistor having first and second gate electrodes that are sequentially stacked and a control MOS transistor connected to the stack gate MOS transistor. A drain of the control MOS transistor is connected to the first gate electrode.

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