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51. 发明申请

US20090173928A1 POLYSILICON EMITTER BJT ACCESS DEVICE FOR PCRAM 有权
标题翻译：用于PCRAM的多晶硅发射器BJT接入装置
公开(公告)号：US20090173928A1
公开(公告)日：2009-07-09
申请号：US11971761
申请日：2008-01-09
申请人： Bipin Rajendran , Tak H. Ning , Chung H. Lam
发明人： Bipin Rajendran , Tak H. Ning , Chung H. Lam
IPC分类号： H01L45/00
CPC分类号： H01L45/148 , H01L27/0623 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A resistive non-volatile memory cell with a bipolar junction transistor (BJT) access device formed in conjunction with the entire memory cell. The memory cell includes a substrate acting as a collector, a semiconductor base layer acting as a base, and a semiconductor emitter layer acting as an emitter. Additionally, metal plugs and the phase change memory element are formed above the BJT access device while the emitter, metal plugs, and phase change memory element are contained within an insulating region. In one embodiment of the invention, a spacer layer is formed and the emitter layer is contained within the protective spacer layer. The spacer layer is contained within the insulating region.
摘要翻译：具有与整个存储单元结合形成的双极结型晶体管（BJT）存取装置的电阻性非易失性存储单元。存储单元包括用作集电极的基板，用作基极的半导体基极层和用作发射极的半导体发射极层。此外，金属插头和相变存储元件形成在BJT存取装置的上方，而发射极，金属插塞和相变存储元件包含在绝缘区域内。在本发明的一个实施例中，形成间隔层，并且发射极层包含在保护间隔层内。间隔层包含在绝缘区域内。

52. 发明申请

US20090073785A1 MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION 有权
标题翻译：多级存储单元利用测量时间延迟作为等级定义的特征参数
公开(公告)号：US20090073785A1
公开(公告)日：2009-03-19
申请号：US11857370
申请日：2007-09-18
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
IPC分类号： G11C7/10
CPC分类号： G11C11/5628 , G11C11/1675 , G11C11/1693 , G11C11/5642 , G11C11/5678 , G11C13/0002 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C16/32 , G11C2013/0076
摘要： A method for operating a memory cell. Memory cells represent binary values by storing a characteristic parameter. The method of memory cell operation entails receiving a binary value to be stored by a memory cell. A determining operation determines a target discharge time corresponding to the binary value. The target discharge time being the time needed to discharge a pre-charged circuit through the said memory cell to a predetermined level. A storing operation stores a characteristic parameter in the memory cell such that an electron discharge time through an electronic circuit formed, at least partially, by the memory cell, is substantially equal to the target discharge time.
摘要翻译：一种操作存储单元的方法。存储单元通过存储特征参数来表示二进制值。存储单元操作的方法需要接收由存储器单元存储的二进制值。确定操作确定对应于二进制值的目标放电时间。目标放电时间是将预充电电路通过所述存储单元放电至预定水平所需的时间。存储操作将特征参数存储在存储单元中，使得通过至少部分地由存储单元形成的电子电路的电子放电时间基本上等于目标放电时间。

53. 发明申请

US20090073784A1 MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION 有权
标题翻译：多级存储单元利用测量时间延迟作为等级定义的特征参数
公开(公告)号：US20090073784A1
公开(公告)日：2009-03-19
申请号：US11857356
申请日：2007-09-18
申请人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung H. Lam , Bipin Rajendran
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C11/565 , G11C11/5628 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C16/32 , G11C2013/0054
摘要： A memory array and computer program product for operating a memory cell and memory array. An embodiment of the invention entails receiving a binary value to be stored by a memory cell. A determining operation determines a target discharge time corresponding to the binary value. The target discharge time being the time needed to discharge a pre-charged circuit through the said memory cell to a predetermined level. A storing operation stores a characteristic parameter in the memory cell such that an electron discharge time through an electronic circuit formed, at least partially, by the memory cell, is substantially equal to the target discharge time.
摘要翻译：用于操作存储器单元和存储器阵列的存储器阵列和计算机程序产品。本发明的实施例需要接收由存储器单元存储的二进制值。确定操作确定对应于二进制值的目标放电时间。目标放电时间是将预充电电路通过所述存储单元放电至预定水平所需的时间。存储操作将特征参数存储在存储单元中，使得通过至少部分地由存储单元形成的电子电路的电子放电时间基本上等于目标放电时间。

54. 发明申请

US20090013146A1 METHOD TO CREATE A UNIFORMLY DISTRIBUTED MULTI-LEVEL CELL (MLC) BITSTREAM FROM A NON-UNIFORM MLC BITSTREAM 失效
标题翻译：从非均质MLC BITSTREAM创建均匀分布的多层细胞（MLC）BITSTREAM的方法
公开(公告)号：US20090013146A1
公开(公告)日：2009-01-08
申请号：US11774539
申请日：2007-07-06
申请人： Chung H. Lam , Bipin Rajendran
发明人： Chung H. Lam , Bipin Rajendran
IPC分类号： G06F12/02 , G06F7/38
CPC分类号： G11C11/56 , G11C11/5628 , G11C16/3418 , G11C29/00
摘要： A method, system, and computer software product for operating a collection of memory cells. Each memory cell in the collection of memory cells is configured to store a binary multi-bit value delimited by characteristic parameter bands. In one embodiment, a transforming unit transforms an original collection of data to a transformed collection of data using a reversible mathematical operator. The original collection of data has binary multi-bit values arbitrarily distributed across the binary multi-bit values assigned to the characteristic parameter bands and the transformed collection of data has binary multi-bit values substantially uniformly distributed across the binary multi-bit values assigned to the characteristic parameter bands.
摘要翻译：一种用于操作存储器单元集合的方法，系统和计算机软件产品。存储器单元集合中的每个存储器单元被配置为存储由特征参数带限定的二进制多位值。在一个实施例中，变换单元使用可逆数学运算符将原始数据集合转换成变换的数据集合。原始数据集合具有任意分配给分配给特征参数带的二进制多位值的二进制多位值，并且变换的数据集合具有基本上均匀分布在分配给二进制多位值的二进制多位值的二进制多位值特征参数带。

55. 发明授权

US08832010B2 Electronic synapses from stochastic binary memory devices 有权
标题翻译：随机二进制存储器件的电子突触
公开(公告)号：US08832010B2
公开(公告)日：2014-09-09
申请号：US13343371
申请日：2012-01-04
申请人： Bipin Rajendran , Mark B. Ritter
发明人： Bipin Rajendran , Mark B. Ritter
IPC分类号： G06N3/04 , G06N3/063
CPC分类号： G06N3/0635 , G06N3/04 , G06N3/049
摘要： According to a technique, an electronic device is configured to correspond to characteristic features of a biological synapse. The electronic device includes multiple bipolar resistors arranged in parallel to form an electronic synapse, an axonal connection connected to one end of the electronic synapse and to a first electronic neuron, and a dendritic connection connected to another end of the electronic synapse and to a second electronic neuron. An increase and decrease of synaptic conduction in the electronic synapse is based on a probability of switching the plurality of bipolar resistors between a low resistance state and a high resistance state.
摘要翻译：根据技术，电子设备被配置为对应于生物突触的特征。电子装置包括平行布置的多个双极性电阻器以形成电子突触，连接到电子突触的一端和第一电子神经元的轴突连接，以及连接到电子突触的另一端的树突状连接和第二电子神经元。电子突触中突触传导的增加和减少是基于在低电阻状态和高电阻状态之间切换多个双极性电阻器的概率。

56. 发明授权

US08824218B2 Compact low-power asynchronous resistor-based memory read operation and circuit 有权
标题翻译：紧凑型低功耗基于异步电阻的存储器读操作和电路
公开(公告)号：US08824218B2
公开(公告)日：2014-09-02
申请号：US13552932
申请日：2012-07-19
申请人： Seongwon Kim , Yong Liu , Bipin Rajendran
发明人： Seongwon Kim , Yong Liu , Bipin Rajendran
IPC分类号： G11C7/06
CPC分类号： G11C13/004 , G11C7/067 , G11C11/5678 , G11C13/0004
摘要： A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states.
摘要翻译：紧凑型低功率异步电阻器存储器读取电路包括具有多个连续存储器状态的存储单元，每个所述状态对应于相应的输出电压。读出放大器读取存储单元的状态。感测放大器包括分压器，其被配置为接收存储器单元的输出电压并且输出稳定电压，放大器具有在与所述连续存储器状态中的两个相关联的稳定电压之间的电压阈值，其被配置为区分所述两个连续存储器状态。

57. 发明授权

US08559217B2 Phase change material cell with stress inducer liner 有权
标题翻译：相变材料电池与应力诱导衬管
公开(公告)号：US08559217B2
公开(公告)日：2013-10-15
申请号：US12964980
申请日：2010-12-10
申请人： Catherine A. Dubourdieu , Martin M. Frank , Bipin Rajendran , Alejandro G. Schrott
发明人： Catherine A. Dubourdieu , Martin M. Frank , Bipin Rajendran , Alejandro G. Schrott
IPC分类号： G11C11/00
CPC分类号： H01L45/1608 , G11C11/22 , G11C13/0004 , G11C13/0069 , G11C2013/0095 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/143 , H01L45/144
摘要： An example embodiment disclosed is a phase change memory cell. The memory cell includes a phase change material and a transducer positioned proximate the phase change material. The phase change material is switchable between at least an amorphous state and a crystalline state. The transducer is configured to activate when the phase change material is changed from the amorphous state to the crystalline state. In a particular embodiment, the transducer is ferroelectric material.
摘要翻译：所公开的示例实施例是相变存储单元。存储单元包括相变材料和位于相变材料附近的换能器。相变材料可在至少非晶状态和结晶状态之间切换。换能器被配置为当相变材料从非晶状态转变为结晶状态时激活。在特定实施例中，换能器是铁电材料。

58. 发明授权

US08527438B2 Producing spike-timing dependent plasticity in an ultra-dense synapse cross-bar array 有权
标题翻译：在超密集突触交叉阵列中产生尖峰时序依赖性可塑性
公开(公告)号：US08527438B2
公开(公告)日：2013-09-03
申请号：US12645479
申请日：2009-12-22
申请人： Bryan Lawrence Jackson , Dharmendra Shantilal Modha , Bipin Rajendran
发明人： Bryan Lawrence Jackson , Dharmendra Shantilal Modha , Bipin Rajendran
IPC分类号： G06E1/00 , G06E3/00 , G06F15/18 , G06G7/00
CPC分类号： G06N3/049 , G06N3/0635
摘要： Embodiments of the invention relate to producing spike-timing dependent plasticity in an ultra-dense synapse cross-bar array for neuromorphic systems. An aspect of the invention includes when an electronic neuron spikes, an alert pulse is sent from the spiking electronic neuron to each electronic neuron connected to the spiking electronic neuron. When the spiking electronic neuron sends the alert pulse, a gate pulse is sent from the spiking electronic neuron to each electronic neuron connected to the spiking electronic neuron. When each electronic neuron receives the alert pulse, a response pulse is sent from each electronic neuron receiving the alert pulse to the spiking electronic neuron. The response pulse is a function of time since a last spiking of the electronic neuron receiving the alert pulse. In addition, the combination of the gate pulse and response pulse is capable increasing or decreasing conductance of a variable state resistor.
摘要翻译：本发明的实施方案涉及在用于神经形态系统的超密集突触交叉阵列中产生尖峰时间依赖性可塑性。本发明的一个方面包括当电子神经元尖峰时，警报脉冲从尖峰电子神经元发送到连接到尖峰电子神经元的每个电子神经元。当尖峰电子神经元发出警报脉冲时，门脉冲从尖峰电子神经元发送到连接到尖峰电子神经元的每个电子神经元。当每个电子神经元接收到警报脉冲时，从接收警报脉冲的每个电子神经元发送响应脉冲到尖峰电子神经元。响应脉冲是从接收警报脉冲的电子神经元的最后一次尖峰起的时间的函数。此外，门脉冲和响应脉冲的组合能够增加或降低可变状态电阻器的电导。

59. 发明申请

US20120259804A1 RECONFIGURABLE AND CUSTOMIZABLE GENERAL-PURPOSE CIRCUITS FOR NEURAL NETWORKS 有权
公开(公告)号：US20120259804A1
公开(公告)日：2012-10-11
申请号：US13083414
申请日：2011-04-08
申请人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
发明人： Bernard V. Brezzo , Leland Chang , Steven K. Esser , Daniel J. Friedman , Yong Liu , Dharmendra S. Modha , Robert K. Montoye , Bipin Rajendran , Jae-sun Seo , Jose A. Tierno
IPC分类号： G06N3/04 , G06N3/08
CPC分类号： G06N3/063 , G06N3/04 , G06N3/049 , G06N3/082
摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

60. 发明申请

US20110119215A1 HARDWARE ANALOG-DIGITAL NEURAL NETWORKS 有权
标题翻译：硬件模拟数字神经网络
公开(公告)号：US20110119215A1
公开(公告)日：2011-05-19
申请号：US12618101
申请日：2009-11-13
申请人： Bruce G. Elmegreen , Ralph Linsker , Dennis M. Newns , Bipin Rajendran
发明人： Bruce G. Elmegreen , Ralph Linsker , Dennis M. Newns , Bipin Rajendran
IPC分类号： G06N3/06
CPC分类号： G06N3/0635 , G06N3/063
摘要： An analog-digital crosspoint-network includes a plurality of rows and columns, a plurality of synaptic nodes, each synaptic node of the plurality of synaptic nodes disposed at an intersection of a row and column of the plurality of rows and columns, wherein each synaptic node of the plurality of synaptic nodes includes a weight associated therewith, a column controller associated with each column of the plurality of columns, wherein each column controller is disposed to enable a weight change at a synaptic node in communication with said column controller, and a row controller associated with each row of the plurality of rows, wherein each row controller is disposed to control a weight change at a synaptic node in communication with said row controller.
摘要翻译：模拟数字交叉点网络包括多个行和列，多个突触节点，多个突触节点中的每个突触节点设置在多个行和列的行和列的交点处，其中每个突触所述多个突触节点的节点包括与其相关联的权重，与所述多个列中的每列相关联的列控制器，其中每个列控制器被设置为使能与所述列控制器通信的突触节点处的权重变化，以及与多个行的每一行相关联的行控制器，其中每个行控制器被设置为控制与所述行控制器通信的突触节点处的权重变化。

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