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51. 发明授权

US07917731B2 Method and apparatus for prefetching non-sequential instruction addresses 有权
标题翻译：用于预取非顺序指令地址的方法和装置
公开(公告)号：US07917731B2
公开(公告)日：2011-03-29
申请号：US11461883
申请日：2006-08-02
申请人： Brian Michael Stempel , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Brian Michael Stempel , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F9/32
CPC分类号： G06F9/3804 , G06F9/3806
摘要： A processor performs a prefetch operation on non-sequential instruction addresses. If a first instruction address misses in an instruction cache and accesses a higher-order memory as part of a fetch operation, and a branch instruction associated with the first instruction address or an address following the first instruction address is detected and predicted taken, a prefetch operation is performed using a predicted branch target address, during the higher-order memory access. If the predicted branch target address hits in the instruction cache during the prefetch operation, associated instructions are not retrieved, to conserve power. If the predicted branch target address misses in the instruction cache during the prefetch operation, a higher-order memory access may be launched, using the predicted branch instruction address. In either case, the first instruction address is re-loaded into the fetch stage pipeline to await the return of instructions from its higher-order memory access.
摘要翻译：处理器对非顺序指令地址执行预取操作。如果第一指令地址在指令高速缓存中丢失并且作为获取操作的一部分访问高阶存储器，并且检测并预测与第一指令地址或第一指令地址之后的地址相关联的分支指令，则预取在高级存储器访问期间使用预测的分支目标地址执行操作。如果预取分支目标地址在预取操作期间在指令高速缓存中命中，则不检索相关联的指令以节省功率。如果在预取操作期间预测的分支目标地址在指令高速缓存中丢失，则可以使用预测的分支指令地址来启动高阶存储器访问。在任一种情况下，第一指令地址被重新加载到提取级流水线中以等待指令从其高阶存储器访问返回。

52. 发明申请

US20080229069A1 System, Method And Software To Preload Instructions From An Instruction Set Other Than One Currently Executing 有权
标题翻译：系统，方法和软件可以从目前正在执行的指令集预加载指令
公开(公告)号：US20080229069A1
公开(公告)日：2008-09-18
申请号：US11685850
申请日：2007-03-14
申请人： Thomas Andrew Sartorius , Brian Michael Stempel , Rodney Wayne Smith
发明人： Thomas Andrew Sartorius , Brian Michael Stempel , Rodney Wayne Smith
IPC分类号： G06F9/44 , G06F9/30
CPC分类号： G06F9/30196 , G06F9/30047 , G06F9/30189 , G06F9/3802 , G06F9/382
摘要： An instruction preload instruction executed in a first processor instruction set operating mode is operative to correctly preload instructions in a different, second instruction set. The instructions are pre-decoded according to the second instruction set encoding in response to an instruction set preload indicator (ISPI). In various embodiments, the ISPI may be set prior to executing the preload instruction, or may comprise part of the preload instruction or the preload target address.
摘要翻译：在第一处理器指令集操作模式中执行的指令预加载指令可操作以在不同的第二指令集中正确地预加载指令。根据指令集预加载指示符（ISPI），根据第二指令集编码对指令进行预解码。在各种实施例中，可以在执行预加载指令之前设置ISPI，或者可以包括预加载指令或预加载目标地址的一部分。

53. 发明授权

US07711927B2 System, method and software to preload instructions from an instruction set other than one currently executing 有权
标题翻译：系统，方法和软件，用于从除当前执行的指令集之外的指令集预加载指令
公开(公告)号：US07711927B2
公开(公告)日：2010-05-04
申请号：US11685850
申请日：2007-03-14
申请人： Thomas Andrew Sartorius , Brian Michael Stempel , Rodney Wayne Smith
发明人： Thomas Andrew Sartorius , Brian Michael Stempel , Rodney Wayne Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/30196 , G06F9/30047 , G06F9/30189 , G06F9/3802 , G06F9/382
摘要： An instruction preload instruction executed in a first processor instruction set operating mode is operative to correctly preload instructions in a different, second instruction set. The instructions are pre-decoded according to the second instruction set encoding in response to an instruction set preload indicator (ISPI). In various embodiments, the ISPI may be set prior to executing the preload instruction, or may comprise part of the preload instruction or the preload target address.
摘要翻译：在第一处理器指令集操作模式中执行的指令预加载指令可操作以在不同的第二指令集中正确地预加载指令。根据指令集预加载指示符（ISPI），根据第二指令集编码对指令进行预解码。在各种实施例中，可以在执行预加载指令之前设置ISPI，或者可以包括预加载指令或预加载目标地址的一部分。

54. 发明申请

US20080250229A1 System, Method and Software to Preload Instructions from a Variable-Length Instruction Set with Proper Pre-Decoding 有权
标题翻译：用适当的预解码从可变长度指令集预加载指令的系统，方法和软件
公开(公告)号：US20080250229A1
公开(公告)日：2008-10-09
申请号：US11696508
申请日：2007-04-04
申请人： Brian Michael Stempel , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Brian Michael Stempel , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/30047 , G06F9/30152 , G06F9/3802 , G06F9/382
摘要： In a processor executing instructions from a variable-length instruction set, a preload instruction is operative to retrieve from memory a data block corresponding to an instruction cache line, pre-decode instructions from a variable-length instruction set in the data block, and load the instructions and pre-decode information into the instruction cache. An instruction execution unit indicates to a pre-decoder the position within the data block of a first valid instruction. The pre-decoder successively determines the length of each instruction and hence the instruction boundaries. An instruction cache line offset indicator that identifies the position of the first valid instruction may be generated and provided to the pre-decoder in a variety of ways.
摘要翻译：在执行来自可变长度指令集的指令的处理器中，预加载指令用于从存储器检索与指令高速缓存行相对应的数据块，对来自数据块中的可变长度指令集的指令进行预解码，以及负载指令和预解码信息到指令缓存中。指令执行单元向预解码器指示第一有效指令的数据块内的位置。预解码器依次确定每个指令的长度，从而确定指令边界。可以以各种方式生成识别第一有效指令的位置的指令高速缓存行偏移指示符并将其提供给预解码器。

55. 发明申请

US20080040587A1 Debug Circuit Comparing Processor Instruction Set Operating Mode 有权
标题翻译：比较处理器指令集操作模式的调试电路
公开(公告)号：US20080040587A1
公开(公告)日：2008-02-14
申请号：US11463379
申请日：2006-08-09
申请人： Kevin Charles Burke , Brian Michael Stempel , Daren Streett , Kevin Allen Sapp , Leslie Mark DeBruyne , Nabil Amir Rizk , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Kevin Charles Burke , Brian Michael Stempel , Daren Streett , Kevin Allen Sapp , Leslie Mark DeBruyne , Nabil Amir Rizk , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F9/44
CPC分类号： G06F11/3648
摘要： A processor is operative to execute two or more instruction sets, each in a different instruction set operating mode. As each instruction is executed, debug circuit comparison the current instruction set operating mode to a target instruction set operating mode sent by a programmer, and outputs an alert or indication in they match. The alert or indication may additionally be dependent upon the instruction address following within a predetermined target address range. The alert or indication may comprise a breakpoint signal that halts execution and/or it is output as an external signal of the processor. The instruction address at which the processor detects a match in the instruction set operating modes may additionally be output. Additionally or alternatively, the alert or indication may comprise starting or stopping a trace operation, causing an exception, or any other known debugger function.
摘要翻译：处理器可操作以执行两个或更多个指令集，每个指令集处于不同的指令集操作模式。当执行每条指令时，调试电路将当前指令集操作模式与编程器发送的目标指令集操作模式进行比较，并输出其中的警报或指示。警报或指示还可以依赖于在预定目标地址范围内的指令地址。警报或指示可以包括停止执行的断点信号和/或作为处理器的外部信号输出的断点信号。可以另外输出处理器在指令集操作模式中检测到匹配的指令地址。附加地或替代地，警报或指示可以包括启动或停止跟踪操作，引起异常或任何其他已知的调试器功能。

56. 发明申请

US20080034187A1 Method and Apparatus for Prefetching Non-Sequential Instruction Addresses 有权
标题翻译：用于预取非顺序指令地址的方法和装置
公开(公告)号：US20080034187A1
公开(公告)日：2008-02-07
申请号：US11461883
申请日：2006-08-02
申请人： Brian Michael Stempel , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Brian Michael Stempel , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F12/00
CPC分类号： G06F9/3804 , G06F9/3806
摘要： A processor performs a prefetch operation on non-sequential instruction addresses. If a first instruction address misses in an instruction cache and accesses a higher-order memory as part of a fetch operation, and a branch instruction associated with the first instruction address or an address following the first instruction address is detected and predicted taken, a prefetch operation is performed using a predicted branch target address, during the higher-order memory access. If the predicted branch target address hits in the instruction cache during the prefetch operation, associated instructions are not retrieved, to conserve power. If the predicted branch target address misses in the instruction cache during the prefetch operation, a higher-order memory access may be launched, using the predicted branch instruction address. In either case, the first instruction address is re-loaded into the fetch stage pipeline to await the return of instructions from its higher-order memory access.
摘要翻译：处理器对非顺序指令地址执行预取操作。如果第一指令地址在指令高速缓存中丢失并且作为获取操作的一部分访问高阶存储器，并且检测并预测与第一指令地址或第一指令地址之后的地址相关联的分支指令，则预取在高级存储器访问期间使用预测的分支目标地址执行操作。如果预取分支目标地址在预取操作期间在指令高速缓存中命中，则不检索相关联的指令以节省功率。如果在预取操作期间预测的分支目标地址在指令高速缓存中丢失，则可以使用预测的分支指令地址来启动高阶存储器访问。在任一种情况下，第一指令地址被重新加载到提取级流水线中以等待指令从其高阶存储器访问返回。

57. 发明授权

US08352713B2 Debug circuit comparing processor instruction set operating mode 有权
标题翻译：调试电路比较处理器指令集的工作模式
公开(公告)号：US08352713B2
公开(公告)日：2013-01-08
申请号：US11463379
申请日：2006-08-09
申请人： Kevin Charles Burke , Brian Michael Stempel , Daren Streett , Kevin Allen Sapp , Leslie Mark DeBruyne , Nabil Amir Rizk , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Kevin Charles Burke , Brian Michael Stempel , Daren Streett , Kevin Allen Sapp , Leslie Mark DeBruyne , Nabil Amir Rizk , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F9/48
CPC分类号： G06F11/3648
摘要： A processor is operative to execute two or more instruction sets, each in a different instruction set operating mode. As each instruction is executed, debug circuit comparison the current instruction set operating mode to a target instruction set operating mode sent by a programmer, and outputs an alert or indication in they match. The alert or indication may additionally be dependent upon the instruction address following within a predetermined target address range. The alert or indication may comprise a breakpoint signal that halts execution and/or it is output as an external signal of the processor. The instruction address at which the processor detects a match in the instruction set operating modes may additionally be output. Additionally or alternatively, the alert or indication may comprise starting or stopping a trace operation, causing an exception, or any other known debugger function.
摘要翻译：处理器可操作以执行两个或更多个指令集，每个指令集处于不同的指令集操作模式。当执行每条指令时，调试电路将当前指令集操作模式与编程器发送的目标指令集操作模式进行比较，并输出其中的警报或指示。警报或指示还可以依赖于在预定目标地址范围内的指令地址。警报或指示可以包括停止执行的断点信号和/或作为处理器的外部信号输出的断点信号。可以另外输出处理器在指令集操作模式中检测到匹配的指令地址。附加地或替代地，警报或指示可以包括启动或停止跟踪操作，引起异常或任何其他已知的调试器功能。

58. 发明授权

US08145883B2 Preloading instructions from an instruction set other than a currently executing instruction set 有权
标题翻译：从当前执行的指令集以外的指令集预加载指令
公开(公告)号：US08145883B2
公开(公告)日：2012-03-27
申请号：US12722962
申请日：2010-03-12
申请人： Thomas Andrew Sartorius , Brian Michael Stempel , Rodney Wayne Smith
发明人： Thomas Andrew Sartorius , Brian Michael Stempel , Rodney Wayne Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/30196 , G06F9/30047 , G06F9/30189 , G06F9/3802 , G06F9/382
摘要： A preload instruction in a first instruction set is executed at a processor. The preload instruction causes the processor to preload one or more instructions into an instruction cache. The pre-loaded instructions are pre-decoded according to a second instruction set that is different from the first instruction set. The preloaded instructions are pre-decoded according to the second instruction set in response to an instruction set preload indicator (ISPI).
摘要翻译：在处理器中执行第一指令集中的预加载指令。预加载指令使处理器将一个或多个指令预加载到指令高速缓存中。预加载指令根据与第一指令集不同的第二指令集进行预解码。响应于指令集预加载指示符（ISPI），预加载指令根据第二指令集进行预解码。

59. 发明申请

US20070250666A1 Virtually-Tagged Instruction Cache with Physically-Tagged Behavior 有权
标题翻译：具有物理标记行为的几何标记指令缓存
公开(公告)号：US20070250666A1
公开(公告)日：2007-10-25
申请号：US11468850
申请日：2006-08-31
申请人： Thomas Andrew Sartorius , Rodney Wayne Smith , Daren Eugene Streett
发明人： Thomas Andrew Sartorius , Rodney Wayne Smith , Daren Eugene Streett
IPC分类号： G06F12/00
CPC分类号： G06F12/1063 , G06F12/0891 , G06F2212/1056 , G06F2212/683
摘要： An instruction cache system having a virtually tagged instruction cache which, from a software program perspective, operates as if it were a physically tagged instruction cache is disclosed. The instruction cache system also includes a means for address translation which is responsive to an address translation invalidate instruction and a control logic circuit. The control logic circuit is configured to invalidate an entry in the virtually tagged instruction cache in response to the address translation invalidate instruction.
摘要翻译：一种具有虚拟标记的指令高速缓存的指令高速缓存系统，其从软件程序的角度来看，如同它是物理标记的指令高速缓存一样被操作。指令高速缓存系统还包括响应于地址转换无效指令和控制逻辑电路的地址转换装置。控制逻辑电路被配置为响应于地址转换无效指令使虚拟标记的指令高速缓存中的条目无效。

60. 发明授权

US07802055B2 Virtually-tagged instruction cache with physically-tagged behavior 有权
标题翻译：具有物理标记行为的虚拟标记指令高速缓存
公开(公告)号：US07802055B2
公开(公告)日：2010-09-21
申请号：US11468850
申请日：2006-08-31
申请人： Thomas Andrew Sartorius , Rodney Wayne Smith , Daren Eugene Streett
发明人： Thomas Andrew Sartorius , Rodney Wayne Smith , Daren Eugene Streett
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/1063 , G06F12/0891 , G06F2212/1056 , G06F2212/683
摘要： An instruction cache system having a virtually tagged instruction cache which, from a software program perspective, operates as if it were a physically tagged instruction cache is disclosed. The instruction cache system also includes a means for address translation which is responsive to an address translation invalidate instruction and a control logic circuit. The control logic circuit is configured to invalidate an entry in the virtually tagged instruction cache in response to the address translation invalidate instruction.
摘要翻译：一种具有虚拟标记的指令高速缓存的指令高速缓存系统，其从软件程序的角度来看，如同它是物理标记的指令高速缓存一样被操作。指令高速缓存系统还包括响应于地址转换无效指令和控制逻辑电路的地址转换装置。控制逻辑电路被配置为响应于地址转换无效指令使虚拟标记的指令高速缓存中的条目无效。

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