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51. 发明申请

US20080263415A1 Integrated Circuit, Memory Module, Method of Operating an Integrated Circuit, Method of Fabricating an Integrated Circuit, Computer Program Product, and Computing System 审中-公开
标题翻译：集成电路，存储器模块，集成电路的操作方法，制造集成电路的方法，计算机程序产品和计算系统
公开(公告)号：US20080263415A1
公开(公告)日：2008-10-23
申请号：US11736382
申请日：2007-04-17
申请人： Bernhard Ruf , Michael Kund , Heinz Hoenigschmid
发明人： Bernhard Ruf , Michael Kund , Heinz Hoenigschmid
IPC分类号： G11C29/00
CPC分类号： G11C13/0011 , B82Y10/00 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0033 , G11C29/1201 , G11C29/48 , G11C29/50 , G11C2029/1206 , G11C2029/5602 , G11C2213/31 , G11C2213/71 , G11C2213/79
摘要： According to one embodiment of the present invention, an integrated circuit includes a plurality of memory cells, the integrated circuit being operable in a memory cell testing mode in which testing signals are applied to the memory cells, wherein the strengths and durations of the testing signals at least partly differ from the strengths and durations of programming signals or sensing signals used for programming and sensing memory states of the memory cells.
摘要翻译：根据本发明的一个实施例，集成电路包括多个存储器单元，该集成电路可以以将测试信号施加到存储单元的存储单元测试模式操作，其中测试信号的强度和持续时间至少部分不同于编程信号或用于编程和感测存储器单元的存储器状态的感测信号的强度和持续时间。

52. 发明申请

US20080224178A1 RESISTIVE MEMORY AND METHOD 有权
标题翻译：电阻记忆和方法
公开(公告)号：US20080224178A1
公开(公告)日：2008-09-18
申请号：US11687365
申请日：2007-03-16
申请人： Christian Pacha , Tim Schonauer , Michael Kund
发明人： Christian Pacha , Tim Schonauer , Michael Kund
IPC分类号： H01L27/10 , G11C11/00
CPC分类号： G11C13/0011 , G11C13/0004 , G11C13/0007 , G11C2213/32 , H01L27/2436 , H01L29/785 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1273 , H01L45/145
摘要： A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.
摘要翻译：存储器件包括具有接触区域的翅片的多栅极场效应晶体管（MuGFET）。可编程存储元件邻接鳍片接触区域。

53. 发明授权

US07372716B2 Memory having CBRAM memory cells and method 有权
标题翻译：具有CBRAM存储单元和方法的内存
公开(公告)号：US07372716B2
公开(公告)日：2008-05-13
申请号：US11209424
申请日：2005-08-23
申请人： Thomas Roehr , Ralf Symanczyk , Michael Kund
发明人： Thomas Roehr , Ralf Symanczyk , Michael Kund
IPC分类号： G11C17/00
CPC分类号： G11C13/0011 , G11C13/0069 , G11C2013/0078
摘要： A memory cell arrangement has a plurality of memory cells of the CBRAM type and a programming apparatus, the memory cells being arranged along bit lines and each bit line having a programming apparatus. The invention provides for the programming apparatus to comprise a charge storage device and a switchable charging apparatus. The inventive method for programming memory cells of the CBRAM type is carried out in such a manner that, a given quantity of an electrical charge is stored in a charge storage device, and the stored quantity of electrical charge is transferred to the memory cell to be programmed.
摘要翻译：存储单元布置具有多个CBRAM类型的存储单元和编程设备，存储器单元沿着位线布置，并且每个位线具有编程设备。本发明提供了编程装置，其包括电荷存储装置和可切换充电装置。用于编写CBRAM类型的存储单元的本发明方法是以一定量的方式进行的，即将一定数量的电荷存储在电荷存储装置中，并将存储的电荷量传送到存储单元以成为程序。

54. 发明申请

US20080080109A1 Electric device protection circuit and method for protecting an electric device 失效
标题翻译：电气设备保护电路及其保护方法
公开(公告)号：US20080080109A1
公开(公告)日：2008-04-03
申请号：US11541402
申请日：2006-09-29
申请人： Alexander Duch , Ulrich Klostermann , Michael Kund
发明人： Alexander Duch , Ulrich Klostermann , Michael Kund
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , G11C13/0011 , G11C13/0038 , G11C13/0059 , H02H9/02
摘要： An electric device protection circuit comprises at least one conductive bridging unit which electrically connects a terminal of the electric device to a protection node set to a protection potential, the protection potential being chosen such that the conductive bridging unit switches from a resistive state to a conductive state in case that the voltage or current at the terminal exceeds a predetermined threshold value.
摘要翻译：电气设备保护电路包括至少一个导电桥接单元，其将电气设备的端子与设置为保护电位的保护节点电连接，所述保护电位被选择为使得导电桥接单元从电阻状态切换到导电在端子处的电压或电流超过预定阈值的情况下状态。

55. 发明申请

US20080049531A1 Memory arrangement and method for operating such a memory arrangement 审中-公开
标题翻译：用于操作这种存储器布置的存储器布置和方法
公开(公告)号：US20080049531A1
公开(公告)日：2008-02-28
申请号：US10577881
申请日：2004-10-27
申请人： Michael Kund
发明人： Michael Kund
IPC分类号： G11C7/00
CPC分类号： G11C16/3431 , G11C7/24 , G11C11/406 , G11C16/3418
摘要： A memory arrangement and method of operating a memory arrangement is disclosed. In one embodiment of the memory arrangement according to the invention, rewritable memory cells are arranged at crossovers between word lines and bit lines, said memory cells being configured in such a manner that the information stored in them is essentially read out in a nondestructive manner. According to the invention, the memory arrangement has a flag cell either for each word line or for each bit line, said flag cell being able to store an item of information that indicates whether at least one of the memory cells either along the respective word line or along the respective bit line has been subjected to a reading operation since a basic state occurred.
摘要翻译：公开了一种操作存储装置的存储装置和方法。在根据本发明的存储器装置的一个实施例中，可重写存储器单元被布置在字线和位线之间的交叉处，所述存储器单元被配置为使得存储在其中的信息基本上以非破坏性方式读出。根据本发明，存储器装置对于每个字线或对于每个位线具有标志单元，所述标志单元能够存储指示存储器单元中的至少一个沿着相应字线的信息项或者沿着相应的位线已经进行了基本状态的读取操作。

56. 发明授权

US07337282B2 Memory system and process for controlling a memory component to achieve different kinds of memory characteristics on one and the same memory component 有权
标题翻译：用于控制存储器组件以在同一存储器组件上实现不同种类的存储器特性的存储器系统和过程
公开(公告)号：US07337282B2
公开(公告)日：2008-02-26
申请号：US10722576
申请日：2003-11-28
申请人： Thomas D. Happ , Michael Kund , Ralf Symanczyk
发明人： Thomas D. Happ , Michael Kund , Ralf Symanczyk
IPC分类号： G06F12/00
CPC分类号： G06F13/1694 , G11C7/1045 , G11C11/005 , G11C14/00
摘要： According to the invention, a memory system, and a process for controlling a memory component, to achieve different kinds of memory characteristics on one and the same memory component, is provided, the process comprising the steps: Sending out a signal to select one of several possible modes for the memory component; and Operating the memory component in accordance with the specific mode selected by the signal.
摘要翻译：根据本发明，提供了存储器系统和用于控制存储器组件以在同一存储器组件上实现不同种类的存储器特性的过程，该过程包括以下步骤：发送信号以选择存储器组件的几种可能的模式; 并根据信号选择的特定模式操作存储器组件。

57. 发明申请

US20070276623A1 Semiconductor Component Test Process and a System for Testing Semiconductor Components 审中-公开
标题翻译：半导体元件测试过程和半导体元件测试系统
公开(公告)号：US20070276623A1
公开(公告)日：2007-11-29
申请号：US11835033
申请日：2007-08-07
申请人： Michael Kund , Georg Mueller
发明人： Michael Kund , Georg Mueller
IPC分类号： G01R31/00
CPC分类号： G11C29/56016 , G01R31/3167 , G11C29/56
摘要： A test system can be used for testing semiconductor components, with which several different semiconductor component tests can be performed in succession. A test apparatus receives a test result for a first test and a test result for a second test and evaluates whether the test results from the first and second tests are mutually correlated by evaluating whether the test results comprises a pattern determined during a training phase of the system. The test apparatus then determines whether or not the pattern indicates that a further test is to be dispensed with.
摘要翻译：测试系统可用于测试半导体组件，可以连续执行几个不同的半导体组件测试。测试装置接收用于第一测试的测试结果和用于第二测试的测试结果，并且通过评估测试结果是否包括在训练阶段期间确定的模式来评估来自第一和第二测试的测试结果是否相互相关系统。然后，测试设备确定该图案是否指示将要省略进一步的测试。

58. 发明申请

US20070211515A1 Resistive Memory Arrangement 有权
标题翻译：电阻记忆布置
公开(公告)号：US20070211515A1
公开(公告)日：2007-09-13
申请号：US11688556
申请日：2007-03-20
申请人： Corvin Liaw , Thomas Roehr , Michael Kund
发明人： Corvin Liaw , Thomas Roehr , Michael Kund
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0011 , G11C2213/78 , G11C2213/79
摘要： Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular, and also to a writing, reading and erasing method for a resistive memory arrangement realized with CBRAM resistance elements.
摘要翻译：提供了具有以行和列构成的单元阵列并且具有连接到用于驱动的驱动元件的电阻性存储单元的电阻式存储器装置。每个驱动元件共同连接到形成存储单元的n个单元电阻器，单元电阻器是CBRAM电阻元件，特别是与CBRAM电阻元件实现的用于电阻存储器布置的写入，读取和擦除方法。

59. 发明申请

US20070002618A1 MEMORY ELEMENT, MEMORY READ-OUT ELEMENT AND MEMORY CELL 失效
标题翻译：存储器元件，存储器读出元件和存储器单元
公开(公告)号：US20070002618A1
公开(公告)日：2007-01-04
申请号：US11427337
申请日：2006-06-28
申请人： TIM SCHOENAUER , Michael Kund , Thomas Niedermeier , Joerg Berthold
发明人： TIM SCHOENAUER , Michael Kund , Thomas Niedermeier , Joerg Berthold
IPC分类号： G11C11/34
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0071 , G11C2213/74
摘要： A memory element comprises a resistance element having a first resistance value in a first state and a second resistance value in a second state, it being possible to convert the resistance element from the first state into the second state and from the second state into the first state and the first resistance value and the second resistance value being different, a current generating device, coupled to a first terminal of the resistance element, the current generating device being designed to generate a current with a first amplitude through the resistance element when a predetermined potential is present at a second terminal of the resistance element, in order to convert the resistance element into the first state for setting the first resistance value, or to generate a current with a second amplitude through the resistance element when the predetermined potential is present at the second terminal of the resistance element, in order to convert the resistance element into the second state for setting the second resistance value, the first resistance value representing a first memory state and the second resistance value representing a second memory state.
摘要翻译：存储元件包括具有第一状态的第一电阻值和第二状态的第二电阻值的电阻元件，可以将电阻元件从第一状态转换为第二状态并从第二状态转换为第一状态状态，并且所述第一电阻值和所述第二电阻值不同;电流产生装置，耦合到所述电阻元件的第一端子，所述电流产生装置被设计成当预定的电流值产生具有第一振幅的电流时，电位存在于电阻元件的第二端子处，以便将电阻元件转换成用于设定第一电阻值的第一状态，或者当预定电位存在于电阻元件时通过电阻元件产生具有第二幅度的电流电阻元件的第二端子，以便将电阻元件转换成第二端子状态，用于设定第二电阻值，第一电阻值表示第一存储状态，第二电阻值表示第二存储状态。

60. 发明申请

US20060120138A1 Semiconductor memory with volatile and non-volatile memory cells 审中-公开
标题翻译：具有易失性和非易失性存储单元的半导体存储器
公开(公告)号：US20060120138A1
公开(公告)日：2006-06-08
申请号：US11260691
申请日：2005-10-28
申请人： Corvin Liaw , Josef Willer , Michael Kund
发明人： Corvin Liaw , Josef Willer , Michael Kund
IPC分类号： G11C11/24
CPC分类号： G11C14/00 , B82Y10/00 , G11C13/0009 , G11C13/0014 , G11C13/0016 , G11C14/0045 , H01L27/105 , H01L27/10897 , H01L27/286 , H01L51/0595
摘要： The present invention relates to a semiconductor memory with a volatile memory device, in particular a DRAM memory device, and with a non-volatile memory device. The volatile memory device is electrically coupled with the non-volatile memory device, and the non-volatile memory device has a polymer memory device adapted to be switched between two states of information.
摘要翻译：本发明涉及具有易失性存储器件，特别是DRAM存储器件以及非易失性存储器件的半导体存储器。易失性存储器件与非易失性存储器件电耦合，并且非易失性存储器件具有适于在两种信息状态之间切换的聚合物存储器件。

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