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51. 发明授权

US07885123B2 Integrated circuit for memory card and memory card using the circuit 有权
标题翻译：用于存储卡和存储卡的集成电路使用该电路
公开(公告)号：US07885123B2
公开(公告)日：2011-02-08
申请号：US09881581
申请日：2001-06-14
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： G11C16/04 , G11C7/10 , G11C16/06 , G11C16/18 , G11C8/12
CPC分类号： G11C16/102 , G11C7/16 , G11C16/18
摘要： An integrated circuit for storing data, and for application in a memory card that operates in cooperation with at least one of an external acquisition system and an external processing system includes input/output terminals for receiving the data to be stored, and an electrically programmable non-volatile memory for storing the data in digital format. The memory includes a first terminal for receiving a programming signal for enabling storage of the data, and a second terminal for receiving a reading signal for enabling output of the stored data via the input/output terminals. A memory control circuit is connected to the first and second terminals of the electrically programmable non-volatile memory, and to the input/output terminals for generating programming and reading signals based upon the command signal. The electrically programmable non-volatile memory is erasable by electromagnetic radiation for permitting a non-electrical erasure of the stored data.
摘要翻译：一种用于存储数据并用于应用于与外部采集系统和外部处理系统中的至少一个协同操作的存储卡的集成电路，包括用于接收要存储的数据的输入/输出端子，用于以数字格式存储数据的非易失性存储器。存储器包括用于接收用于使数据存储的编程信号的第一端子，以及用于接收经由输入/输出端子输出存储的数据的读取信号的第二端子。存储器控制电路连接到电可编程非易失性存储器的第一和第二端子以及输入/输出端子，用于基于该命令信号产生编程和读取信号。电可编程非易失性存储器可通过电磁辐射进行擦除，以允许存储数据的非电擦除。

52. 发明授权

US07649778B2 Method for accessing in reading, writing and programming to a NAND non-volatile memory electronic device monolithically integrated on semiconductor 有权
标题翻译：用于访问在单片集成在半导体上的NAND非易失性存储器电子器件的读取，写入和编程的方法
公开(公告)号：US07649778B2
公开(公告)日：2010-01-19
申请号：US12409740
申请日：2009-03-24
申请人： Luigi Pascucci , Paolo Rolandi
发明人： Luigi Pascucci , Paolo Rolandi
IPC分类号： G11C16/04
CPC分类号： G11C5/066 , G11C7/1018 , G11C7/1045 , G11C16/0483 , G11C16/08 , G11C2207/105
摘要： A method for accessing, in reading, programming, and erasing a semiconductor-integrated non-volatile memory device of the Flash EEPROM type with a NAND architecture having at least one memory matrix organized in rows or word lines and columns or bit lines, and wherein, for the memory, a plurality of additional address pins are provided. The method provides both an access protocol of the asynchronous type and a protocol of the extended type allowing to address, directly and in parallel, a memory extended portion by loading an address register associated with the additional pins in two successive clock pulses. A third multi-sequential access mode and a parallel additional bus referring to the additional address pins are also provided to allow a double addressing mode, sequential and in parallel.
摘要翻译：一种用于以具有至少一个以行或字线和列或位线组织的存储矩阵的NAND架构来访问，读取，编程和擦除闪存EEPROM类型的半导体集成非易失性存储器件的方法，其中为了存储器，提供了多个附加的地址引脚。该方法提供异步类型的访问协议和扩展类型的协议，允许通过在两个连续的时钟脉冲中加载与附加引脚相关联的地址寄存器来直接和并行地寻址存储器扩展部分。还提供了第三个多次访问模式和引用附加地址引脚的并行附加总线，以允许双寻址模式，顺序和并行。

53. 发明授权

US07649773B2 Row selector circuit for electrically programmable and erasable non volatile memories 有权
标题翻译：用于电可编程和可擦除非易失性存储器的行选择器电路
公开(公告)号：US07649773B2
公开(公告)日：2010-01-19
申请号：US12244717
申请日：2008-10-02
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： G11C16/00
CPC分类号： G11C8/10 , G11C16/16
摘要： The invention relates to a row decoder circuit for non volatile memory devices of the electrically programmable and erasable type, for example of the Flash EEPROM type having a NOR architecture. The proposed row decoder circuit allows to carry out the erasing step very quickly, for example with a granularity emulating at least 16 kB and even overcoming by at least 2 kB Flash memories of the NAND type. The memory can thus maintain high performances in terms of random access speed but shows a high erasing speed typical of memory architectures of the NAND type.
摘要翻译：本发明涉及一种用于电可编程和可擦除类型的非易失性存储器件的行解码器电路，例如具有NOR架构的闪速EEPROM类型。所提出的行解码器电路允许非常快速地执行擦除步骤，例如，以至少16kB的粒度并且甚至由NAND类型的至少2kB的闪存来克服的粒度。因此，存储器可以在随机访问速度方面保持高性能，但是显示出NAND类型的存储器架构的典型的高擦除速度。

54. 发明授权

US07295472B2 Integrated electronic non-volatile memory device having nand structure 有权
标题翻译：具有nand结构的集成电子非易失性存储器件
公开(公告)号：US07295472B2
公开(公告)日：2007-11-13
申请号：US11279384
申请日：2006-04-11
申请人： Luigi Pascucci , Paolo Rolandi
发明人： Luigi Pascucci , Paolo Rolandi
IPC分类号： G11C11/34
CPC分类号： G11C16/08 , G11C16/0408 , G11C16/0483 , G11C16/12 , G11C16/24 , Y10T29/49002
摘要： A non-volatile memory electronic device is integrated on a semiconductor and is of the Flash EEPROM type with an architecture of the NAND type including at least one memory matrix divided into sectors being singularly erasable and organized in rows or word lines and columns or bit lines of memory cells. Advantageously, the matrix may include logic sectors wherein pairs of rows or word lines are electrically short-circuited and refer to a single biasing terminal, source terminals of the associated cells of each pair of rows associated with a same source select line referring to a corresponding biasing terminal, and at least one pair of independent drain select lines, each of the rows and of the lines being provided with metallization shunts to by-pass groups of bit lines and/or to speed up the propagation times of the biasing in the corresponding logic sector.
摘要翻译：非易失性存储器电子器件集成在半导体上，并且是具有NAND型结构的闪存EEPROM类型，包括被划分成扇区的至少一个存储器矩阵，其被单独地擦除并且被组织成行或字线和列或位线的记忆细胞。有利地，矩阵可以包括其中行或字线对被电短路并且指代单个偏置端子的逻辑扇区，每对行的相关联的单元的源极端子与相应的源选择线相关联，其指向相应的偏置端子以及至少一对独立的漏极选择线，行和行中的每一行被设置有金属化分流器以逐行排列组和/或加速相应的偏置的传播时间逻辑部门。

55. 发明授权

US07274594B2 Non-volatile memory electronic device with NAND structure being monolithically integrated on semiconductor 有权
标题翻译：具有NAND结构的非易失性存储器电子器件单片集成在半导体上
公开(公告)号：US07274594B2
公开(公告)日：2007-09-25
申请号：US11279378
申请日：2006-04-11
申请人： Luigi Pascucci , Paolo Rolandi
发明人： Luigi Pascucci , Paolo Rolandi
IPC分类号： G11C16/04
CPC分类号： G11C16/08 , G11C16/0408 , G11C16/0483 , G11C16/12 , G11C16/24 , Y10T29/49002
摘要： A non-volatile memory electronic device is integrated on a semiconductor with an architecture including at least one memory matrix organized in rows or word lines and columns or bit lines of memory cells. The matrix is divided into at least a first and a second memory portions having a different access speed. The first and second memory portions may share the structures of the bit lines which correspond to one another and one by one and are electrically interrupted by controlled switches placed between the first and the second portions.
摘要翻译：非易失性存储器电子器件集成在具有包括以行或字线和存储器单元的列或位线组织的至少一个存储器矩阵的架构的半导体上。矩阵被分成至少具有不同访问速度的第一和第二存储器部分。第一和第二存储器部分可以共享彼此对应的位线的结构并且逐个地并且被放置在第一和第二部分之间的受控开关电中断。

56. 发明授权

US07072212B2 String programmable nonvolatile memory with NOR architecture 有权
标题翻译：具有NOR架构的字符串可编程非易失性存储器
公开(公告)号：US07072212B2
公开(公告)日：2006-07-04
申请号：US10742429
申请日：2003-12-19
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： G11C14/00
CPC分类号： G11C16/08 , G11C8/10
摘要： A nonvolatile memory with a memory array arranged in rows and columns of memory cells in NOR configuration, the memory cells arranged on a same column being connected to one of a plurality of bit lines and a column decoder. The column decoder comprises a plurality of selection stages, each of which is connected to respective bit lines and receives first bit line addressing signals. The selection stages comprise word programming selectors controlled by the first bit line addressing signals and supplying a programming voltage to only one of the bit lines of each selection stage. Each selection stage moreover comprises a string programming selection circuit controlled by second bit line addressing signals thereby simultaneously supplying the programming voltage to a plurality of the bit lines of each selection stage.
摘要翻译：一种非易失性存储器，其具有以NOR形式排列成存储器单元的行和列的存储器阵列，布置在同一列上的存储器单元连接到多个位线之一和列解码器。列解码器包括多个选择级，每个选择级连接到相应的位线并且接收第一位线寻址信号。选择级包括由第一位线寻址信号控制的字编程选择器，并将编程电压提供给每个选择级的仅一位位线。每个选择级还包括由第二位线寻址信号控制的串编程选择电路，从而同时将编程电压提供给每个选择级的多个位线。

57. 发明授权

US06967876B2 Method for controlling programming voltage levels of non-volatile memory cells, the method tracking the cell features, and corresponding voltage regulator 有权
标题翻译：用于控制非易失性存储单元的编程电压电平的方法，跟踪单元特征的方法以及相应的电压调节器
公开(公告)号：US06967876B2
公开(公告)日：2005-11-22
申请号：US10651019
申请日：2003-08-28
申请人： Paolo Rolandi , Luigi Pascucci
发明人： Paolo Rolandi , Luigi Pascucci
IPC分类号： G11C11/00 , G11C11/34 , G11C16/12
CPC分类号： G11C16/12
摘要： A method for controlling programming voltage levels of non-volatile memory cells comprises: providing a resistive divider connected to a programming voltage reference and effective to generate at least one programming voltage level; and providing a reference cell crossed by a cell current. Advantageously according to an embodiment of the invention the cell current is applied to the resistive divider to correlate the programming voltage level to the intrinsic features of the reference cell. A programming voltage regulator of non-volatile memory cells comprises at least an input stage inserted between a first and a second voltage reference and connected to a reference memory cell, as well as, in correspondence with its output terminal, to a resistive divider, inserted in turn between a programming voltage reference and the second voltage reference and connected to at least an output terminal of the regulator, effective to supply the programming voltage to the non-volatile memory cells. Advantageously according to an embodiment of the invention, the output terminal of the input stage is connected to a first circuit node of the resistive divider in correspondence with an end of a resistive element comprised in the resistive divider and having a further end connected to the programming voltage reference. In such a way, a voltage value obtained by shunting the programming voltage reference is applied at the first circuit node. The voltage regulator according to embodiments of the invention can be used in two-level contexts and in multilevel contexts, even for parallel programming of several multilevel memory cells.
摘要翻译：用于控制非易失性存储器单元的编程电压电平的方法包括：提供连接到编程电压参考并有效地产生至少一个编程电压电平的电阻分压器; 并提供由电池电流交叉的参考电池。有利地，根据本发明的实施例，电池电流被施加到电阻分压器以将编程电压电平与参考单元的固有特征相关联。非易失性存储单元的编程电压调节器至少包括插入在第一和第二参考电压之间并连接到参考存储器单元的输入级，以及与其输出端相对应的电阻分压器，插入在编程电压基准和第二参考电压之间，并连接到调节器的至少一个输出端，有效地将编程电压提供给非易失性存储单元。有利地，根据本发明的实施例，输入级的输出端子与电阻分压器的第一电路节点相对应地连接到电阻分压器中包含的电阻元件的端部，并具有连接到编程的另一端电压参考。以这种方式，在第一电路节点处施加通过分流编程电压基准获得的电压值。根据本发明的实施例的电压调节器可以在两级上下文和多级上下文中使用，甚至可以用于几个多电平存储器单元的并行编程。

58. 发明授权

US06965523B2 Multilevel memory device with memory cells storing non-power of two voltage levels 有权
公开(公告)号：US06965523B2
公开(公告)日：2005-11-15
申请号：US10964160
申请日：2004-10-12
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： G11C16/02 , G11C11/56 , G11C19/28 , G11C16/04
CPC分类号： G11C19/282 , G11C11/5628 , G11C11/5642
摘要： According to the multilevel programming method, each memory location can be programmed at a non-binary number of levels. The bits to be stored in the two locations are divided into two sets, wherein the first set defines a number of levels higher than the non-binary number of levels. During programming, if the first set of bits to be written corresponds to a number smaller than the non-binary number of levels, the first set of bits is written in the first location and the second set of bits is written in the second location; ifit is greater than the non-binary number of levels, the first set of bits is written in the second location and the second set of bits is written in the first location. The bits of the first set in the second location are stored in different levels with respect to the bits of the second set.

59. 发明申请

US20050063219A1 Multilevel memory device with memory cells storing non-power of two voltage levels 有权
标题翻译：具有存储单元的多级存储器件存储两个电压电平的非功率
公开(公告)号：US20050063219A1
公开(公告)日：2005-03-24
申请号：US10964160
申请日：2004-10-12
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： G11C16/02 , G11C11/56 , G11C19/28 , G11C11/00
CPC分类号： G11C19/282 , G11C11/5628 , G11C11/5642
摘要： According to the multilevel programming method, each memory location can be programmed at a non-binary number of levels. The bits to be stored in the two locations are divided into two sets, wherein the first set defines a number of levels higher than the non-binary number of levels. During programming, if the first set of bits to be written corresponds to a number smaller than the non-binary number of levels, the first set of bits is written in the first location and the second set of bits is written in the second location; ifit is greater than the non-binary number of levels, the first set of bits is written in the second location and the second set of bits is written in the first location. The bits of the first set in the second location are stored in different levels with respect to the bits of the second set.
摘要翻译：根据多级编程方法，每个存储器位置可以以非二进制数的级编程。要存储在两个位置中的位被分成两组，其中第一组定义高于非二进制数量级的级数。在编程期间，如果要写入的第一组位对应于小于非二进制数量级的数字，则将第一组位写入第一位置，并将第二组位写入第二位置; 如果大于非二进制数量级，则将第一组位写入第二位置，并将第二组位写入第一位置。第二位置中的第一组的位相对于第二组的位被存储在不同的电平。

60. 发明授权

US06363015B1 Reading method for non-volatile memories with sensing ratio variable with the reading voltage, and device to realize said method 有权
标题翻译：具有读取电压的感测比变量的非易失性存储器的读取方法，以及实现所述方法的装置
公开(公告)号：US06363015B1
公开(公告)日：2002-03-26
申请号：US09589723
申请日：2000-06-08
申请人： Antonio Barcella , Paolo Rolandi
发明人： Antonio Barcella , Paolo Rolandi
IPC分类号： G11C1606
CPC分类号： G11C16/28
摘要： A reading method for non-volatile memory cells is which includes a first step in which a memory cell of the matrix is selected by the row decoder and by the column multiplexer, a second step of preload and equalization during which the voltage on the drain electrode of the selected memory cell reaches a defined value and a third step during which the selected cell is read with a sensing ratio depending on the reading voltage of said cell. Moreover a device for the reading of the cells is described, which comprises a modulation branch with at least one modulation transistor and a load generator associated with said modulation transistor in such a way to modulate analogous the transconductance of one of the two load transistors as a function of the reading voltage of the memory cell.
摘要翻译：用于非易失性存储单元的读取方法包括第一步骤，其中由行解码器和列多路复用器选择矩阵的存储单元，预加载和均衡的第二步骤，其中漏电极上的电压所选择的存储单元达到限定值和第三步骤，在该步骤期间，根据所述单元的读取电压以感测比率读取所选择的单元。此外，描述了用于读取单元的器件，其包括具有至少一个调制晶体管的调制分支和与所述调制晶体管相关联的负载发生器，以这样的方式将两个负载晶体管中的一个的跨导类似于存储单元的读取电压的功能。

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