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51. 发明授权

US08415248B2 Self-aligned dual damascene BEOL structures with patternable low-k material and methods of forming same 有权
标题翻译：具有可编程低k材料的自对准双镶嵌BEOL结构及其形成方法
公开(公告)号：US08415248B2
公开(公告)日：2013-04-09
申请号：US13474349
申请日：2012-05-17
申请人： Shyng-Tsong Chen , Qinghuang Lin , Sampath Purushothaman , Terry A. Spooner , Shawn M. Walsh
发明人： Shyng-Tsong Chen , Qinghuang Lin , Sampath Purushothaman , Terry A. Spooner , Shawn M. Walsh
IPC分类号： H01L21/4763
CPC分类号： H01L23/5329 , H01L21/4846 , H01L21/76801 , H01L21/76808 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76831 , H01L23/49894 , H01L23/53295 , H01L2221/1031 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided.
摘要翻译：提供了自对准的互连结构，其包括位于衬底的表面上的第一图案化和固化的低k材料，其中第一图案化和固化的低k材料包括至少一个第一互连图案（通孔或沟槽图案）其中。具有不同于第一互连图案的至少一个第二互连图案的第二图案化和固化的低k材料位于第一图案化和固化的低k材料的顶部。第二图案化和固化的低k材料的一部分部分地填充第一图案化和固化的低k材料内的至少一个第一互连。导电材料填充至少一个第一互连图案和至少一个第二互连图案。还提供了形成这种自对准互连结构的方法。

52. 发明授权

US08399336B2 Method for fabricating a 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer 有权
标题翻译：用于制造具有在较高成本的有源电路层之前堆叠的较低成本有源电路层的3D集成电路器件的方法
公开(公告)号：US08399336B2
公开(公告)日：2013-03-19
申请号：US12194211
申请日：2008-08-19
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
IPC分类号： H01L21/30
CPC分类号： H01L25/50 , H01L21/6835 , H01L21/76898 , H01L21/8221 , H01L25/0657 , H01L25/18 , H01L27/0688 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L2221/68377 , H01L2224/0401 , H01L2224/05558 , H01L2224/0557 , H01L2224/131 , H01L2224/16 , H01L2224/16227 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/73153 , H01L2224/73253 , H01L2224/83121 , H01L2224/83895 , H01L2224/92242 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/00011 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/15311 , H01L2924/157 , H01L2924/37001 , H01L2224/80001 , H01L2924/014 , H01L2224/83 , H01L2224/11
摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. The first active circuitry layer wafer is lower-cost than the other wafer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.
摘要翻译：提供了一种用于制造3D集成电路结构的方法。根据该方法，提供包括有源电路的第一有源电路层晶片，并且去除第一有源电路层晶片的第一部分，使得第一有源电路层晶片的第二部分保留。提供了包括有源电路的另一个晶片，另一个晶片结合到第一有源电路层晶片的第二部分。第一有源电路层晶片比另一个晶片低成本。还提供了用用于制造3D集成电路结构的程序编码的有形计算机可读介质和3D集成电路结构。

53. 发明申请

US20120309127A1 METHOD FOR FABRICATING 3D INTEGRATED CIRCUIT DEVICE USING INTERFACE WAFER AS PERMANENT CARRIER 有权
标题翻译：使用界面波形作为永久载体制作3D集成电路设备的方法
公开(公告)号：US20120309127A1
公开(公告)日：2012-12-06
申请号：US13572037
申请日：2012-08-10
申请人： Mukta G. FAROOQ , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
发明人： Mukta G. FAROOQ , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
IPC分类号： H01L21/60
CPC分类号： H01L25/0657 , H01L21/6835 , H01L25/18 , H01L25/50 , H01L2221/68377 , H01L2224/0401 , H01L2224/05001 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05558 , H01L2224/05568 , H01L2224/0557 , H01L2224/056 , H01L2224/131 , H01L2224/16227 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/73153 , H01L2224/73253 , H01L2224/83121 , H01L2224/83895 , H01L2224/92242 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/15311 , H01L2924/157 , H01L2924/37001 , H01L2224/83 , H01L2224/11 , H01L2924/014 , H01L2924/00014
摘要： A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.
摘要翻译：提供了一种计算机可读介质，其由包括用于执行制造3D集成电路结构的方法的指令的程序编码。提供了包括第一布线层和穿硅通孔的接口晶片，以及包括有源电路的第一有源电路层晶片。第一有源电路层晶片被结合到界面晶片。然后，去除第一有源电路层晶片的第一部分，使得第二部分保持附着到界面晶片。包括接口晶片和第一有源电路层晶片的第二部分的堆叠结构被结合到基底晶片。接下来，将界面晶片减薄以形成界面层，并且在界面层上形成通过界面层中的穿硅通孔耦合到第一布线层的金属化。

54. 发明授权

US08314005B2 Homogeneous porous low dielectric constant materials 有权
标题翻译：均质多孔低介电常数材料
公开(公告)号：US08314005B2
公开(公告)日：2012-11-20
申请号：US13010004
申请日：2011-01-20
申请人： Sampath Purushothaman , Geraud Jean-Michel Dubois , Teddie P. Magbitang , Willi Volksen , Theo J. Frot
发明人： Sampath Purushothaman , Geraud Jean-Michel Dubois , Teddie P. Magbitang , Willi Volksen , Theo J. Frot
IPC分类号： H01L21/76
CPC分类号： H01L21/3105 , H01L21/02203 , H01L21/7682 , H01L2221/1047
摘要： In one exemplary embodiment, a method includes: providing a structure having a first layer overlying a substrate, where the first layer includes a dielectric material having a plurality of pores; applying a filling material to an exposed surface of the first layer; heating the structure to a first temperature to enable the filling material to homogeneously fill the plurality of pores; after filling the plurality of pores, performing at least one process on the structure; and after performing the at least one process, removing the filling material from the plurality of pores by heating the structure to a second temperature to decompose the filling material.
摘要翻译：在一个示例性实施例中，一种方法包括：提供具有覆盖衬底的第一层的结构，其中第一层包括具有多个孔的电介质材料; 将填充材料施加到第一层的暴露表面; 将结构加热到第一温度以使填充材料均匀地填充多个孔; 在填充所述多个孔之后，在所述结构上执行至少一个处理; 并且在执行所述至少一个处理之后，通过将所述结构加热至第二温度以分解所述填充材料，从所述多个孔中除去所述填充材料。

55. 发明申请

US20120193752A1 Novel 3D Integration Method Using SOI Substrates and Structures Produced Thereby 有权
标题翻译：使用SOI基板和结构生成的新型3D积分方法
公开(公告)号：US20120193752A1
公开(公告)日：2012-08-02
申请号：US13016994
申请日：2011-01-29
申请人： Sampath Purushothaman , Roy Rongqing Yu
发明人： Sampath Purushothaman , Roy Rongqing Yu
IPC分类号： H01L27/12 , H01L21/60
CPC分类号： H01L21/76897 , H01L21/304 , H01L21/30604 , H01L21/76251 , H01L21/76256 , H01L21/76802 , H01L21/76805 , H01L21/7684 , H01L21/76879 , H01L21/76898 , H01L21/84 , H01L23/5226 , H01L23/544 , H01L24/03 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/89 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L27/1203 , H01L27/1207 , H01L29/0649 , H01L2221/68372 , H01L2223/54426 , H01L2224/03002 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/11002 , H01L2224/1148 , H01L2224/11616 , H01L2224/13007 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/17181 , H01L2224/8013 , H01L2224/81005 , H01L2224/81065 , H01L2224/81075 , H01L2224/8109 , H01L2224/81093 , H01L2224/81193 , H01L2224/81201 , H01L2224/81209 , H01L2224/9202 , H01L2224/94 , H01L2225/06548 , H01L2924/00014 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2224/03 , H01L2224/11 , H01L2224/81 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.
摘要翻译：通过这种方法制造的工艺和最终的制品包括将包含硅绝缘体（SOI）的顶部硅晶片中的将底部硅晶片中的底部器件层连接到顶部器件层中的底部器件层所需的通孔形成，晶圆。通孔以这样的方式设置，使得它们从顶部晶片的线（MOL）互连的中间延伸到SOI晶片的掩埋氧化物（BOX）层，其中提供了适当的绝缘以将它们与SOI器件层隔离开。

56. 发明申请

US20120149173A1 3D INTEGRATED CIRCUIT DEVICE FABRICATION WITH PRECISELY CONTROLLABLE SUBSTRATE REMOVAL 有权
标题翻译：具有精密可控底板拆卸的3D集成电路设备制造
公开(公告)号：US20120149173A1
公开(公告)日：2012-06-14
申请号：US13398481
申请日：2012-02-16
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Sampath Purushothaman , Roy R. Yu
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Sampath Purushothaman , Roy R. Yu
IPC分类号： H01L21/30
CPC分类号： H01L27/105 , H01L24/11 , H01L27/0688 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05147 , H01L2224/05184 , H01L2224/05568 , H01L2224/0557 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/05599
摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a non-transitory computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.
摘要翻译：提供了一种用于制造3D集成电路结构的方法。根据该方法，提供第一有源电路层晶片。第一有源电路层晶片包括由P层覆盖的P +部分，并且P层包括有源电路。第一有源电路层晶片面向下接合到包括第一布线层的接口晶片，然后相对于第一有源电路层晶片的P层选择性地去除第一有源电路层晶片的P +部分。接下来，在P-层的背面上制造布线层。还提供了编码有用于制造3D集成电路结构的程序的非暂时计算机可读介质，以及3D集成电路结构。

57. 发明授权

US08129286B2 Reducing effective dielectric constant in semiconductor devices 有权
标题翻译：降低半导体器件中的有效介电常数
公开(公告)号：US08129286B2
公开(公告)日：2012-03-06
申请号：US12139803
申请日：2008-06-16
申请人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
发明人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
IPC分类号： H01L21/302 , B44C1/22
CPC分类号： B82Y30/00 , H01L21/0332 , H01L21/31111 , H01L21/31144 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.
摘要翻译：制造半导体器件结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在该绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成亚光刻特征跨越至少一个互连的侧壁。

58. 发明授权

US07969770B2 Programmable via devices in back end of line level 有权
标题翻译：可通过线路级后端设备进行编程
公开(公告)号：US07969770B2
公开(公告)日：2011-06-28
申请号：US11833321
申请日：2007-08-03
申请人： Kuan-Neng Chen , Lia Krusin-Elbaum , Dennis M. Newns , Sampath Purushothaman
发明人： Kuan-Neng Chen , Lia Krusin-Elbaum , Dennis M. Newns , Sampath Purushothaman
IPC分类号： G11C11/00
CPC分类号： H01L28/65 , H01L28/20 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/1286 , H01L45/144 , H01L45/148 , H01L45/1683 , Y10S977/754
摘要： Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided. The programmable via device comprises a first dielectric layer; at least one isolation layer over the first dielectric layer; a heater within the isolation layer; a capping layer over a side of the isolation layer opposite the first dielectric layer; at least one programmable via extending through the capping layer and at least a portion of the isolation layer and in contact with the heater, the programmable via comprising at least one phase change material; a conductive cap over the programmable via; a second dielectric layer over a side of the capping layer opposite the isolation layer; a first conductive via and a second conductive via, each extending through the second dielectric layer, the capping layer and at least a portion of the isolation layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive cap.
摘要翻译：提供可编程的器件及其制造方法。在一个方面，提供了可编程通路装置。可编程通孔装置包括第一介电层; 在所述第一介电层上方的至少一个隔离层; 隔离层内的加热器; 在所述隔离层的与所述第一介电层相对的一侧上的覆盖层; 至少一个可编程通道，其延伸穿过所述封盖层和所述隔离层的至少一部分并与所述加热器接触，所述可编程通孔包括至少一个相变材料; 可编程通孔上的导电盖; 在覆盖层的与隔离层相对的一侧上的第二电介质层; 第一导电通孔和第二导电通孔，每个延伸穿过第二介电层，封盖层和至少一部分隔离层并与加热器接触; 以及延伸穿过所述第二介电层并与所述导电盖接触的第三导电通孔。

59. 发明授权

US07968450B2 Methods for incorporating high dielectric materials for enhanced SRAM operation and structures produced thereby 有权
标题翻译：用于引入用于增强SRAM操作的高介电材料和由此产生的结构的方法
公开(公告)号：US07968450B2
公开(公告)日：2011-06-28
申请号：US12543999
申请日：2009-08-19
申请人： Azeez J. Bhavnagarwala , Stephen V. Kosonocky , Satyanarayana V. Nitta , Sampath Purushothaman
发明人： Azeez J. Bhavnagarwala , Stephen V. Kosonocky , Satyanarayana V. Nitta , Sampath Purushothaman
IPC分类号： H01L21/768
CPC分类号： H01L21/76801 , G11C11/412 , H01L23/53295 , H01L27/11 , H01L27/1104 , H01L2924/0002 , H01L2924/00
摘要： Methods for fabricating a hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip. Several methods to fabricate such a structure are provided. Circuit implementations of such hybrid interconnect structures are described that enable increased static noise margin and reduce the leakage in SRAM cells and common power supply voltages for SRAM and logic in such a chip. Methods that enable combining these circuit benefits with higher interconnect performance speed and superior mechanical robustness in such chips are also taught.
摘要翻译：制造在一组区域中具有比在同一微电子芯片上的其它区域更高的互连电容的混合互连结构的方法。提供了几种制造这种结构的方法。描述了这样的混合互连结构的电路实现，其能够增加静态噪声容限并且减少SRAM单元中的泄漏以及用于这种芯片中的SRAM和逻辑的公共电源电压。还教导了能够将这些电路优点与更高的互连性能速度和优异的机械鲁棒性相结合的方法。

60. 发明申请

US20100207276A1 SPIN-ON ANTIREFLECTIVE COATING FOR INTEGRATION OF PATTERNABLE DIELECTRIC MATERIALS AND INTERCONNECT STRUCTURES 有权
标题翻译：用于整合电介质材料和互连结构的旋转抗反射涂层（SPIN-ON ANTIREFLECTIVE COATING FOR INTEGRATION OF PATTERNABLE DIELECTRIC MATERIALS AND INTERCONNECT STRUCTURES
公开(公告)号：US20100207276A1
公开(公告)日：2010-08-19
申请号：US12772451
申请日：2010-05-03
申请人： Robert D. Allen , Phillip J. Brock , Blake W. Davis , Wu-Song S. Huang , Qinghuang Lin , Alshakim Nelson , Sampath Purushothaman , Ratnam Sooriyakumaran
发明人： Robert D. Allen , Phillip J. Brock , Blake W. Davis , Wu-Song S. Huang , Qinghuang Lin , Alshakim Nelson , Sampath Purushothaman , Ratnam Sooriyakumaran
IPC分类号： H01L23/522 , C09D5/00
CPC分类号： H01L21/76808 , H01L21/02137 , H01L21/02282 , H01L21/02304 , H01L21/02348 , H01L21/0276 , H01L21/3122 , H01L21/76802 , H01L21/76835 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , Y10T428/24802 , H01L2924/00
摘要： The present invention provides a method of fabricating an interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and a dielectric material. Specifically, this invention relates to a simplified method of fabricating single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric and at least one inorganic antireflective coating. In general terms, a method is provided that includes providing at least one patternable low-k material on a surface of an inorganic antireflective coating that is located atop a substrate. The inorganic ARC is liquid deposited and comprises a polymer that has at least one monomer unit comprising the formula M-R1 wherein M is at least one of Si, Ge, B, Sn, Fe, Ta, Ti, Ni, Hf and La and R1 is a chromophore. At least one interconnect pattern is formed within the at least one patternable low-k material and thereafter the at least one patternable low-k material is cured. The inventive method can be used to form dual-damascene interconnect structures as well as single-damascene interconnect structures.
摘要翻译：本发明提供一种制造互连结构的方法，其中可图案化的低k材料替代了使用单独的光致抗蚀剂和电介质材料的需要。具体地说，本发明涉及一种制备具有至少一个可图案化的低k电介质和至少一种无机抗反射涂层的单镶嵌和双镶嵌低k互连结构的简化方法。通常，提供了一种方法，其包括在位于基底顶部的无机抗反射涂层的表面上提供至少一种可图案化的低k材料。无机ARC是液体沉积的，并且包含具有至少一个单体单元的聚合物，该单体单元包括式M-R1，其中M是Si，Ge，B，Sn，Fe，Ta，Ti，Ni，Hf和La中的至少一种， R1是发色团。在至少一个可模制的低k材料内形成至少一个互连图案，此后至少一个可图案化的低k材料固化。本发明的方法可用于形成双镶嵌互连结构以及单镶嵌互连结构。

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