专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US5822655A Color image forming apparatus having intermediate transfer member 失效
标题翻译：具有中间转印部件的彩色图像形成装置
公开(公告)号：US5822655A
公开(公告)日：1998-10-13
申请号：US665358
申请日：1996-06-17
申请人： Masayuki Ikeda
发明人： Masayuki Ikeda
IPC分类号： G03G15/01 , G03G15/08 , G03G15/16 , G03G21/16
CPC分类号： G03G15/1605 , G03G21/168 , G03G2215/0177 , G03G2221/1642
摘要： The present invention provides a color image forming apparatus having an intermediate transfer member, including an electrophotographic photosensitive member, an image forming unit for forming color toner images on the photosensitive drum, an intermediate transfer member which is moved endlessly and to which the color toner images are successively transferred superimposedly, and a transfer unit for transferring the color toner images transferred to the intermediate transfer member onto a transfer material collectively. The intermediate transfer member is rotatably held by a holding member having holding plates, connecting members interconnecting them, and protruded guide members sliding on a guiding member of the image forming apparatus. The mounting and dismounting of the intermediate transfer member to or from the image forming apparatus is effected by shifting the holding member along a shifting direction of the intermediate transfer member by using the holding plates of the holding member as grips.
摘要翻译：本发明提供了一种彩色图像形成装置，其具有中间转印部件，该中间转印部件包括电子照相感光部件，用于在感光鼓上形成彩色调色剂图像的图像形成单元，中间转印部件，该中间转印部件被不断地移动，彩色调色剂图像并且转印单元用于将转印到中间转印部件上的彩色调色剂图像集中地转印到转印材料上。中间转印部件由具有保持板的保持构件，与它们互连的连接构件和在图像形成装置的引导构件上滑动的突出的引导构件可旋转地保持。通过使用保持构件的保持板作为把手，将中间转印构件安装和拆卸成图像形成装置的方法是通过沿着中间转印构件的移动方向移动保持构件来实现的。

52. 发明授权

US5592628A Data communication system which guarantees at a transmission station the arrival of transmitted data to a receiving station and method thereof 失效
标题翻译：数据通信系统，在传输站保证发送数据到达接收站及其方法
公开(公告)号：US5592628A
公开(公告)日：1997-01-07
申请号：US595505
申请日：1996-02-01
申请人： Haruhiko Ueno , Shigeru Nagasawa , Masayuki Ikeda , Naoki Shinjo , Ken-ichi Ishizaka , Teruo Utsumi , Masami Dewa , Kazushige Kobayakawa
发明人： Haruhiko Ueno , Shigeru Nagasawa , Masayuki Ikeda , Naoki Shinjo , Ken-ichi Ishizaka , Teruo Utsumi , Masami Dewa , Kazushige Kobayakawa
IPC分类号： G06F9/46 , G06F12/08 , G06F15/173 , H04L12/70 , H04L29/06 , G06F15/163
CPC分类号： G06F9/544 , G06F12/0813 , G06F15/17375
摘要： Any two of multiple processor elements are coupled with each other via a data communication network that has a definite communication buffer length and includes multiple communication buffers. A packet having a header and body is created using processed data, and then transferred by a transmitting unit. After sending the processed data, the transmitting unit transmits dummy data, having a body which is longer than the communication buffer length in the data communication network, to the same receiving station as the one to which the processed data is transmitted. The transmitting unit then guarantees a processor element serving as a receiving station the arrival of preceding processed data and the header. Control data representing cache invalidation waiting is embedded in the header of the dummy data. When a transmitting end terminates transfer of the dummy data, the sending station can guarantee the termination of cache invalidation, which is performed by the processor element serving as a receiving station to attain the consistency of the contents of preceding storage data main storage and a cache memory.
摘要翻译：多个处理器元件中的任何两个通过具有确定的通信缓冲器长度并包括多个通信缓冲器的数据通信网络相互耦合。使用处理的数据创建具有报头和主体的分组，然后由发送单元传送。在发送处理后的数据之后，发送单元将具有比数据通信网络中的通信缓冲器长度长的身体的虚拟数据发送到与发送处理后的数据相同的接收站。然后，发送单元保证作为接收站的处理器元件到达先前处理的数据和报头。表示缓存无效等待的控制数据被嵌入到伪数据的头部。当发送端终止虚拟数据的传送时，发送站可以保证由用作接收站的处理器元件执行的高速缓存无效的终止，以达到先前存储数据主存储和高速缓存的内容的一致性记忆。

53. 发明授权

US5557744A Multiprocessor system including a transfer queue and an interrupt processing unit for controlling data transfer between a plurality of processors 失效
标题翻译：包括传送队列的多处理器系统和用于控制多个处理器之间的数据传送的中断处理单元
公开(公告)号：US5557744A
公开(公告)日：1996-09-17
申请号：US104482
申请日：1993-07-28
申请人： Kazushige Kobayakawa , Shigeru Nagasawa , Masayuki Ikeda , Haruhiko Ueno , Naoki Shinjo , Teruo Utsumi , Masami Dewa , Kenichi Ishizaka
发明人： Kazushige Kobayakawa , Shigeru Nagasawa , Masayuki Ikeda , Haruhiko Ueno , Naoki Shinjo , Teruo Utsumi , Masami Dewa , Kenichi Ishizaka
IPC分类号： G06F15/16 , G06F9/54 , G06F13/24 , G06F15/17 , G06F15/177 , G06F13/00
CPC分类号： G06F15/17 , G06F13/24
摘要： A multiprocessor system having a plurality of processors connected in parallel with each other through a network for performing mutual communication. Each processor includes a transfer queue unit for storing transfer requests, a main storage, a reception unit for receiving a transfer request from another processor, and a transmission unit for sending designated data to another processor when the transfer request is enqueued in the transfer queue unit. Each processor also includes a first register for storing information indicating whether the transfer queue unit is full, i.e. has an area available for storing a transfer request, and a second register for indicating whether a transfer request is a valid transfer request during a reception operation. A save unit is connected to the reception unit for temporarily saving a transfer request, and an enqueuing unit is provided for enqueuing a transfer request from the save unit to the transfer queue unit. An interruption processing unit receives an interrupt request from the reception unit, supervises the vacant/full state of the transfer queue unit, i.e. monitors whether the transfer queue unit has an area available for storing a transfer request, and outputs an enqueuing request to the enqueuing unit to realize the interrupt request.
摘要翻译：多处理器系统具有通过网络彼此并行连接的多个处理器，用于执行相互通信。每个处理器包括用于存储传送请求的传送队列单元，主存储器，用于从另一个处理器接收传送请求的接收单元，以及当传送请求在传送队列单元中排队时将指定数据发送到另一个处理器的传输单元。每个处理器还包括第一寄存器，用于存储指示传输队列单元是否已满的信息，即具有可用于存储传送请求的区域;以及第二寄存器，用于在接收操作期间指示传输请求是否为有效传送请求。保存单元连接到接收单元以暂时保存传送请求，并且提供了一个进入单元，用于将从保存单元传送请求排队到传送队列单元。中断处理单元从接收单元接收中断请求，监视传送队列单元的空/满状态，即监视传输队列单元是否具有可用于存储传送请求的区域，并且向入队队列输出入队请求单元实现中断请求。

54. 发明授权

US5552166A Coated fried food product 失效
标题翻译：涂油炸食品
公开(公告)号：US5552166A
公开(公告)日：1996-09-03
申请号：US463104
申请日：1995-06-05
申请人： Seiki Harada , Masayuki Ikeda
发明人： Seiki Harada , Masayuki Ikeda
IPC分类号： A23L1/00 , A23L1/01 , A23L1/05 , A23L1/0528 , A23L1/0532 , A23L1/214 , A23L1/216 , A23L1/217 , A23P1/00 , A23P1/08 , A23L1/212 , A23L1/31
CPC分类号： A23L19/18 , A23L19/115 , A23L19/135 , A23L29/244 , A23L29/256 , A23P20/20
摘要： A fried food, consisting essentially of one or more solid foodstuffs and a paste-like foodstuff. The paste-like foodstuff includes a cohesive foodstuff and a condiment. The cohesive foodstuff includes one or more selected from the group of alginic acid, an alginate and glucomannan. The paste-like foodstuff coats the solid foodstuffs. The coated foodstuff is subsequently frozen or dried and then fried to produce the fried food.
摘要翻译：一种油炸食品，主要由一种或多种固体食品和糊状食品组成。糊状食品包括粘性食品和调味品。粘性食品包括选自海藻酸，藻酸盐和葡甘露聚糖的一种或多种。糊状食品涂上固体食品。随后将涂覆的食物冷冻或干燥，然后油炸以产生油炸食品。

55. 发明授权

US5478508A Method of producing seamless capsule 失效
标题翻译：生产无缝胶囊的方法
公开(公告)号：US5478508A
公开(公告)日：1995-12-26
申请号：US143475
申请日：1993-10-26
申请人： Toshiyuki Suzuki , Masayuki Ikeda , Takahiro Okuda
发明人： Toshiyuki Suzuki , Masayuki Ikeda , Takahiro Okuda
IPC分类号： A61J3/07 , B01J13/04 , B01J13/14 , B29C47/26 , B01J13/20 , B65B3/12
CPC分类号： A61K9/4833 , A61K9/5089 , B01J13/04
摘要： A process for producing a seamless capsule wherein a two-layer droplet is ejected from a double orifice type nozzle in an aqueous hardening liquid, and an outer layer of the droplet is hardened under cooling, the viscosity of the aqueous hardening liquid being made within the range of 20 to 100 mPa.multidot.s, and any difference in specific gravity between any two of the liquids of the layers ejected from the nozzle and the aqueous hardening liquid is made within 0.05.
摘要翻译：一种无水胶囊的制造方法，其特征在于，将二层液滴从双重孔型喷嘴喷出到水性硬化液中，在冷却下使液滴的外层硬化，使硬化液的粘度在范围为20〜100mPax，并且从喷嘴和水硬化液喷射的层中的任何两种液体之间的比重差异为0.05以内。

56. 再颁专利

USRE34317E Variable frequency oscillator 失效
公开(公告)号：USRE34317E
公开(公告)日：1993-07-20
申请号：US798064
申请日：1991-11-27
申请人： Masayuki Ikeda
发明人： Masayuki Ikeda
IPC分类号： G11B20/14 , H03L1/00 , H03L7/07 , H03L7/099
CPC分类号： H03L7/0805 , G11B20/1403 , H03L1/00 , H03L7/07 , H03L7/0995
摘要： A variable frequency oscillator circuit adapted for stabilization of its free-running frequency comprises a first signal synthesizing circuit, first voltage-controlled oscillator, a phase-locked loop and reference signal generator, the phase-locked loop consisting of a second signal synthesizing circuit, second voltage-controlled oscillator, phase comparator and low-pass filter. The first and second signal synthesizing circuits have the same characteristics, and the first and second voltage-controlled oscillators have the same characteristics. The reference signal and output of the second voltage-controlled oscillator are input to the phase comparator. The comparator output is applied to the first and second signal synthesizing circuits. An external signal is applied to the first signal synthesizing circuit, and the output of the first voltage-controlled oscillator acts as the output of the variable frequency oscillator circuit.The principles are applied to reading data pulses from a floppy disk.

57. 发明授权

US5175839A Storage control system in a computer system for double-writing 失效
标题翻译：存储控制系统在计算机系统中进行双重写入
公开(公告)号：US5175839A
公开(公告)日：1992-12-29
申请号：US766951
申请日：1991-09-16
申请人： Masayuki Ikeda , Koichi Ueda
发明人： Masayuki Ikeda , Koichi Ueda
IPC分类号： G06F11/14 , G11C29/00
CPC分类号： G11C29/74 , G06F11/14
摘要： In a computer system having at least a main storage unit and a memory control unit, a storage control system accesses two memory areas provided in the main storage unit, each of the two memory areas storing the same information. A double-writing device is provided in the memory control unit for writing the same information to each of the two memory areas by determining the state of a double-writing bit (D-bit) contained in an address order from a processor or the state of a storage configuration bit (F/S-bit) sent from the processor.
摘要翻译：在至少具有主存储单元和存储器控制单元的计算机系统中，存储控制系统访问设置在主存储单元中的两个存储区域，两个存储区域中的每一个存储相同的信息。在存储器控制单元中提供双写装置，用于通过从处理器或状态确定包含在地址顺序中的双写位（D位）的状态，将相同的信息写入两个存储区域中的每一个从处理器发送的存储配置位（F / S位）。

58. 外观设计

USD306861S Telephone unit 失效
公开(公告)号：USD306861S
公开(公告)日：1990-03-27
申请号：US178445
申请日：1988-04-07
申请人： Takashi Oshima , Ryoji Yamaguchi , Masayuki Ikeda
设计人： Takashi Oshima , Ryoji Yamaguchi , Masayuki Ikeda

59. 外观设计

USD294022S Combined telephone stand and handset 失效
公开(公告)号：USD294022S
公开(公告)日：1988-02-02
申请号：US823787
申请日：1986-01-29
申请人： Akira Sekiguchi , Masayuki Ikeda
设计人： Akira Sekiguchi , Masayuki Ikeda

60. 发明授权

US4567448A Variable frequency oscillator 失效
标题翻译：变频振荡器
公开(公告)号：US4567448A
公开(公告)日：1986-01-28
申请号：US520270
申请日：1983-08-04
申请人： Masayuki Ikeda
发明人： Masayuki Ikeda
IPC分类号： G11B20/14 , H03L7/07 , H03L7/099 , H03L7/00
CPC分类号： H03L7/0805 , G11B20/1403 , H03L7/07 , H03L7/0995
摘要： A variable frequency oscillator circuit adapted for stabilization of its free-running frequency comprises a first signal synthesizing circuit, first voltage-controlled oscillator, a phase-locked loop and reference signal generator, the phase-locked loop consisting of a second signal synthesizing circuit, second voltage-controlled oscillator, phase comparator and low-pass filter. The first and second signal synthesizing circuits have the same characteristics, and the first and second voltage-controlled oscillators have the same characteristics. The reference signal and output of the second voltage-controlled oscillator are input to the phase comparator. The comparator output is applied to the first and second signal synthesizing circuits. An external signal is applied to the first signal synthesizing circuit, and the output of the first voltage-controlled oscillator acts as the output of the variable frequency oscillator circuit.The principles are applied to reading data pulses from a floppy disk.
摘要翻译：适于稳定其自由运行频率的可变频率振荡器电路包括第一信号合成电路，第一压控振荡器，锁相环和参考信号发生器，由第二信号合成电路组成的锁相环，第二压控振荡器，相位比较器和低通滤波器。第一和第二信号合成电路具有相同的特性，第一和第二压控振荡器具有相同的特性。第二压控振荡器的参考信号和输出被输入到相位比较器。比较器输出被施加到第一和第二信号合成电路。外部信号施加到第一信号合成电路，第一压控振荡器的输出作为可变频率振荡电路的输出。这些原理适用于从软盘读取数据脉冲。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式