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51. 发明授权

US08809871B2 Semiconductor element and semiconductor device 有权
标题翻译：半导体元件和半导体器件
公开(公告)号：US08809871B2
公开(公告)日：2014-08-19
申请号：US13519010
申请日：2011-10-27
申请人： Masao Uchida
发明人： Masao Uchida
IPC分类号： H01L29/15
CPC分类号： H01L21/26506 , H01L21/046 , H01L29/1608 , H01L29/66068 , H01L29/7828
摘要： A semiconductor element according to the present invention includes: a semiconductor substrate of a first conductivity type; a first silicon carbide semiconductor layer of the first conductivity type on the semiconductor substrate; a body region of a second conductivity type defined in the first silicon carbide semiconductor layer; an impurity region of the first conductivity type defined in the body region; a second silicon carbide semiconductor layer of the first conductivity type on the first silicon carbide semiconductor layer; a gate insulating film on the second silicon carbide semiconductor layer; a gate electrode on the gate insulating film; a first ohmic electrode connected to the impurity region; and a second ohmic electrode on the back surface of the semiconductor substrate. The body region includes first and second body regions. The average impurity concentration of the first body region is twice or more as high as that of the second body region. And the bottom of the impurity region is deeper than that of the first body region.
摘要翻译：根据本发明的半导体元件包括：第一导电类型的半导体衬底; 在半导体衬底上的第一导电类型的第一碳化硅半导体层; 限定在第一碳化硅半导体层中的第二导电类型的体区; 在身体区域中限定的第一导电类型的杂质区域; 在第一碳化硅半导体层上的第一导电类型的第二碳化硅半导体层; 第二碳化硅半导体层上的栅极绝缘膜; 栅极绝缘膜上的栅电极; 连接到杂质区的第一欧姆电极; 以及在半导体衬底的背面上的第二欧姆电极。身体区域包括第一和第二身体区域。第一体区的平均杂质浓度为第二体区的平均杂质浓度的两倍以上。并且杂质区域的底部比第一体区域的底部更深。

52. 发明授权

US08772788B2 Semiconductor element and method of manufacturing thereof 有权
标题翻译：半导体元件及其制造方法
公开(公告)号：US08772788B2
公开(公告)日：2014-07-08
申请号：US14122823
申请日：2012-04-23
申请人： Ryo Ikegami , Masao Uchida , Yuki Tomita , Masahiko Niwayama
发明人： Ryo Ikegami , Masao Uchida , Yuki Tomita , Masahiko Niwayama
IPC分类号： H01L29/15 , H01L31/0312 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7802 , H01L21/046 , H01L21/8213 , H01L21/823412 , H01L21/823487 , H01L29/0619 , H01L29/0623 , H01L29/0696 , H01L29/1608 , H01L29/4236 , H01L29/66068 , H01L29/66666 , H01L29/7827 , H01L29/7828
摘要： A semiconductor device disclosed in the present application includes: a semiconductor substrate; a first silicon carbide semiconductor layer located on a principal surface of the semiconductor substrate, the first silicon carbide semiconductor layer including a drift region of a first conductivity type, a body region of a second conductivity type, and an impurity region of a first conductivity type; a trench provided in the first silicon carbide semiconductor layer so as to reach inside of the drift region; a second silicon carbide semiconductor layer of the first conductivity type located at least on a side surface of the trench so as to be in contact with the impurity region and the drift region; a gate insulating film; a gate electrode; a first ohmic electrode; and a second ohmic electrode. The body region includes a first body region which is in contact with the second silicon carbide semiconductor layer on the side surface of the trench, and a second body region which is in contact with the drift region and has a smaller average impurity concentration than the first body region.
摘要翻译：本申请中公开的半导体器件包括：半导体衬底; 位于所述半导体衬底的主表面上的第一碳化硅半导体层，所述第一碳化硅半导体层包括第一导电类型的漂移区，第二导电类型的体区和第一导电类型的杂质区 ; 设置在所述第一碳化硅半导体层中以便到达所述漂移区域内部的沟槽; 所述第一导电类型的第二碳化硅半导体层至少位于所述沟槽的侧表面上以与所述杂质区域和所述漂移区域接触; 栅极绝缘膜; 栅电极; 第一欧姆电极; 和第二欧姆电极。主体区域包括与沟槽侧表面上的第二碳化硅半导体层接触的第一体区域和与漂移区域接触并且具有比第一区域更小的平均杂质浓度的第二体区域身体区域。

53. 发明授权

US08742427B2 Semiconductor element 有权
标题翻译：半导体元件
公开(公告)号：US08742427B2
公开(公告)日：2014-06-03
申请号：US13504360
申请日：2011-10-14
申请人： Makoto Kitabatake , Masao Uchida
发明人： Makoto Kitabatake , Masao Uchida
IPC分类号： H01L29/15
CPC分类号： H01L29/7828 , H01L29/0696 , H01L29/1608 , H01L29/2003 , H01L29/7391
摘要： A semiconductor element according to the present invention can perform both a transistor operation and a diode operation via its channel layer. If the potential Vgs of its gate electrode 165 with respect to that of its source electrode 150 is 0 volts, then a depletion layer with a thickness Dc, which has been depleted entirely in the thickness direction, is formed in at least a part of the channel layer 150 due to the presence of a pn junction between a portion of its body region 130 and the channel layer 150, and another depletion layer that has a thickness Db as measured from the junction surface of the pn junction is formed in that portion of the body region 130. If the dielectric constant of the wide bandgap semiconductor is identified by ∈s, the dielectric constant and the thickness of the insulating film 160 are identified by ∈i and Di, respectively, the sum of Dc and Db is identified by Ds, and the absolute value of the turn-on voltage of the diode is identified by Vf0, then Ds
摘要翻译：根据本发明的半导体元件可以经由其沟道层执行晶体管操作和二极管操作两者。如果栅极电极165的电位Vgs相对于其源电极150的电压为0伏，则在至少一部分厚度方向上已经耗尽的具有厚度Dc的耗尽层由于在其主体区域130的一部分和沟道层150之间存在pn结，并且从pn结的接合表面测量出的具有厚度Db的另一个耗尽层形成在沟道层150的那部分如果宽带隙半导体的介电常数用∈s识别，则绝缘膜160的介电常数和厚度分别由∈i和Di标识，Dc和Db之和通过 Ds，二极管的导通电压的绝对值由Vf0表示，则满足Ds

54. 发明申请

US20130140586A1 SILICON CARBIDE SEMICONDUCTOR ELEMENT AND METHOD FOR PRODUCING THE SAME 有权
标题翻译：硅碳化硅半导体元件及其制造方法
公开(公告)号：US20130140586A1
公开(公告)日：2013-06-06
申请号：US13816571
申请日：2012-06-25
申请人： Kunimasa Takahashi , Masahiko Niwayama , Masao Uchida , Chiaki Kudou
发明人： Kunimasa Takahashi , Masahiko Niwayama , Masao Uchida , Chiaki Kudou
IPC分类号： H01L29/16 , H01L29/66
CPC分类号： H01L29/1608 , H01L29/045 , H01L29/1033 , H01L29/1041 , H01L29/4236 , H01L29/42368 , H01L29/66068 , H01L29/66666 , H01L29/7813 , H01L29/7827 , H01L29/7828
摘要： This silicon carbide semiconductor element includes: a body region of a second conductivity type which is located on a drift layer of a first conductivity type; an impurity region of the first conductivity type which is located on the body region; a trench which runs through the body region and the impurity region to reach the drift layer; a gate insulating film which is arranged on surfaces of the trench; and a gate electrode which is arranged on the gate insulating film. The surfaces of the trench include a first side surface and a second side surface which is opposed to the first side surface. The concentration of a dopant of the second conductivity type is higher at least locally in a portion of the body region which is located beside the first side surface than in another portion of the body region which is located beside the second side surface.
摘要翻译：该碳化硅半导体元件包括：位于第一导电类型的漂移层上的第二导电类型的体区; 位于身体区域上的第一导电类型的杂质区域; 穿过身体区域和杂质区域到达漂移层的沟槽; 布置在沟槽表面上的栅极绝缘膜; 以及设置在栅极绝缘膜上的栅电极。沟槽的表面包括与第一侧表面相对的第一侧表面和第二侧表面。第二导电类型的掺杂剂的浓度至少局部地位于位于第一侧表面旁边的身体区域的部分中，而不是位于第二侧表面旁边的身体区域的另一部分中。

55. 发明申请

US20120153303A1 SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体元件及其制造方法
公开(公告)号：US20120153303A1
公开(公告)日：2012-06-21
申请号：US13393661
申请日：2010-08-31
申请人： Masao Uchida
发明人： Masao Uchida
IPC分类号： H01L29/161 , H01L21/336
CPC分类号： H01L29/7802 , H01L29/1095 , H01L29/1608 , H01L29/41766 , H01L29/45 , H01L29/66068 , H01L29/7395 , H01L29/7813 , H01L29/7828
摘要： A semiconductor device 100 includes: a silicon carbide layer 102; a source region 104 of a first conductivity type disposed in the silicon carbide layer; a body region 103 of a second conductivity type disposed at a position in contact with the source region 104 in the silicon carbide layer; a contact region 105 of the second conductivity type formed in the body region; a drift region 102d of the first conductivity type disposed in the silicon carbide layer; and a source electrode 109 in ohmic contact with the source region 104 and the contact region 105, wherein: a side wall of the source electrode 109 is in contact with the source region 104; a lower surface of the source electrode 109 is in contact with the contact region 105 and is not in contact with the source region 104; and at least a portion of the source region 104 overlaps the contact region 105 as viewed from a direction perpendicular to a principle surface of a substrate 101.
摘要翻译：半导体器件100包括：碳化硅层102; 布置在碳化硅层中的第一导电类型的源极区104; 设置在与碳化硅层中的源极区域104接触的位置的第二导电类型的主体区域103; 形成在身体区域中的第二导电类型的接触区域105; 布置在碳化硅层中的第一导电类型的漂移区域102d; 以及与源极区域104和接触区域105欧姆接触的源电极109，其中：源电极109的侧壁与源极区域104接触; 源电极109的下表面与接触区域105接触并且不与源极区域104接触; 并且源极区104的至少一部分从垂直于衬底101的主表面的方向观察时与接触区105重叠。

56. 发明申请

US20060220027A1 Silicon carbide semiconductor device and process for producing the same 失效
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US20060220027A1
公开(公告)日：2006-10-05
申请号：US10553845
申请日：2005-01-28
申请人： Kunimasa Takahashi , Makoto Kitabatake , Kenya Yamashita , Masao Uchida , Osamu Kusumoto , Ryoko Miyanaga
发明人： Kunimasa Takahashi , Makoto Kitabatake , Kenya Yamashita , Masao Uchida , Osamu Kusumoto , Ryoko Miyanaga
IPC分类号： H01L31/0312 , H01L21/265
CPC分类号： H01L21/046
摘要： A method for fabricating a semiconductor device includes the steps of implanting ions into a silicon carbide thin film (2) formed on a silicon carbide substrate (1), heating the silicon carbide substrate in a reduced pressure atmosphere to form a carbon layer (5) on the surface of the silicon carbide substrate, and performing activation annealing with respect to the silicon carbide substrate in an atmosphere under a pressure higher than in the step of forming the carbon layer (5) and at a temperature higher than in the step of forming the carbon layer (5).
摘要翻译：一种制造半导体器件的方法包括以下步骤：将离子注入形成在碳化硅衬底（1）上的碳化硅薄膜（2）中，在减压气氛中加热碳化硅衬底以形成碳层（5）在碳化硅衬底的表面上，并且在比形成碳层（5）的步骤高的压力的气氛中，并且在高于形成步骤的温度的气氛中，相对于碳化硅衬底进行激活退火碳层（5）。

57. 发明申请

US20050173739A1 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050173739A1
公开(公告)日：2005-08-11
申请号：US10494705
申请日：2003-07-09
申请人： Osamu Kusumoto , Makoto Kitabatake , Kunimasa Takahashi , Kenya Yamashita , Ryoko Miyanaga , Masao Uchida
发明人： Osamu Kusumoto , Makoto Kitabatake , Kunimasa Takahashi , Kenya Yamashita , Ryoko Miyanaga , Masao Uchida
IPC分类号： H01L21/28 , H01L21/04 , H01L21/336 , H01L21/338 , H01L21/82 , H01L21/822 , H01L21/8232 , H01L21/8234 , H01L27/04 , H01L27/06 , H01L27/095 , H01L29/12 , H01L29/24 , H01L29/36 , H01L29/45 , H01L29/47 , H01L29/772 , H01L29/78 , H01L29/812 , H01L29/872 , H01L29/80 , H01L31/112
CPC分类号： H01L29/7813 , H01L21/0485 , H01L21/8213 , H01L27/0605 , H01L27/0629 , H01L29/1029 , H01L29/105 , H01L29/1608 , H01L29/365 , H01L29/41766 , H01L29/66068 , H01L29/7725 , H01L29/7828 , H01L29/7838 , H01L29/812 , H01L29/872 , Y10S438/931
摘要： An accumulation-mode MISFET comprises: a high-resistance SiC layer 102 epitaxially grown on a SiC substrate 101; a well region 103; an accumulation channel layer 104 having a multiple δ-doped layer formed on the surface region of the well region 103; a contact region 105; a gate insulating film 108; and a gate electrode 110. The accumulation channel layer 104 has a structure in which undoped layers 104b and δ-doped layers 104a allowing spreading movement of carriers to the undoped layers 104b under a quantum effect are alternately stacked. A source electrode 111 is provided which enters into the accumulation channel layer 104 and the contact region 105 to come into direct contact with the contact region 105. It becomes unnecessary that a source region is formed by ion implantation, leading to reduction in fabrication cost.
摘要翻译：累积模式MISFET包括：在SiC衬底101上外延生长的高电阻SiC层102; 井区域103; 具有形成在阱区域103的表面区域上的多个δ-掺杂层的累积沟道层104; 接触区域105; 栅极绝缘膜108; 和栅电极110。累积通道层104具有这样的结构，其中未掺杂层104b和δ-掺杂层104a允许载流子在量子效应下向未掺杂层104b的扩展移动交替堆叠。提供源电极111，其进入累积沟道层104和接触区域105以与接触区域105直接接触。不需要通过离子注入形成源极区域，导致制造成本的降低。

58. 发明授权

US06900483B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06900483B2
公开(公告)日：2005-05-31
申请号：US10162503
申请日：2002-06-04
申请人： Masao Uchida , Makoto Kitabatake , Toshiya Yokogawa , Osamu Kusumoto , Kunimasa Takahashi , Ryoko Miyanaga , Kenya Yamashita
发明人： Masao Uchida , Makoto Kitabatake , Toshiya Yokogawa , Osamu Kusumoto , Kunimasa Takahashi , Ryoko Miyanaga , Kenya Yamashita
IPC分类号： H01L21/329 , H01L29/24 , H01L29/872 , H01L29/80
CPC分类号： H01L29/66143 , H01L29/1608 , H01L29/872
摘要： A Schottky diode includes a semiconductor substrate made of 4H—SiC, an epitaxially grown 4H—SiC layer, an ion implantation layer, a Schottky electrode, an ohmic electrode, and an insulative layer made of a thermal oxide film. The Schottky electrode and the insulative layer are not in contact with each other, with a gap being provided therebetween, whereby an altered layer does not occur. Therefore, it is possible to suppress the occurrence of a leak current.
摘要翻译：肖特基二极管包括由4H-SiC制成的半导体衬底，外延生长的4H-SiC层，离子注入层，肖特基电极，欧姆电极和由热氧化膜制成的绝缘层。肖特基电极和绝缘层彼此不接触，其间设置有间隙，由此不发生改变的层。因此，可以抑制泄漏电流的发生。

59. 发明申请

US20050077569A1 Silicon carbide-oxide layered structure, production method thereof, and semiconductor device 有权
标题翻译：碳化硅 - 氧化物层状结构体及其制造方法以及半导体装置
公开(公告)号：US20050077569A1
公开(公告)日：2005-04-14
申请号：US10956078
申请日：2004-10-04
申请人： Kenya Yamashita , Makoto Kitabatake , Osamu Kusumoto , Kunimasa Takahashi , Masao Uchida , Ryoko Miyanaga
发明人： Kenya Yamashita , Makoto Kitabatake , Osamu Kusumoto , Kunimasa Takahashi , Masao Uchida , Ryoko Miyanaga
IPC分类号： H01L21/04 , H01L29/24 , H01L29/417 , H01L29/51 , H01L29/78 , H01L29/15
CPC分类号： H01L29/518 , H01L21/049 , H01L29/1608 , H01L29/41766 , H01L29/513 , H01L29/66068 , H01L29/7827 , H01L29/7828
摘要： A gate insulating film which is an oxide layer mainly made of SiO2 is formed over a silicon carbide substrate by thermal oxidation, and then, a resultant structure is annealed in an inert gas atmosphere in a chamber. Thereafter, the silicon carbide-oxide layered structure is placed in a chamber which has a vacuum pump and exposed to a reduced pressure NO gas atmosphere at a high temperature higher than 1100° C. and lower than 1250° C., whereby nitrogen is diffused in the gate insulating film. As a result, a gate insulating film which is a V-group element containing oxide layer, the lower part of which includes a high nitrogen concentration region, and the relative dielectric constant of which is 3.0 or higher, is obtained. The interface state density of an interface region between the V-group element containing oxide layer and the silicon carbide layer decreases.
摘要翻译：通过热氧化在碳化硅衬底上形成作为主要由SiO 2形成的氧化物层的栅极绝缘膜，然后将所得结构在室内的惰性气体气氛中退火。然后，将碳化硅 - 氧化物层叠体置于具有真空泵的室内，在高于1100℃且低于1250℃的高温下暴露于减压NO气体气氛中，由此氮气扩散在栅极绝缘膜上。结果，获得了包含氧化物层的V族元素的栅绝缘膜，其下部包括高氮浓度区域，并且其相对介电常数为3.0或更高。含V族元素的氧化物层和碳化硅层之间的界面区域的界面态密度降低。

60. 发明授权

US06654604B2 Equipment for communication system 有权
标题翻译：通讯系统设备
公开(公告)号：US06654604B2
公开(公告)日：2003-11-25
申请号：US09989270
申请日：2001-11-20
申请人： Toshiya Yokogawa , Kunimasa Takahashi , Masao Uchida , Makoto Kitabatake , Osamu Kusumoto
发明人： Toshiya Yokogawa , Kunimasa Takahashi , Masao Uchida , Makoto Kitabatake , Osamu Kusumoto
IPC分类号： H04Q720
CPC分类号： H03F3/601 , H01L21/8213 , H01L27/0605 , H01L29/105 , H01L29/157 , H01L29/1608 , H01L29/365 , H01L29/7725 , H01L29/812 , H01L29/872 , H03D7/125 , H03F2200/294
摘要： Equipment for a communication system has a semiconductor device formed by integrating a Schottky diode, a MOSFET, a capacitor, and an inductor in a SiC substrate. The SiC substrate has a first multilayer portion and a second multilayer portion provided upwardly in this order. The first multilayer portion is composed of &dgr;-doped layers each containing an n-type impurity (nitrogen) at a high concentration and undoped layers which are alternately stacked. The second multilayer portion is composed of &dgr;-doped layers each containing a p-type impurity (aluminum) at a high concentration and undoped layers which are alternately stacked. Carriers in the &dgr;-doped layers spread out extensively to the undoped layers. Because of a low impurity concentration in each of the undoped layers, scattering by impurity ions is reduced so that a low resistance and a high breakdown voltage are obtained.
摘要翻译：用于通信系统的设备具有通过将肖特基二极管，MOSFET，电容器和电感器集成在SiC衬底中而形成的半导体器件。 SiC衬底具有依次向上设置的第一多层部分和第二多层部分。第一多层部分由各自含有高浓度的n型杂质（氮）和交替层叠的未掺杂层的δ掺杂层组成。第二多层部分由各自含有高浓度的p型杂质（铝）和交替层叠的未掺杂层的δ掺杂层组成。 δ掺杂层中的载体广泛扩展到未掺杂的层。由于每个未掺杂的层中的杂质浓度低，所以杂质离子的散射被降低，从而获得低的电阻和高的击穿电压。

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