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51. 发明授权

US06376869B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06376869B1
公开(公告)日：2002-04-23
申请号：US09385013
申请日：1999-08-27
申请人： Hiroyoshi Tomita
发明人： Hiroyoshi Tomita
IPC分类号： H01L2972
CPC分类号： G11C7/1084 , G11C7/1051 , G11C7/1078
摘要： A semiconductor device includes a first terminal for inputting and outputting data and a second terminal for inputting control data in synchronization with a strobe signal. The semiconductor device includes an equivalent circuit which is provided in the second terminal. Further, the equivalent circuit has a capacitance which is equivalent to that in an output circuit which is provided in the first terminal.
摘要翻译：半导体器件包括用于输入和输出数据的第一端子和用于与选通信号同步地输入控制数据的第二端子。半导体器件包括设置在第二端子中的等效电路。此外，等效电路具有与设置在第一端子中的输出电路中的电容相当的电容。

52. 发明授权

US06369627B1 Delay circuit and semiconductor integrated circuit having same 有权
标题翻译：延迟电路和具有相同的半导体集成电路
公开(公告)号：US06369627B1
公开(公告)日：2002-04-09
申请号：US09604247
申请日：2000-06-27
申请人： Hiroyoshi Tomita
发明人： Hiroyoshi Tomita
IPC分类号： H03L706
CPC分类号： G11C7/22 , H03K5/133 , H03K5/135 , H03K2005/00286 , H03L7/0814
摘要： A delay circuit including a plurality of interpolators connected in cascade. Each of the interpolators receives a reference clock signal and a clock signal output from the preceding interpolator. One of the interpolators generates a clock signal whose transition edge is between the transition edge of the reference clock signal and the transition edge of the clock signal. The subsequent interpolators operate as delay stages, thereby generating a delayed clock signal delaying from the reference clock signal by a predetermined time. It is possible to make smaller the minimum unit of a delay adjustment to the delayed clock signal by using the interpolators. A semiconductor integrated circuit including the delay circuit supplies ratio information to the phase adjustment circuits based on the result of comparing the phase of the reference clock signal with the phase of the delayed clock signal from a phase comparator and makes the phase of the delayed clock signal coincide with the phase of the reference clock signal. As a result, the phase adjustment can be made with reliability even when a reference clock signal of higher frequency is supplied.
摘要翻译：包括级联连接的多个内插器的延迟电路。每个内插器接收从前一个插值器输出的参考时钟信号和时钟信号。其中一个内插器产生一个时钟信号，该时钟信号的过渡沿位于参考时钟信号的过渡沿和时钟信号的过渡沿之间。随后的内插器作为延迟级操作，由此产生延迟的时钟信号从参考时钟信号延迟预定时间。通过使用内插器，可以使延迟时钟信号的延迟调整的最小单位更小。包括延迟电路的半导体集成电路基于将参考时钟信号的相位与来自相位比较器的延迟时钟信号的相位进行比较的结果向相位调整电路提供比率信息，并使延迟的时钟信号的相位与参考时钟信号的相位一致。结果，即使提供较高频率的参考时钟信号，也可以进行相位调整。

53. 发明授权

US06320819B2 Semiconductor device reconciling different timing signals 有权
公开(公告)号：US06320819B2
公开(公告)日：2001-11-20
申请号：US09733961
申请日：2000-12-12
申请人： Hiroyoshi Tomita , Tatsuya Kanda
发明人： Hiroyoshi Tomita , Tatsuya Kanda
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1072 , G11C8/00 , G11C8/04 , G11C8/18
摘要： A semiconductor device which receives addresses in synchronism with a clock signal and receives data in synchronism with a strobe signal includes address-latch circuits, a first control circuit which selects one of the address-latch circuits in sequence in response to the clock signal, and controls the selected one of the address-latch circuits to latch a corresponding one of the addresses in response to the clock signal, and a second control circuit which selects one of the address-latch circuits in sequence in response to the strobe signal, and controls the selected one of the address-latch circuits to output a corresponding one of the addresses in response to the strobe signal.

54. 发明授权

US06318707B1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06318707B1
公开(公告)日：2001-11-20
申请号：US09536467
申请日：2000-03-28
申请人： Kota Hara , Hiroyoshi Tomita , Naoharu Shinozaki
发明人： Kota Hara , Hiroyoshi Tomita , Naoharu Shinozaki
IPC分类号： G11C800
CPC分类号： G11C7/1084 , G11C7/1051 , G11C7/106 , G11C7/1069 , G11C7/109 , G11C7/22 , G11C7/225
摘要： A semiconductor integrated circuit device includes a clock buffer circuit receiving a clock signal, a data buffer circuit receiving a data signal, an output circuit outputting the data signal from the data buffer circuit in accordance with the clock signal from the clock buffer circuit, and an adjustment circuit adjusting timings of the clock signal and the data signals.
摘要翻译：一种半导体集成电路装置，包括接收时钟信号的时钟缓冲电路，接收数据信号的数据缓冲电路，根据来自时钟缓冲器电路的时钟信号从数据缓冲电路输出数据信号的输出电路，以及调整电路调整时钟信号和数据信号的定时。

55. 发明授权

US06295245B1 Write data input circuit 有权
标题翻译：写数据输入电路
公开(公告)号：US06295245B1
公开(公告)日：2001-09-25
申请号：US09385004
申请日：1999-08-27
申请人： Hiroyoshi Tomita , Tatsuya Kanda
发明人： Hiroyoshi Tomita , Tatsuya Kanda
IPC分类号： G11C1300
CPC分类号： G11C7/109 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C11/4096
摘要： A write data input circuit for a double data rate (DDR) SDRAM acquires write data at both a rising and falling edge of a clock signal. The input circuit includes a command input buffer for receiving external commands, such as a read, write or refresh command. An external command latch circuit connected to the input buffer latches the external command in sync with a first clock signal. A decoder decodes the latched external command. A write determination circuit also receives the (undecoded) external command and generates an enable signal if the external command is a write command. A data input buffer is activated by the enable signal and receives write data. A data latch circuit latches the write data provided to the data input buffer in sync with a second clock signal.
摘要翻译：双数据速率（DDR）SDRAM的写数据输入电路在时钟信号的上升沿和下降沿都获取写数据。输入电路包括用于接收诸如读取，写入或刷新命令的外部命令的命令输入缓冲器。连接到输入缓冲器的外部命令锁存电路与第一时钟信号同步地锁存外部指令。解码器解码锁定的外部命令。如果外部命令是写命令，则写入确定电路还接收（未解码）外部命令并产生使能信号。数据输入缓冲器由使能信号激活并接收写入数据。数据锁存电路与第二时钟信号同步地锁存提供给数据输入缓冲器的写入数据。

56. 发明授权

US06242954B1 Timing clock generation circuit using hierarchical DLL circuit 有权
标题翻译：定时时钟生成电路采用分层DLL电路
公开(公告)号：US06242954B1
公开(公告)日：2001-06-05
申请号：US09385010
申请日：1999-08-27
申请人： Nobutaka Taniguchi , Hiroyoshi Tomita
发明人： Nobutaka Taniguchi , Hiroyoshi Tomita
IPC分类号： H04L708
CPC分类号： H03L7/0814 , G06F1/10 , H03L7/0818 , H03L7/087
摘要： The present invention has a hierarchical DLL circuit comprising a rough DLL circuit for phase adjustment by rough delay unit and a fine DLL circuit for phase adjustment by smaller, fine delay unit. When phase adjustment begins, only the rough DLL circuit operates; when the rough DLL circuit locks on, phase adjustment by the rough DLL circuit ends and the delay amount of the rough DLL circuit is set. When the rough DLL circuit locks on, the fine DLL circuit is caused to operate. In this way, the phase of the timing clock generated by the DLL circuit is adjusted only by fine delay units even if the phase of the reference clock is temporarily shifted by a large amount due to power source noise or the like. Consequently, in the event of temporary phase shifting, the amount of jitter in the timing clock can be suppressed to the small amount of a fine delay unit. Phase adjustment by the rough DLL circuit is stopped by ending phase comparison by the phase comparison circuit, or ending the input of the clock to the phase comparison circuit, for example.
摘要翻译：本发明具有分级DLL电路，其包括用于通过粗略延迟单元进行相位调整的粗略DLL电路和用于通过较小的精细延迟单元进行相位调整的精细DLL电路。当相位调整开始时，只有粗略的DLL电路运行; 当粗体DLL电路锁定时，粗体DLL电路的相位调整结束，并设置粗略电路的延迟量。当粗体DLL电路锁定时，使细小的DLL电路工作。以这种方式，即使由于电源噪声等而使参考时钟的相位暂时移位了大量，由DLL电路产生的定时时钟的相位仅被微调延迟单元调整。因此，在临时相移的情况下，可以将定时时钟中的抖动量抑制到微小的延迟单元的量。例如，通过由相位比较电路结束相位比较或将时钟的输入结束到相位比较电路来停止粗略DLL电路的相位调整。

57. 发明授权

US6075393A Clock synchronous semiconductor device system and semiconductor devices used with the same 失效
标题翻译：时钟同步半导体器件系统和使用的半导体器件
公开(公告)号：US6075393A
公开(公告)日：2000-06-13
申请号：US998478
申请日：1997-12-29
申请人： Hiroyoshi Tomita , Yoshihiro Takemae
发明人： Hiroyoshi Tomita , Yoshihiro Takemae
IPC分类号： G11C11/413 , G06F1/10 , G06F12/00 , G11C7/00 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , H03K5/135 , H03L7/081 , H03L7/00
CPC分类号： G11C7/222 , G11C7/1078 , G11C7/22 , H03L7/0812
摘要： A clock synchronous semiconductor device system and semiconductor devices used with the system have the read and write operations performed at a proper timing without increasing the types of clock or the amount of wiring. The system includes a plurality of semiconductor devices operated in synchronism with a clock. One of the semiconductor devices operates as a controller for producing a signal related to the controlling of the remaining semiconductor devices. A clock signal line for transmitting a clock to each semiconductor device is arranged in parallel with the other signal lines. A clock source is arranged at a position far from the controller not to cause any skew when the read data arrive at the controller from the remaining semiconductor devices. The timing at which each memory retrieves the write data from the controller is adjusted by an input timing adjusting circuit included in each memory, thereby permitting each memory to retrieve the write data at an optimum timing.
摘要翻译：与系统一起使用的时钟同步半导体器件系统和半导体器件具有在适当的定时执行的读和写操作，而不增加时钟的类型或布线的数量。该系统包括与时钟同步操作的多个半导体器件。其中一个半导体器件用作用于产生与其余半导体器件的控制有关的信号的控制器。用于将时钟发送到每个半导体器件的时钟信号线与其他信号线并联布置。当远离控制器的位置处的时钟源被布置在读取数据从其余半导体器件到达控制器时不会产生任何偏斜。通过每个存储器中包括的输入定时调整电路调整每个存储器从控制器检索写数据的定时，从而允许每个存储器在最佳定时检索写数据。

58. 发明授权

US6066969A Semiconductor device with DLL circuit avoiding excessive power consumption 有权
标题翻译：具有DLL电路的半导体器件避免功耗过大
公开(公告)号：US6066969A
公开(公告)日：2000-05-23
申请号：US130168
申请日：1998-08-06
申请人： Kenichi Kawasaki , Yasuharu Sato , Hiroyoshi Tomita
发明人： Kenichi Kawasaki , Yasuharu Sato , Hiroyoshi Tomita
IPC分类号： G06F1/10 , G11C11/407 , G11C11/4076 , H01L27/00 , H03K5/13 , H03L7/00 , H03L7/081 , H03L7/06
CPC分类号： H03L7/0805 , H03L7/0814
摘要： A semiconductor device includes a variable-delay circuit which delays an input-clock signal to generate a delay clock signal, a clock-control circuit which selects one of the input-clock signal and the delayed clock signal, an output circuit which outputs data in synchronism with a clock signal selected by the clock-control circuit, and a DLL circuit which adjusts a delay of the variable-delay circuit. The DLL circuit includes a delay-control circuit which adjusts the delay of the variable-delay circuit, and a clock-selection circuit which controls the clock-control circuit to select one of the input-clock signal and the delayed clock signal. The variable-delay circuit is controlled such that the delay is not increased when the input-clock signal is selected by the clock-selection circuit.
摘要翻译：一种半导体器件包括延迟输入时钟信号以产生延迟时钟信号的可变延迟电路，选择输入时钟信号和延迟时钟信号之一的时钟控制电路，输出电路，输出数据与由时钟控制电路选择的时钟信号的同步，以及调整可变延迟电路的延迟的DLL电路。 DLL电路包括调整可变延迟电路的延迟的延迟控制电路和控制时钟控制电路以选择输入时钟信号和延迟的时钟信号之一的时钟选择电路。控制可变延迟电路，使得当时钟选择电路选择输入时钟信号时，延迟不增加。

59. 发明授权

US5912858A Clock-synchronized input circuit and semiconductor memory device that utilizes same 失效
标题翻译：时钟同步输入电路和利用其的半导体存储器件
公开(公告)号：US5912858A
公开(公告)日：1999-06-15
申请号：US1649
申请日：1997-12-31
申请人： Hiroyoshi Tomita , Yuji Kurita
发明人： Hiroyoshi Tomita , Yuji Kurita
IPC分类号： G11C11/413 , G06F1/12 , G06F13/42 , G11C7/10 , G11C7/22 , G11C11/407 , G11C11/409 , H04L7/00 , G11C8/00 , G11C7/00
CPC分类号： G11C7/1093 , G11C7/1072 , G11C7/1078 , G11C7/22
摘要： A semiconductor memory device, to which a plurality of command signals are supplied in synchronous with a clock, comprises a plurality of input circuits, having a sampling unit for inputting said command signals and said clock and sampling said command signals in synchronous with said clock, and an output unit for outputting said sampled command signals; a command decoder for receiving the command signals output by said plurality of input circuits, decoding said plurality of command signals and generating a corresponding control signal; a memory element, which implements a variety of operational modes in response to said control signals; an output timing signal generator circuit, having a circuit architecture equivalent to at least the sampling unit of said input circuit, for sampling a predetermined signal level in synchronous with said clock, and for generating an output timing signal based on the timing of the operational delay time of said sampling unit; and wherein said input circuit outputs said sampled command signals in response to said output timing signal.
摘要翻译：与时钟同步地供给多个命令信号的半导体存储器件包括多个输入电路，具有用于输入所述命令信号和所述时钟的采样单元，并与所述时钟同步地对所述命令信号进行采样，以及输出单元，用于输出所述采样的指令信号; 命令解码器，用于接收由所述多个输入电路输出的命令信号，解码所述多个命令信号并产生相应的控制信号; 存储元件，其响应于所述控制信号实现各种操作模式; 输出定时信号发生器电路，具有与至少所述输入电路的采样单元相当的电路结构，用于与所述时钟同步地采样预定信号电平，并且用于基于所述操作延迟的定时产生输出定时信号所述采样单元的时间; 并且其中所述输入电路响应于所述输出定时信号而输出所述采样的指令信号。

60. 发明授权

US5896347A Semiconductor memory system using a clock-synchronous semiconductor device and semiconductor memory device for use in the same 失效
标题翻译：使用时钟同步半导体器件的半导体存储器系统和用于其的半导体存储器件
公开(公告)号：US5896347A
公开(公告)日：1999-04-20
申请号：US925458
申请日：1997-09-08
申请人： Hiroyoshi Tomita , Yoshihiro Takemae
发明人： Hiroyoshi Tomita , Yoshihiro Takemae
IPC分类号： G11C11/413 , G11C7/10 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/409 , H03L7/00 , G11C8/00
CPC分类号： G11C7/1093 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222
摘要： A semiconductor memory system using a synchronous memory and operating at a higher speed due to a reduced margin required when reading data from the SDRAM, and a semiconductor memory device for achieving the same are disclosed. The semiconductor memory system comprises at least one semiconductor memory device and a control device for performing data input/output to and from the semiconductor memory device, wherein the control device outputs data to be stored in the semiconductor memory device, synchronously with a first synchronizing signal that the control device outputs, and the semiconductor memory device delivers output data therefrom synchronously with a second synchronizing signal that the semiconductor memory device outputs. In the thus constructed semiconductor memory system, the semiconductor memory device incorporates an output phase shift circuit which introduces a prescribed phase angle between the output data and second synchronizing signal, and provisions are made so that at the semiconductor memory device side the output data and the second synchronizing signal are controlled precisely at the prescribed phase angle with respect to each other, and so that a latch pulse can be immediately generated at the controller side upon reception of a data strobe signal.
摘要翻译：公开了一种使用同步存储器并且由于在从SDRAM读取数据时所需的余量减小而以更高速度工作的半导体存储器系统，以及用于实现其的半导体存储器件。半导体存储器系统包括至少一个半导体存储器件和用于对半导体存储器件进行数据输入/输出的控制器件，其中控制器件与第一同步信号同步地输出要存储在半导体存储器件中的数据控制装置输出，半导体存储装置与半导体存储装置输出的第二同步信号同步地输出输出数据。在这样构成的半导体存储器系统中，半导体存储器件包括在输出数据和第二同步信号之间引入规定相位角的输出移相电路，并且在半导体存储器件侧进行输出数据和第二同步信号相对于彼此精确地以规定的相位角被控制，并且使得在接收数据选通信号时可以在控制器侧立即产生锁存脉冲。

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