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51. 发明申请

US20110047355A1 Offset Based Register Address Indexing 审中-公开
标题翻译：基于偏移的寄存器地址索引
公开(公告)号：US20110047355A1
公开(公告)日：2011-02-24
申请号：US12546071
申请日：2009-08-24
申请人： Eric O. Mejdrich , Adam J. Muff , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Adam J. Muff , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/30
CPC分类号： G06F9/342 , G06F9/30098 , G06F9/30185 , G06F9/3851
摘要： A circuit arrangement and method support offset based register address indexing, wherein register addresses to be used by an instruction are calculated using offsets to the full target register address, and the offsets are contained in the instruction and occupy less instruction space than the full address widths. An instruction may include at least one offset value that identifies a register address. During decoding of the instruction, an offset and a full target address are retrieved from the instruction, and then a register address is calculated by addition of the offset to the full target address.
摘要翻译：电路布置和方法支持基于偏移的寄存器地址索引，其中由指令使用的寄存器地址使用对全目标寄存器地址的偏移来计算，并且偏移量包含在指令中并占据比全地址宽度少的指令空间。指令可以包括标识寄存器地址的至少一个偏移值。在指令解码期间，从指令中检索偏移量和完整目标地址，然后通过将补偿相加到完整目标地址来计算寄存器地址。

52. 发明授权

US07814303B2 Execution of a sequence of vector instructions preceded by a swizzle sequence instruction specifying data element shuffle orders respectively 有权
标题翻译：执行一系列向量指令，之前是分别指定数据元素随机顺序的交换序列指令
公开(公告)号：US07814303B2
公开(公告)日：2010-10-12
申请号：US12256550
申请日：2008-10-23
申请人： Adam J. Muff , Robert A. Shearer , Matthew R. Tubbs
发明人： Adam J. Muff , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/315
CPC分类号： G06F9/30036 , G06F9/30032 , G06F9/30145 , G06F9/3851
摘要： Operand vector multiplexer sequence control is used in a vector-based execution unit to control the shuffling of data elements in operand vectors used by a sequence of vector instructions processed by the vector-based execution unit. A swizzle sequence instruction is defined in an instruction set for the vector-based execution unit and is used to selectively apply a sequence of vector data element shuffle orders to one or more operand vectors to be used by the associated sequence of vector instructions. As a result, when a common sequence of data element shuffle orders is used frequently for a sequence of vector instructions, a single swizzle sequence instruction may be used to select the desired sequence of custom data element ordering for each of the vector instructions in the sequence.
摘要翻译：操作数向量复用器序列控制在基于向量的执行单元中用于控制由基于向量的执行单元处理的向量指令序列使用的操作数向量中的数据元素的混洗。在用于基于矢量的执行单元的指令集中定义了一个旋转序列指令，并且用于向量数据元素洗牌顺序的一个或多个操作数向量选择性地应用以由相关的向量指令序列使用。结果，当对于一系列向量指令频繁使用数据元素随机顺序的公共序列时，可以使用单个交换序列指令来选择序列中每个向量指令的定制数据元素排序的期望序列。

53. 发明申请

US20100191939A1 TRIGONOMETRIC SUMMATION VECTOR EXECUTION UNIT 失效
标题翻译： TRIGONOMETRIC建立矢量执行单元
公开(公告)号：US20100191939A1
公开(公告)日：2010-07-29
申请号：US12360243
申请日：2009-01-27
申请人： Adam J. Muff , Matthew R. Tubbs
发明人： Adam J. Muff , Matthew R. Tubbs
IPC分类号： G06F9/302
CPC分类号： G06F7/485 , G06F7/49936 , G06F7/509 , G06F7/5443 , G06F7/548 , G06F9/30014 , G06F2207/3828
摘要： A unique instruction and exponent adjustment adder selectively shift outputs from multiple execution units, including a plurality of multipliers, in a processor core in order to scale mantissas for related trigonometric functions used in a vector dot product.
摘要翻译：独特的指令和指数调整加法器在处理器核心中选择性地将来自多个执行单元（包括多个乘法器）的输出移位，以缩放用于矢量点积中的相关三角函数的尾数。

54. 发明授权

US08719455B2 DMA-based acceleration of command push buffer between host and target devices 失效
标题翻译：主机和目标设备之间基于DMA的加速命令推送缓冲区
公开(公告)号：US08719455B2
公开(公告)日：2014-05-06
申请号：US12824674
申请日：2010-06-28
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F3/00 , G06F13/28
CPC分类号： G06F13/28
摘要： Direct Memory Access (DMA) is used in connection with passing commands between a host device and a target device coupled via a push buffer. Commands passed to a push buffer by a host device may be accumulated by the host device prior to forwarding the commands to the push buffer, such that DMA may be used to collectively pass a block of commands to the push buffer. In addition, a host device may utilize DMA to pass command parameters for commands to a command buffer that is accessible by the target device but is separate from the push buffer, with the commands that are passed to the push buffer including pointers to the associated command parameters in the command buffer.
摘要翻译：直接存储器访问（DMA）用于在通过推送缓冲器耦合的主机设备和目标设备之间传递命令。由宿主设备传递到推送缓冲器的命令可以在将命令转发到推送缓冲器之前被主机设备累积，使得可以使用DMA来共同地将一组命令传递给推送缓冲器。此外，主机设备可以利用DMA将用于命令的命令参数传递给目标设备可访问但与推送缓冲区分离的命令缓冲区，其中传递到推送缓冲器的命令包括指向相关命令的指针命令缓冲区中的参数。

55. 发明授权

US08692825B2 Parallelized streaming accelerated data structure generation 失效
标题翻译：并行流加速数据结构生成
公开(公告)号：US08692825B2
公开(公告)日：2014-04-08
申请号：US12822427
申请日：2010-06-24
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G09G5/00
CPC分类号： G06T15/06 , G06T2200/28 , G06T2210/52
摘要： A method includes receiving at a master processing element primitive data that includes properties of a primitive. The method includes partially traversing a spatial data structure that represents a three-dimensional image to identify an internal node of the spatial data structure. The internal node represents a portion of the three-dimensional image. The method also includes selecting a slave processing element from a plurality of slave processing elements. The selected processing element is associated with the internal node. The method further includes sending the primitive data to the selected slave processing element to traverse a portion of the spatial data structure to identify a leaf node of the spatial data structure.
摘要翻译：一种方法包括在主处理元件处接收包括原语的属性的原始数据。该方法包括部分地遍历表示三维图像以识别空间数据结构的内部节点的空间数据结构。内部节点表示三维图像的一部分。该方法还包括从多个从属处理元件中选择从属处理元件。所选择的处理元件与内部节点相关联。该方法还包括将原始数据发送到所选择的从属处理元件以遍历空间数据结构的一部分以识别空间数据结构的叶节点。

56. 发明授权

US08514232B2 Propagating shared state changes to multiple threads within a multithreaded processing environment 有权
标题翻译：将共享状态更改传播到多线程处理环境中的多个线程
公开(公告)号：US08514232B2
公开(公告)日：2013-08-20
申请号：US12824778
申请日：2010-06-28
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F15/80
CPC分类号： G06F12/0813 , G06T15/005
摘要： A circuit arrangement and method make state changes to shared state data in a highly multithreaded environment by propagating or streaming the changes to multiple parallel hardware threads of execution in the multithreaded environment using an on-chip communications network and without attempting to access any copy of the shared state data in a shared memory to which the parallel threads of execution are also coupled.
摘要翻译：电路布置和方法通过使用片上通信网络在多线程环境中传播或将变化传播或传输到多个并行硬件执行线程而不尝试访问任何副本，从而使状态对高度多线程环境中的共享状态数据进行改变并行线程执行的共享存储器中的共享状态数据也被耦合。

57. 发明申请

US20130145128A1 PROCESSING CORE WITH PROGRAMMABLE MICROCODE UNIT 有权
标题翻译：加工核心与可编程微控制器
公开(公告)号：US20130145128A1
公开(公告)日：2013-06-06
申请号：US13311809
申请日：2011-12-06
申请人： Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/30 , G06F9/312
CPC分类号： G06F9/22 , G06F9/24 , G06F9/328 , G06F9/3851
摘要： A method and circuit arrangement utilize a programmable microcode unit that is capable of being programmed via software to modify the instruction sequences output by the microcode unit in response to microcode instructions issued to the microcode unit. Among other benefits, a programmable microcode unit consistent with the invention enables customization of a processor design to handle specific applications or tasks, as well as to support specific hardware configurations such as specific execution units. In addition, a programmable microcode unit may be updatable, e.g., to correct bugs or faults found in previous instruction sequences supported by the unit.
摘要翻译：一种方法和电路装置利用可编程的微码单元，该可编程微码单元能够通过软件进行编程，以便响应于发出到微代码单元的微码指令来修改由微代码单元输出的指令序列。除了其他优点之外，与本发明一致的可编程微代码单元使得能够定制处理器设计以处理特定应用或任务，以及支持特定硬件配置，例如特定执行单元。此外，可编程微代码单元可以是可更新的，例如，以校正由该单元支持的先前指令序列中发现的错误或故障。

58. 发明申请

US20130044117A1 VECTOR REGISTER FILE CACHING OF CONTEXT DATA STRUCTURE FOR MAINTAINING STATE DATA IN A MULTITHREADED IMAGE PROCESSING PIPELINE 有权
标题翻译：用于维护多图像处理管道中状态数据的上下文数据结构的矢量寄存器文件
公开(公告)号：US20130044117A1
公开(公告)日：2013-02-21
申请号：US13212418
申请日：2011-08-18
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06T1/20 , G06F9/02 , G06F15/76
CPC分类号： G06F9/30 , G06F9/38 , G06F9/383 , G06T1/20
摘要： Frequently accessed state data used in a multithreaded graphics processing architecture is cached within a vector register file of a processing unit to optimize accesses to the state data and minimize memory bus utilization associated therewith. A processing unit may include a fixed point execution unit as well as a vector floating point execution unit, and a vector register file utilized by the vector floating point execution unit may be used to cache state data used by the fixed point execution unit and transferred as needed into the general purpose registers accessible by the fixed point execution unit, thereby reducing the need to repeatedly retrieve and write back the state data from and to an L1 or lower level cache accessed by the fixed point execution unit.
摘要翻译：在多线程图形处理架构中使用的经常访问的状态数据被缓存在处理单元的向量寄存器文件中，以优化对状态数据的访问并最小化与其相关联的存储器总线利用。处理单元可以包括固定点执行单元以及向量浮点执行单元，并且向量浮点执行单元使用的向量寄存器文件可用于对由固定点执行单元使用的状态数据进行缓存并转移为需要进入由固定点执行单元访问的通用寄存器，从而减少了从固定点执行单元访问的L1或更低级高速缓存重复检索和回写状态数据的需要。

59. 发明申请

US20120176364A1 REUSE OF STATIC IMAGE DATA FROM PRIOR IMAGE FRAMES TO REDUCE RASTERIZATION REQUIREMENTS 失效
标题翻译：从先前的图像框架中减少静态图像数据以减少放射性要求
公开(公告)号：US20120176364A1
公开(公告)日：2012-07-12
申请号：US12985607
申请日：2011-01-06
申请人： Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs , Eric O. Mejdrich
发明人： Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs , Eric O. Mejdrich
IPC分类号： G06T15/00
CPC分类号： G09G5/393 , G06T1/60 , G06T15/005 , G06T15/20 , G06T15/405 , G09G5/39
摘要： An apparatus, program product and method reuse static image data generated during rasterization of static geometry to reduce the processing overhead associated with rasterizing subsequent image frames. In particular, static image data generated one frame may be reused in a subsequent image frame such that the subsequent image frame is generated without having to re-rasterize the static geometry from the scene, i.e., with only the dynamic geometry rasterized. The resulting image frame includes dynamic image data generated as a result of rasterizing the dynamic geometry during that image frame, and static image data generated as a result of rasterizing the static image data during a prior image frame.
摘要翻译：一种装置，程序产品和方法重用在静态几何的光栅化期间产生的静态图像数据，以减少与后续图像帧的光栅化相关联的处理开销。特别地，生成一帧的静态图像数据可以在随后的图像帧中重新使用，使得生成后续图像帧，而不必从场景重新光栅化静态几何，即仅光栅化动态几何。所得到的图像帧包括作为在该图像帧期间光栅化动态几何结果而生成的动态图像数据，以及作为在先前图像帧期间对静态图像数据进行光栅化而产生的静态图像数据。

60. 发明申请

US20100269123A1 Performance Event Triggering Through Direct Interthread Communication On a Network On Chip 失效
标题翻译：通过芯片上网络直接通信的性能事件触发
公开(公告)号：US20100269123A1
公开(公告)日：2010-10-21
申请号：US12427090
申请日：2009-04-21
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/54
CPC分类号： H04L43/0817
摘要： Performance event triggering through direct interthread communication (‘DITC’) on a network on chip (‘NOC’), the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, including enabling performance event monitoring in a selected set of IP blocks distributed throughout the NOC, each IP block within the selected set of IP blocks having one or more event counters; collecting performance results from the one or more event counters; and returning performance results from the one or more event counters to a destination repository, the returning being initiated by a triggering event occurring within the NOC.
摘要翻译：通过芯片上的直接线间通信（“DITC”）触发的性能事件，NOC包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器和网络接口控制器适配于路由器，其中每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器进行IP间块通信的每个网络接口控制器，包括在分配在整个NOC上的所选择的一组IP块，所选择的一组IP块中的每个IP块具有一个或多个事件计数器; 从一个或多个事件计数器收集性能结果; 并将性能结果从一个或多个事件计数器返回到目的地存储库，返回由在NOC内发生的触发事件发起。

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